DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 11/17/2025. Claims 1-8, 21-27 & 30-32 are pending in this application. Claims 9-20, 28 & 29 are canceled.
Claim Objections
2. The claims are objected because of the following reasons:
Re claim 1, line 13: in front (2x) “topmost surface”, delete (2x) “a” and insert (2x) --the--.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2018/0277681) in view of Schaetz et al. (US 2021/0035882) and Hsieh et al. (US 2018/0174904).
Re claim 1, Lin teaches, Figs. 10A-12C, 16B, 16C, 17B, 17C, 21B & 21C, [0022, 0027, 0035, 0037, 0042, 0044, 0053], a method for manufacturing a semiconductor device, the method comprising:
-forming a source/drain region (82) on a semiconductor fin (56), the source/drain region (84) being adjacent to a dummy gate (70);
-after forming the source/drain region, forming a first interlayer dielectric (ILD) (88) over the source/drain region (82) and the dummy gate (70), the first ILD (88) having a dielectric constant of 3.5 or less (e.g., BSG);
-forming an opening (90) by removing the dummy gate (70);
-depositing a gate structure (gate electrode 94, mask 104) in the opening, wherein a topmost surface of the gate structure (94, 104) is coplanar with a topmost surface of the first ILD (88) (16B);
-forming a source/drain contact (112) electrically contacting the source/drain region (82) and extending through the first ILD (88), a topmost surface of the source/drain contact (112) being coplanar with a topmost surface of the gate structure (94, 104) and with a topmost surface of the first ILD (88) (Fig.17B); and
-after forming the source/drain contact (112), depositing a first etch stop layer (metallic nitride 136) on the first ILD (88) and the gate structure (94, 104) (Fig. 21B).
Note: Supported by US 2010/0059895, BSG having dielectric constant of 3.5 [0059].
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Lin does not explicitly teach the first ILD comprises boron nitride.
Schaetz teaches the first ILD (13) comprises boron nitride [0064].
As taught by Schaetz, one of ordinary skill in the art would utilize & modify the above teaching into Lin to obtain/achieve the first ILD comprising boron nitride as claimed, because it aids in improving thermal performance in a power semiconductor device. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Schaetz in combination with Lin due to above reason.
Lin/Schaetz does not teach forming a second dielectric layer overlying the first etch stop layer and the first ILD.
Hsieh teaches, Fig. 7, [0020-0021], forming a second dielectric layer (64) overlying the first etch stop layer (62) and the first ILD (40).
As taught by Hsieh, one of ordinary skill in the art would utilize & modify the above teaching to obtain a second dielectric layer as claimed, because it aids in enhancing protection and achieving desired device dimension.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Khaderbad in combination with Lin/Schaetz due to above reason.
Re claim 6, in combination cited above, Hsieh teaches, Fig. 13, [0014, 0015, 0026], depositing another etch stop layer (76 or 38) to cover and contact the source/drain region (42).
4. Claim(s) 2 and 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as modified by Schaetz/Hsieh as applied to claim 1 above, and further in view of You (US 2015/0171147).
The teachings of Lin/Schaetz/Hsieh have been discussed above.
Re claims 2 & 3, Lin/Schaetz/Hsieh does not teach forming the first ILD comprises a plasma process using capacitive coupling plasma (claim 2); and using inductive coupling plasma (claim 3).
You teaches “The inorganic insulating layer is patterned by a dry etching process, and in this case, inductive coupled plasma (ICP) or enhanced capacitive coupled plasma (ECCP) may be used (utilized) as the plasma.” [0086].
As taught by You, one of ordinary skill in the art would utilize & modify the above teaching to form the first ILD comprising a plasma process using capacitive coupling plasma, and using inductive coupling plasma as claimed, because it aids in achieving high quality thin film with minimize damage.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by You in combination with Lin/Schaetz/Hsieh due to above reason.
5. Claim(s) 4 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as modified by Schaetz/Hsieh as applied to claim 1 above, and further in view of Murakami et al. (WO 2021/193237).
The teachings of Lin/Schaetz/Hsieh have been discussed above.
Re claims 4 & 5, Lin/Schaetz/Hsieh does not teach forming the first ILD comprising using borazine as process gas; and using boron trichloride and nitrogen as process gas.
Murakami teaches forming the first ILD comprising using borazine as process gas (B3N); and using boron trichloride and nitrogen (e.g., boron trichloride and ammonia) as process gas (Step 7, pages 6-7).
As taught by Murakami, one of ordinary skill in the art would utilize & modify the above teaching to form the first ILD comprising using borazine as process gas; and using boron trichloride and nitrogen as process gas as claimed, because those materials are known in the art to form boron nitride film. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Murakami in combination with Lin/Schaetz/Hsieh due to above reason.
6. Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as modified by Schaetz/Hsieh as applied to claim 1 above, and further in view of Khaderbad et al. (2021/0184018).
The teachings of Lin/Schaetz/Hsieh have been discussed above.
Re claim 7, in combination cited above, Hsieh teaches, Fig. 13, forming a second etch stop layer (76) over the second dielectric layer (64), the second etch stop layer (76) being in physical contact with the second dielectric layer (64); and
forming a third dielectric layer (78) over the second etch stop layer (76), the third dielectric layer (78) being in physical contact with the second etch stop layer (76).
Lin/Shaetz/Hsieh does not explicitly teach a dielectric constant of 3.5 or less and a dielectric constant of 3.9 or greater.
Khaderbad teaches materials having a dielectric constant of 3.5 or less and a dielectric constant of 3.9 or greater [0052-0053].
As taught by Khaderbad, one of ordinary skill in the art would utilize & modify the above teaching to obtain materials of the second dielectric layer and third dielectric layer as claimed, because it aids in improving the device performance. Further, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended used a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Khaderbad in combination with Lin/Schaetz/Hsieh due to above reason.
Re claim 8, in combination cited above, Hsieh teaches, Fig. 13, [0026] forming a second etch stop layer (76) over the second dielectric layer (64); and forming a third dielectric layer (78) over the second etch stop layer (76); and Khaderbad teaches dielectric layer having a dielectric constant of 3.9 or greater and dielectric layer having a dielectric constant of 3.5 or less [0052, 0053].
Allowable Subject Matter
7. Claims 21-27 & 30-32 are allowed.
The allowable subject matters include steps of:
“depositing a boron nitride first interlayer dielectric (ILD) over the source/drain region and the dummy gate using a plasma deposition process wherein the plasma deposition process is selected from the group consisting of capacitive coupling plasma and inductive coupling plasma, the first ILD having a dielectric constant of 3.5 or less;
forming an opening in the first ILD by removing the dummy gate;
forming a metal gate structure in the opening;
forming a first contact extending through the first ILD and contacting the source/drain region;
depositing over the first ILD and over the first contact a second dielectric layer, the second dielectric layer having a dielectric constant of 3.5 or less; and
forming a second contact and a third contact extending through the second dielectric layer, the second contact contacting the first contact and the third contact contacting the metal gate structure” (claim 21); and
“depositing a first boron nitride interlayer dielectric (ILD) over the source/drain region and the dummy gate structure, the first boron nitride ILD having a dielectric constant value, the dielectric constant value being in a range of from 2.o to 3.5, wherein the first boron nitride ILD is deposited using a plasma deposition process using a precursor gas selected from the group consisting of borazine and boron trichloride;
planarizing a top surface of the first boron nitride ILD to expose a top surface of the dummy gate structure;
removing the dummy gate structure and forming in its place a metal gate structure; and
depositing a protective dielectric layer over the first boron nitride ILD, the protective dielectric layer having a dielectric constant value in a range of from 2.0 to 3.5;
forming a mask structure over the protective dielectric layer;
patterning the mask structure in a first patterning step to form a patterned mask structure having a pattern opening exposing the protective dielectric layer;
patterning the protective dielectric layer exposed by the pattern opening in a second patterning step separate from the first patterning step to form a patterned protective dielectric layer; and
etching openings in the first boron nitride ILD using the patterned protective dielectric layer as an etch mask” (claim 27).
Response to Arguments
8. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Conclusion
9. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 12/1/25
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