DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed March 6, 2026. Claims 1, 11, and 16 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-20 are pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, and 16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1, 11, and 16, all the claims recite a limitation related to “a purge gas associated with an outgassing process of the wafer”. It is unclear in what way the purge gas is associated with the outgassing process.
Claims 2-10, 12-15, and 17-20 depend upon claims 1, 11, and 16 and do not rectify the problem. Therefore, they are rejected on at least the same basis.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Clark et al. (US 20200083080 A1) herein after “Clark” in view of Ye et al. (US 20070099438 A1) herein after “Ye” and Rebstock (US 20130004270 A1).
Regarding claim 1, Figs. 4 and 13A-13E of Clark disclose a system, comprising:
a second chamber (Fig. 4, second processing module 420b, ¶ [0123]) configured to deposit a passivation layer (Figs. 13B-13D, SAM 1308, ¶ [0262]) on the wafer (Figs. 13A-13E, workpiece 1300, ¶ [0260]) (“the second processing module 420b might form a self-aligned monolayer (SAM) on a workpiece”, ¶ [0124]);
a third chamber (Fig. 4, fourth processing module 420d, ¶ [0123]) configured to deposit a target layer (Figs. 13C-13E, film 1310, ¶ [0264]) on the wafer (1300) (“the fourth processing module 420d may deposit a film on a workpiece by a suitable deposition process”, ¶ [0124]);
a fourth chamber (Fig. 4, third processing module 420c, ¶ [0123]) configured to etch the passivation layer (Fig. 13E, “the SAM 1308 may be removed from the workpiece, for example by etching”, ¶ [0269]) from the wafer (1300) (“The third processing module 420c may etch or clean a workpiece”, ¶ [0124]);
a transport mechanism (Fig. 4, “the transfer module defines a chamber therein that houses a transfer robot”, ¶ [0113]) configured to move the wafer (1300) between two or more of: the first chamber (420a), the second chamber (420b), the third chamber (420d), and the fourth chamber (420c) (“transfer module 412 is configured for transferring substrates between any of the substrate processing chambers 420a-420d”, ¶ [0125]);
a buffer (Fig. 4, substrate metrology module 416, ¶ [0124]) comprising a sealed chamber configured to receive the wafer between processes of the system (“transferring substrates between any of the substrate processing chambers 420a-420d and then into the substrate metrology module 416 either before or after a particular processing step”, ¶ [0124]);
wherein the buffer (416) includes:
a residual gas analyzer (RGA) (“the metrology module may include one or more inspection systems “, “The measurement modules and/or inspections systems may include… residual gas analyzers”, ¶ [0116] and [0121]) within the buffer (416)
a mainframe (Fig. 4, platform 400, ¶ [0114]) enclosing the first chamber (Fig. 4, first processing module 420a, ¶ [0123]), the second chamber (420b), the third chamber (420d), the fourth chamber (420c), the buffer (416), and the transport mechanism (“transfer robot”) and configured to maintain a vacuum environment (“the wafer is processed in platform 400 and measured without leaving vacuum”, ¶ [0117]) during movement of the wafer (1300) between the buffer (416), the first chamber (420a), the second chamber (420b), the third chamber (420d), and the fourth chamber (420c).
Fig. 4 of Clark further discloses a first chamber (420a) that “might perform a treatment process on a workpiece”, ¶ [0124], but fails to explicitly disclose that the chamber is configured to perform a cleaning process on a wafer;
the RGA configured to detect concentrations, humidity, and pressure within the buffer; and
a purge pump configured to provide a purge gas associated with an outgassing process of the wafer, wherein the purge pump is configured to operate at a higher speed when contaminant concentrations or humidity increase in the buffer based on detection by the RGA.
In the similar field of endeavor of semiconductor device fabrication, Fig. 3 of Ye discloses a first chamber (Fig. 3, chamber 106d, ¶ [0028]) configured to perform a cleaning process on a wafer (“the wafer may be transferred … to a suitable preclean chamber such as the chamber 106d”, ¶ [0028]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the treatment process disclosed by Clark by adding the cleaning process disclosed by Ye, to reduce contamination (see Ye, ¶ [0023]).
Ye fails to disclose the RGA configured to detect concentrations, humidity, and pressure; and
a purge pump configured to provide a purge gas associated with an outgassing process of the wafer, wherein the purge pump is configured to operate at a higher speed when contaminant concentrations or humidity increase in the buffer based on detection by the RGA.
In the similar field of endeavor of semiconductor fabrication, Fig. 2A of Rebstock discloses the RGA configured to detect concentrations, humidity, and pressure (“A sensor, such as a RGA (residue gas analyzer), can also be included to monitor levels of contamination of the object”, ¶ [0041]); and
a purge pump (Fig. 2A, pumping line 29B, ¶ [0041]) configured to provide a purge gas (Fig. 2A, purge gas 29A, ¶ [0041]) associated with an outgassing process of the wafer (“The pumped/purge process can be a vacuum pumping for outgassing, which follows by a clean gas purge”, ¶ [0046]), wherein the purge pump is configured to operate at a higher speed when contaminant concentrations or humidity increase in the buffer (Fig. 2A, decontamination chamber 20, ¶ [0042]) based on detection by the RGA (“The time for decontamination can set predetermined, or can be set by the level of contaminants observed by the sensor 27”, ¶ [0042]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the treatment process disclosed by Clark by adding the residual gas analyzer and purge process as disclosed by Rebstock, to reduce contamination (see Rebstock, ¶ [0036]).
Regarding claim 3, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Fig. 4 of Clark further discloses wherein at least one pump (“pumping system”, ¶ [0088]) and the mainframe (400) are configured to maintain the vacuum environment at least at 10-7 torr (“The exemplary platform 400 represents a plurality of processing modules organized in a common manufacturing platform around the periphery of workpiece transfer module 412”, “The workpiece transfer module 412 may be maintained at a very low base pressure (e.g., 5×10−8 Torr, or lower)”, ¶ [0115-0116]).
Regarding claim 4, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, Figs. 4 and 13A-13E of Clark further disclose wherein the transport mechanism (“transfer robot”) comprises one or more robotic arms configured to grasp, move, and release the wafer (1300) (“the transfer module defines a chamber therein that houses a transfer robot that is capable of moving substrates, under vacuum, through various gate valves and access or transfer ports into various processing modules or measurement modules”, ¶ [0114]).
Regarding claim 5, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Fig. 4 of Clark discloses wherein the first chamber (420a), the second chamber (420b), the third chamber (420d), and the fourth chamber (420c) configured to maintain a vacuum (“processing chambers and tools, and overall manufacturing platforms to be utilized before, during or after processing, in a vacuum environment”, ¶ [0078]), but fails to explicitly disclose the vacuum is at least at 10-10 torr.
In the similar field of endeavor of semiconductor device fabrication, Fig. 3 of Ye discloses wherein the first chamber (106d), the second chamber (106e), the third chamber (106a), and the fourth chamber (106n) configured to maintain a vacuum at least at 10-10 torr (“one or more of the deposition chambers 106a, 106b . . . 106n may have associated therewith a pump which combines a turbomolecular pump and a cryogenic pump to generate an ultra high vacuum in that chamber”, ¶ [0019]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the system of Clark with the vacuum level as disclosed by Ye, to reduce contaminants (see Ye, ¶ [0028]).
Regarding claim 6, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Figs. 4 and 10D of Clark further disclose wherein the first chamber (420a), the fourth chamber (“The third processing module 420c may etch or clean a workpiece”, ¶ [0123], “etch chamber 1083”, ¶ [0195]), or a combination thereof include a nozzle configured to inject gas (“gas-phase dispensing or distributing system (e.g., 1085a, 1085b, 1086)”, ¶ [0195]).
Regarding claim 7, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Fig. 4 of Clark discloses a first chamber (420a), but fails to disclose that the first chamber includes a nozzle configured to inject gas.
In the similar field of endeavor of semiconductor device fabrication, Fig. 3 of Ye discloses wherein the first chamber (106d) includes a nozzle configured to inject gas (“prior to removing the cleaned wafer from the chamber 106d, gasses may be pumped from or into the chambers 106d”, ¶ [0029]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the system of Clark to include gas injection as disclosed by Ye, to change the pressure in the chamber before transferring (see Ye, ¶ [0029]).
Regarding claim 8, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Figs. 4 and 10D of Clark further disclose wherein the first chamber (420a), the fourth chamber (“The third processing module 420c may etch or clean a workpiece”, ¶ [0123], “etch chamber 1083”, ¶ [0195]), or a combination thereof include a remote plasma system configured to inject plasma (“etching module may include a plasma etching module “, “a power source 1084 (e.g., RF power source) for generating plasma in the etch chamber 1083”, ¶ [0195]).
Regarding claim 9, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Figs. 4 and 10D of Clark further disclose wherein the first chamber (420a), the fourth chamber (“The third processing module 420c may etch or clean a workpiece”, ¶ [0123], “etch chamber 1083”, ¶ [0195]), or a combination thereof receive plasma from a direct plasma system configured to generate plasma (“etching module may include a plasma etching module “, “a power source 1084 (e.g., RF power source) for generating plasma in the etch chamber 1083”, ¶ [0195]).
Regarding claim 10, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, and Figs. 4 and 10C of Clark further disclose wherein the second chamber (420b), the third chamber (“the fourth processing module 420d may deposit a film on a workpiece by a suitable deposition process”, ¶ [0123], “film-forming module 1070 might include a vacuum deposition chamber”, ¶ [0194]), or a combination thereof receive precursor materials from an ampoule storage system (1074) and a nozzle (1078) configured to inject the precursor materials (“a liquid source bubbler 1078 that can be coupled to a liquid dispensing system 1074 for providing the proper material phase into the chamber 1072 such as a deposition chamber”, ¶ [0194]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Clark (US 20200083080 A1), Ye (US 20070099438 A1) and Rebstock (US 20130004270 A1) in further view of Lin (US 20200135509 A1).
Regarding claim 2, Clark, Ye and Rebstock together disclose the system of claim 1 as applied above, but the combination fails to disclose one or more pumps, included in the buffer, configured to provide an air curtain between the buffer and one or more of the first chamber, the second chamber, the third chamber, or the fourth chamber.
In the similar field of endeavor of semiconductor device manufacturing systems, Fig. 1 of Lin discloses one or more pumps (Fig. 1, gas curtain devices 120A-120B, ¶ [0026]), included in the buffer (Fig. 1, transfer module 105, ¶ [0018]), configured to provide an air curtain (Fig. 1, “gas curtain devices 120A-120B can be configured to form a localized gas stream (e.g., gas curtain)”, ¶ [0026]) between the buffer (105) and one or more of the first chamber, the second chamber, the third chamber, or the fourth chamber (Fig. 1, “Such gas curtain can impede an inflow of residue gas (e.g., oxygen or moisture) from transfer module 105 to processing chambers 102A-102B”, ¶ [0026]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the system of Clark with the gas curtain as disclosed by Lin, to increase yield and reliability of manufacturing (see Lin, ¶ [0017]).
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Clark (US 20200083080 A1) in view of Ye (US 20070099438 A1), Rebstock (US 20130004270 A1) and Rothberg et al. (US 20180326412 A1) herein after “Rothberg”.
Regarding claim 11, Figs. 4 and 13A-13E of Clark disclose a method, comprising:
providing a wafer (1300) into a mainframe (400) of a system, wherein the mainframe (400) is configured to maintain a vacuum environment (“The workpieces being processed remain under vacuum”, ¶ [0078]);
moving the wafer (1300) to a buffer (416) of the system in the mainframe (400) under vacuum (“the measurement module 416 is kept at vacuum conditions and the wafer is processed in platform 400 and measured without leaving vacuum”, ¶ [0116]);
moving the wafer (1300) (“the workpiece transfer module transfers the workpiece between the plurality of processing modules”, ¶ [0107]) to a second chamber (420b) of the system in the mainframe (400) under vacuum (“The workpieces being processed remain under vacuum”, ¶ [0078]);
forming the passivation layer (1308) on the wafer (1300) in the second chamber (420b) (“the second processing module 420b might form a self-aligned monolayer (SAM) on a workpiece”, ¶ [0123]);
moving the wafer (1300) (“the workpiece transfer module transfers the workpiece between the plurality of processing modules”, ¶ [0107]) to a third chamber (420d) of the system in the mainframe (400) under vacuum (“The workpieces being processed remain under vacuum”, ¶ [0078]);
forming the target layer (1310) on the wafer (1300) in the third chamber (420d) (“the fourth processing module 420d may deposit a film on a workpiece by a suitable deposition process”, ¶ [0123]);
moving the wafer (1300) (“the workpiece transfer module transfers the workpiece between the plurality of processing modules”, ¶ [0107]) to a fourth chamber (420c) of the system in the mainframe (400) under vacuum (“The workpieces being processed remain under vacuum”, ¶ [0078]); and
etching the passivation layer (1308) in the fourth chamber (420c) (“The third processing module 420c may etch or clean a workpiece”, ¶ [0123]).
Clark fails to disclose performing a cleaning process on the wafer in a first chamber of the system;
providing a purge gas in the buffer, wherein the purge gas is associated with an outgassing process of the wafer; and
wherein the passivation layer comprises a first anchor group that attaches to metal by exhibiting hydrophilic properties and a second anchor group that repels other materials by exhibiting hydrophobic properties.
In the similar field of endeavor of semiconductor device fabrication, Fig. 3 of Ye discloses performing a cleaning process (“the substrate 206 is cleaned prior (that is, precleaned) to subsequent deposition operations”, ¶ [0028]) on the wafer (206) in a first chamber (“a suitable preclean chamber such as the chamber 106d”, ¶ [0028]) of the system (100).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by adding the cleaning process disclosed by Ye, to reduce contamination (see Ye, ¶ [0023]).
Ye fails to disclose providing a purge gas in the buffer, wherein the purge gas is associated with an outgassing process of the wafer; and
wherein the passivation layer comprises a first anchor group that attaches to metal by exhibiting hydrophilic properties and a second anchor group that repels other materials by exhibiting hydrophobic properties.
In the similar field of endeavor of semiconductor fabrication, Fig. 2A of Rebstock discloses providing a purge gas (29A) in the buffer (20), wherein the purge gas associated with an outgassing process of the wafer (“The pumped/purge process can be a vacuum pumping for outgassing, which follows by a clean gas purge”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the treatment process disclosed by Clark by adding the purge process as disclosed by Rebstock, to reduce contamination (see Rebstock, ¶ [0036]).
Rebstock fails to disclose wherein the passivation layer comprises a first anchor group that attaches to metal by exhibiting hydrophilic properties and a second anchor group that repels other materials by exhibiting hydrophobic properties.
In the similar field of substrate surface preparation, Fig. 3 of Rothberg discloses the passivation layer (Fig. 3, coating layer 310, ¶ [0054]) comprises a first anchor group (Fig. 3, hydrophilic head group 316 , ¶ [0054]) that attaches to metal by exhibiting hydrophilic properties (“a hydrophilic head group 316 that preferentially binds the metal oxide surface 302”, ¶ [0054]) and a second anchor group (Fig. 3, hydrophobic tail 314, ¶ [0054]) that repels other materials by exhibiting hydrophobic properties (“interactions with the hydrophobic tail groups 314 of the coating layer 310 based on the hydrophobic effect”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by adding the first and second anchor groups disclosed by Rothberg, to improve binding selectivity (see Rothberg, ¶ [0051]).
Regarding claim 14, Clark, Ye, Rebstock and Rothberg together disclose the method of claim 11 as applied above, and Figs. 13A-13E of Clark further disclose wherein the passivation layer (1308) comprises a nitrogen-based head-group, a sulfur-based head-group, a phosphorus-based head-group, a triazole derivative, a thiol, or a thiol derivative (“the head group of the molecule forming the SAM can include a thiol, a silane, or a phosphonate”, ¶ [0261]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Clark (US 20200083080 A1), Ye (US 20070099438 A1), Rebstock (US 20130004270 A1) and Rothberg (US 20180326412 A1) in further view of Tapily (US 20210202244 A1).
Regarding claim 12, Clark, Ye, Rebstock and Rothberg together disclose the method of claim 11 as applied above, but Clark, Ye, Rebstock and Rothberg fail to disclose wherein the cleaning process uses a hydrogen gas, argon gas, helium gas, hydrogen plasma, argon plasma, helium plasma, or a combination thereof.
In the similar field of endeavor of semiconductor manufacturing, Fig. 1 of Tapily discloses wherein the cleaning process (“performing a treatment process or cleaning process on the substrate 200”, ¶ [0032]) uses a hydrogen gas, argon gas, helium gas, hydrogen plasma, argon plasma, helium plasma, or a combination thereof (“The treating can, for example, include exposure to plasma-excited H.sub.2 gas, plasma-excited Ar gas, substrate heating, or a combination thereof. The treating can include exposure to process gases (e.g., NH.sub.3, N.sub.2H.sub.4, CO, or H.sub.2)”, ¶ [0032]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by incorporating the cleaning process disclosed by Tapily, to remove impurities and contaminants (see Tapily, ¶ [0032]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Clark (US 20200083080 A1), Ye (US 20070099438 A1), Rebstock (US 20130004270 A1) and Rothberg (US 20180326412 A1) in further view of Dutta et al. (US 20200144107 A1) herein after “Dutta”.
Regarding claim 13, Clark, Ye, Rebstock and Rothberg together disclose the method of claim 11 as applied above, but Clark, Ye, Rebstock and Rothberg fail to disclose wherein the target layer comprises a nitride, a metal, or a combination thereof.
In the similar field of endeavor of integrated circuits, Fig. 7 of Dutta discloses wherein the target layer (Fig. 7, barrier layer 150, ¶ [0045]) comprises a nitride, a metal, or a combination thereof (“The barrier layer 150 can comprise a metal-containing material such as, for example, TaN, TiN”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by incorporating the target layer as disclosed by Dutta, to prevent diffusion (see Dutta, ¶ [0032]).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Clark (US 20200083080 A1), Ye (US 20070099438 A1), Rebstock (US 20130004270 A1) and Rothberg (US 20180326412 A1) in further view of Hausmann et al. (US 20240030062 A1) herein after “Hausmann”.
Regarding claim 15, Clark, Ye, Rebstock and Rothberg together disclose the method of claim 11 as applied above, but Clark, Ye, Rebstock and Rothberg fail to disclose wherein the passivation layer comprises an alkyne of the form RC≡CR' or an alkene of the RC=CR', wherein R is Hx or CxHy.
In the similar field of endeavor of processing semiconductor substrates, Fig. 5 of Hausmann discloses wherein the passivation layer (Fig. 5, “in an operation 599 of the process 500, an inhibitor layer is deposited on the exposed barrier surface”, ¶ [0072]) comprises an alkyne of a form RC≡CR' or an alkene of a form RC=CR', wherein R is Hx or CxHy (“the inhibitor layer includes molecules having a hydrocarbon group. In some embodiments, the hydrocarbon group is one or more of alkanes, alkenes, and alkynes.”, ¶ [0008], “The inhibitor layer may include molecules having a CxHy head group”, ¶ [0073]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by incorporating the passivation layer disclosed by Hausmann, to inhibit deposition on certain surfaces (see Hausmann, ¶ [0071]).
Claims 16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 20240183028 A1) herein after “Xie” in view of Rebstock (US 20130004270 A1), Rothberg (US 20180326412 A1) and Naik et al. (US 20150262869 A1) herein after “Naik”.
Regarding claim 16, Figs. 3-6 of Xie disclose a method, comprising:
cleaning a wafer (Fig. 4, substrate 302, ¶ [0032]) having a metal layer (Fig. 4, embedded copper contact 306, ¶ [0032]), at least one etch stop layer (ESL) (Fig. 4, intermediate layer 310, ¶ [0032]), and a dielectric layer (Fig. 4, first low-k dielectric layer 308, ¶ [0032]), wherein the dielectric layer (308) includes a recessed portion such that the metal layer (306) is at least partially exposed (shown in Fig. 3);
forming a passivation layer (Fig. 6, blocking layer 602, ¶ [0034]) on an exposed portion of the metal layer (306), wherein the passivation layer (602) is formed without disturbing a vacuum environment surrounding the wafer (302) (“The blocking layer is formed without an air break between the precleaning process and the formation of the blocking layer”, ¶ [0034]); and
forming a target layer (barrier layer, ¶ [0034]) on sidewalls of the recessed portion, wherein the passivation layer (602) prevents formation of the target layer (barrier layer, ¶ [0034]) on a bottom surface of the recessed portion (“The blocking layer 602 is used in subsequent selective reverse ALD processes to form barrier layers (not shown) on the side walls and non-contact surfaces of the via 318. The blocking layer 602 prevents formation of the barrier layer on the bottom of the via, keeping the contact free from material.”, ¶ [0034]).
Xie fails to explicitly disclose providing a purge gas associated with an outgassing process of the wafer;
wherein the passivation layer comprises a first anchor group that attaches to metal by exhibiting hydrophilic properties and a second anchor group that repels other materials by exhibiting hydrophobic properties;
wherein the target layer is formed without disturbing the vacuum environment surrounding the wafer; and
etching the passivation layer from the wafer, wherein the passivation layer is etched without disturbing the vacuum environment surrounding the wafer.
In the similar field of endeavor of semiconductor fabrication, Fig. 2A of Rebstock discloses providing a purge gas (29A) associated with an outgassing process of the wafer (“The pumped/purge process can be a vacuum pumping for outgassing, which follows by a clean gas purge”, ¶ [0046]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the treatment process disclosed by Clark by adding the purge process as disclosed by Rebstock, to reduce contamination (see Rebstock, ¶ [0036]).
Rebstock fails to disclose wherein the passivation layer comprises a first anchor group that attaches to metal by exhibiting hydrophilic properties and a second anchor group that repels other materials by exhibiting hydrophobic properties;
wherein the target layer is formed without disturbing the vacuum environment surrounding the wafer; and
etching the passivation layer from the wafer, wherein the passivation layer is etched without disturbing the vacuum environment surrounding the wafer.
In the similar field of substrate surface preparation, Fig. 3 of Rothberg discloses the passivation layer (310) comprises a first anchor group (316) that attaches to metal by exhibiting hydrophilic properties (“a hydrophilic head group 316 that preferentially binds the metal oxide surface 302”, ¶ [0054]) and a second anchor group (314) that repels other materials by exhibiting hydrophobic properties (“interactions with the hydrophobic tail groups 314 of the coating layer 310 based on the hydrophobic effect”, ¶ [0054]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Clark by adding the first and second anchor groups disclosed by Rothberg, to improve binding selectivity (see Rothberg, ¶ [0051]).
Rothberg fails to disclose wherein the target layer is formed without disturbing the vacuum environment surrounding the wafer; and
etching the passivation layer from the wafer, wherein the passivation layer is etched without disturbing the vacuum environment surrounding the wafer.
In the similar field of endeavor of semiconductor manufacturing, Figs. 8A-8C of Naik disclose wherein the target layer (Fig. 8C, capping layer 808, ¶ [0150]) is formed without disturbing the vacuum environment (“all these process steps, when manufacturing the interconnection structures of 8A-8C, may also be manufactured in the processing system 500 depicted in FIG. 5 without breaking vacuum”, ¶ [0150]) surrounding the wafer (Fig. 8A, substrate 801, ¶ [0150]); and
etching (Fig. 8B, “an etching process may be performed to remove the liner layer 802”, ¶ [0150]) the passivation layer (Figs. 8A-8B, liner layer 802, ¶ [0150]) from the wafer (801), wherein the passivation layer (802) is etched without disturbing the vacuum environment surrounding the wafer (“all these process steps, when manufacturing the interconnection structures of 8A-8C, may also be manufactured in the processing system 500 depicted in FIG. 5 without breaking vacuum”, ¶ [0150]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Xie with etching the passivation layer and maintaining vacuum as disclosed by Naik, to expose the contact and avoid exposing the substrate to ambient atmosphere (see Naik, ¶ [0150]).
Regarding claim 18, Xie, Rebstock, Rothberg and Naik together disclose the method of claim 16 as applied above, but Xie, Rebstock and Rothberg fail to disclose wherein etching the passivation layer includes plasma striking, thermal annealing, or a combination thereof.
In the similar field of endeavor of semiconductor manufacturing, Figs. 8A-8C of Naik disclose wherein etching (“an etching process may be performed to remove the liner layer 802”, ¶ [0150]) the passivation layer (802) includes plasma striking, thermal annealing, or a combination thereof (“While supplying the etching gas mixture to perform the remote plasma source etching process, a substrate temperature may be maintained at a range of between about 40 degrees Celsius and about 150 degrees Celsius”, ¶ [0128]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the method disclosed by Xie with etching the passivation layer as disclosed by Naik, to expose the contact (see Naik, ¶ [0150]).
Regarding claim 19, Xie, Rebstock, Rothberg and Naik together disclose the method of claim 16 as applied above, and Fig. 4 of Xie discloses wherein cleaning the wafer (302) reduces metal oxide (“cleaning process will continue until the residue or oxide has been removed from the embedded copper contact 306”, ¶ [0033]) at the exposed portion of the metal layer (306).
Regarding claim 20, Xie, Rebstock, Rothberg and Naik together disclose the method of claim 16 as applied above, and Fig. 6 of Xie discloses wherein the passivation layer (602) comprises a dry self-assembling monolayer (“The SAM precursor 604 is selected such that the SAM precursor aligns (builds a monolayer) on the given metal used for the contact such as the embedded copper contact 306 to form a blocking layer 602”, ¶ [0034]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Xie (US 20240183028 A1), Rebstock (US 20130004270 A1), Rothberg (US 20180326412 A1) and Naik (US 20150262869 A1) in further view of Clark (US 20200083080 A1).
Regarding claim 17, Xie, Rebstock, Rothberg and Naik together disclose the method of claim 16 as applied above, and Fig. 1 of Xie further discloses a controller that “enables data collection and feedback”, ¶ [0030], but Xie, Rebstock, Rothberg and Naik do not explicitly disclose scanning the wafer to determine one or more parameters associated with cleaning the wafer, forming the passivation layer, forming the target layer, or etching the passivation layer.
In the similar field of endeavor of semiconductor processing, Figs. 13A-13C of Clark disclose scanning the wafer (Fig. 13A, substrate 1300, ¶ [0246]) to determine one or more parameters associated with cleaning the wafer (1300), forming the passivation layer (Fig. 13B, SAM 1308, ¶ [0262]), forming the target layer (Fig. 13C, film 1310, ¶ [0264]), or etching the passivation layer (1308) (“the inspection system is operable to measure one or more of the following workpiece attributes: a layer thickness, a layer conformality, a layer coverage, a layer profile…”, ¶ [0015]).
It would have been obvious to one of ordinary skill in the art at the time of effective filing of the invention to modify the data collection disclosed by Xie to include the method as disclosed by Clark, to monitor the state or condition of the workpiece for process control purposes (see Clark, ¶ [0015]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORALIE NETTLES whose telephone number is (571)270-5374. The examiner can normally be reached Mon-Fri. 7:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights