DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed April 9, 2026. Claims 1, 7, and 26 have been amended. Claim 28 has been added. Claim 9 has been canceled. Currently, claims 1-4, 6-8, 10-15, 21-23, and 25-28 are pending.
Response to Arguments
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Applicant asserts that the Office Action does not illustrate how the cited references teach or suggest the claimed features without providing specific claimed features that are not disclosed by the references. The Examiner respectfully disagrees with this assertion, and directs Applicant to the detailed citations with explanatory parentheticals accompanying every limitation in view of the applied art in the previous Office Action, which are maintained and repeated herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-8, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20170222008 A1) herein after “Hsu” in view of Maeda et al. (US 20220068706 A1) herein after “Maeda” and Wang et al. (US 20180301371 A1) herein after “Wang”.
Regarding claim 1, Figs. 1A-9 of Hsu disclose a method comprising:
forming a gate structure (Figs. 1A-1B, metal gate structures 10, ¶ [0016]) over a substrate (Figs. 1A-1B, substrate 1, ¶ [0016]) (Figs. 1A-1B, “metal gate structures 10 are formed over a channel layer, for example, a part of a fin structure 5”, ¶ [0016]);
forming a gate spacer (Fig. 1B, sidewall spacers 30, ¶ [0016]) along a sidewall of the gate structure (10) (Fig. 1B, “Sidewall spacers 30 are provided on sidewalls of the metal gate structure 10”, ¶ [0016]);
forming a source/drain region (Fig. 1B, source/drain (S/D) regions 50, ¶ [0016]) adjacent the gate structure (10) (Fig. 1B, “source/drain (S/D) regions 50 are formed adjacent to the gate structures”, ¶ [0016]);
forming a first interlayer dielectric (ILD) (Fig. 2, second ILD layer 60, ¶ [0031]) over the source/drain region (50) (Fig. 2, “a second ILD layer 60 is formed over the structure of FIG. 1B”, ¶ [0031]);
forming a contact plug (Fig. 4, first metal layer 75, ¶ [0033]) extending through the first ILD (60) that electrically contacts the source/drain region (50) (Fig. 4, “a first metal layer 75 is formed to cover the entire upper surface”, ¶ [0033]);
forming a silicide layer (Fig. 6, upper silicide layer 80, ¶ [0037]) on the contact plug (75) (Fig. 6, “an upper silicide layer 80 is formed on the upper surface of the first metal layer 75”, ¶ [0037]);
forming a second ILD (Figs. 7-8, ESL (etch stop layer) 90, third ILD layer 100, ¶ [0044]) extending over the first ILD (60) and the silicide layer (80) (Fig. 7, “an ESL (etch stop layer) 90 is formed over the silicide layer 80 and the second ILD layer 60”, ¶ [0044]), wherein the second ILD (90, 100) interfaces top surfaces of the first ILD (60) and the silicide layer (80);
etching an opening (Fig. 8, contact opening 109, ¶ [0046]) extending through the second ILD (90, 100) and the silicide layer (80) (Fig. 11C shows the contact 110 making direct contact with plug 75 through the silicide layer 80. Therefore, the opening 109 must have been etched through the silicide layer 80) to expose the contact plug (75) (Fig. 8, “a contact opening 109 is formed in the third ILD layer”, ¶ [0046]), wherein the silicide layer (80) is used as an etch stop during the etching of the opening (Fig. 8, “the etching operation to form the contact opening 109 stops on the silicide layer 80”, ¶ [0046]); and
forming a second conductive feature (Fig. 9, via plug 110, ¶ [0047]) in the opening (109) that electrically contacts the contact plug (75) (Fig. 9, “a via plug 110 is formed in the contact opening 109 so as to be electrically connected to the first metal layer 75”, ¶ [0047]), wherein top surfaces of the second conductive feature (110) and the second ILD (90, 100) are level.
Hsu fails to disclose wherein a bottom surface of the silicide layer is lower than a top surface of the gate spacer;
forming a first conductive feature penetrating the first ILD to interface the gate structure;
after forming the first conductive feature, etching an opening extending through the second ILD and the silicide layer to expose the contact plug, wherein the silicide layer is used as an etch stop during the etching of the opening.
In the similar field of endeavor of manufacturing semiconductor devices, Fig. 24 of Maeda discloses wherein a bottom surface of the silicide layer (Fig. 24, silicide layer SI, ¶ [0091]) is lower than a top surface of the gate spacer (Fig. 24, sidewall spacers SW, ¶ [0079]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method disclosed by Hsu to include the silicide layer as disclosed by Maeda, to simplify production and improve reliability (see Maeda, ¶ [0106]).
Maeda fails to disclose forming a first conductive feature penetrating the first ILD to interface the gate structure;
after forming the first conductive feature, etching an opening to expose the contact plug.
In the similar field of endeavor of transistor formation, Figs. 22-23 of Wang disclose forming a first conductive feature (Fig. 23, gate contact plug 104, ¶ [0046]) penetrating the first ILD (Fig. 23, ILD 68, ¶ [0034]) to interface the gate structure (Fig. 22, metallic material 60, ¶ [0030]);
after forming the first conductive feature (104), etching an opening (Fig. 23, contact opening 108, ¶ [0047]) to expose the contact plug (Fig. 23, metallic material 90, ¶ [0041]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method disclosed by Hsu to include forming the conductive features in subsequent steps as disclosed by Wang, to obtain the desired electrode properties (see Wang, ¶ [0048]) and/or because selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results (MPEP 2144.04IV.C).
Regarding claim 2, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, and Fig. 6 of Hsu further discloses wherein the silicide layer (80) comprises a cobalt silicide (Fig. 6, “a Co silicide layer 80”, ¶ [0039]).
Regarding claim 3, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, and Hsu further discloses wherein etching the opening (109) leaves the contact plug (75) free of the silicide layer (80) (“after the contact opening 109 is formed, the silicide layer 80 is removed”, ¶ [0050]).
Regarding claim 4, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, and Fig. 12 of Hsu further discloses wherein a top surface of the silicide layer (80) protrudes above a top surface of the first ILD (60) (Fig. 12, “the silicide layer 80 protrudes above the upper surface of the second ILD layer 60”, ¶ [0054]).
Regarding claim 6, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, but Hsu and Maeda fail to disclose further comprising depositing an etch stop layer on the second ILD.
In the similar field of endeavor of transistor formation, Fig. 26 of Wang discloses comprising depositing an etch stop layer (Fig. 26, etch stop layer 122, ¶ [0052]) on the second ILD (Fig. 26, dielectric layer (ILD) 96, ¶ [0042]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the etch stop layer disclosed by Wang, to allow for formation of subsequent interconnects (see Wang, ¶ [0052]).
Regarding claim 7, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, and Fig. 11C of Hsu further discloses wherein the silicide layer (80) laterally surrounds the second conductive feature (110) (Fig. 11C, “the via plug 110 passes through the silicide layer 80”, ¶ [0052]).
Regarding claim 8, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, and Fig. 9 of Hsu further discloses wherein the second ILD (90, 100) physically contacts the silicide layer (80) and the first ILD (60).
Regarding claim 28, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, but Hsu and Maeda fail to disclose wherein a bottom surface of the first conductive feature is lower than a bottom surface of the second conductive feature.
In the similar field of endeavor of transistor formation, Fig. 25 of Wang discloses wherein a bottom surface of the first conductive feature (104) is lower than a bottom surface of the second conductive feature (Fig. 25, conductive material 110/112, ¶ [0048]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the etch stop layer disclosed by Wang, to allow for formation of subsequent interconnects (see Wang, ¶ [0052]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method disclosed by Hsu to include forming the conductive features having different dimensions as disclosed by Wang, to obtain the desired electrode properties (see Wang, ¶ [0053]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20170222008 A1), Maeda (US 20220068706 A1) and Wang (US 20180301371 A1) in further view of Kim et al. (US 20180096935 A1) herein after “Kim”.
Regarding claim 26, Hsu, Maeda and Wang together disclose the method of claim 1 as applied above, but Hsu, Maeda and Wang fail to disclose the first conductive feature is free of the silicide layer.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 35 of Kim discloses the first conductive feature (Fig. 35, third contact plug 392, ¶ [0018]) is free of the silicide layer (Fig. 35, metal silicide pattern 336, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the gate contact as disclosed by Kim, to ensure electrical isolation of the contacts (see Kim, ¶ [0050]).
Allowable Subject Matter
Claims 10-15, 21-23, 25, and 27 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art of record alone or in combination fails to disclose or fairly suggest “after performing the first etching process, performing a second etching process to etch a second opening in the insulating layer, wherein the second etching process selectively etches the material of the insulating layer at a greater rate than the material of the silicide layer;
after performing the second etching process, performing a third etching process in the second opening, wherein the third etching process etches the silicide layer to extend the second opening through the silicide layer and expose the first conductive feature” in combination with the other limitations of claim 10.
Claims 11-15 are allowed based on their dependency on claim 10.
Regarding claim 21, the prior art of record alone or in combination fails to disclose or fairly suggest “forming a dielectric layer covering and interfacing a top surface of the epitaxial source/drain region;
forming a first contact plug extending through the dielectric layer to physically and electrically contacting the top surface of the epitaxial source/drain region;
forming a silicide layer on a top surface of the first contact plug, wherein the silicide layer directly contacts a sidewall of the dielectric layer” in combination with the other limitations of claim 21.
Claims 22-23, 25, and 27 are allowed based on their dependence on claim 21.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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