DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 4, 2025 has been entered.
Response to Amendment
This Office Action is in response to Applicant's amendments filed November 4, 2025. Claims 1, 10, and 21 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-4, 6-15, 21-23, and 25-27 are pending.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see pages 8-9, filed November 4, 2025, with respect to claim 21 have been fully considered and are persuasive. The rejection of claim 21 under 35 U.S.C. 102 has been withdrawn.
Applicant’s arguments, see pages 11-12, filed November 4, 2025, with respect to claim 10 have been fully considered and are persuasive. The rejection of claim 10 under 35 U.S.C. 103 has been withdrawn.
Applicant’s arguments with respect to the drawing objection are persuasive. The drawing objection outlined in the previous Office Action has been withdrawn.
Applicant’s arguments with respect to the 112(b) rejection of claim 14 are persuasive. The 112(b) rejection outlined in the previous Office Action has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al. (US 20170222008 A1) herein after “Hsu” in view of Maeda et al. (US 20220068706 A1) herein after “Maeda”.
Regarding claim 1, Figs. 1A-9 of Hsu disclose a method comprising:
forming a gate structure (Figs. 1A-1B, metal gate structures 10, ¶ [0016]) over a substrate (Figs. 1A-1B, substrate 1, ¶ [0016]) (Figs. 1A-1B, “metal gate structures 10 are formed over a channel layer, for example, a part of a fin structure 5”, ¶ [0016]);
forming a gate spacer (Fig. 1B, sidewall spacers 30, ¶ [0016]) along a sidewall of the gate structure (10) (Fig. 1B, “Sidewall spacers 30 are provided on sidewalls of the metal gate structure 10”, ¶ [0016]);
forming a source/drain region (Fig. 1B, source/drain (S/D) regions 50, ¶ [0016]) adjacent the gate structure (10) (Fig. 1B, “source/drain (S/D) regions 50 are formed adjacent to the gate structures”, ¶ [0016]);
forming a first interlayer dielectric (ILD) (Fig. 2, second ILD layer 60, ¶ [0031]) over the source/drain region (50) (Fig. 2, “a second ILD layer 60 is formed over the structure of FIG. 1B”, ¶ [0031]);
forming a contact plug (Fig. 4, first metal layer 75, ¶ [0033]) extending through the first ILD (60) that electrically contacts the source/drain region (50) (Fig. 4, “a first metal layer 75 is formed to cover the entire upper surface”, ¶ [0033]);
forming a silicide layer (Fig. 6, upper silicide layer 80, ¶ [0037]) on the contact plug (75) (Fig. 6, “an upper silicide layer 80 is formed on the upper surface of the first metal layer 75”, ¶ [0037]);
forming a second ILD (Figs. 7-8, ESL (etch stop layer) 90, third ILD layer 100, ¶ [0044]) extending over the first ILD (60) and the silicide layer (80) (Fig. 7, “an ESL (etch stop layer) 90 is formed over the silicide layer 80 and the second ILD layer 60”, ¶ [0044]), wherein the second ILD (90, 100) interfaces top surfaces of the first ILD (60) and the silicide layer (80);
etching an opening (Fig. 8, contact opening 109, ¶ [0046]) extending through the second ILD (90, 100) and the silicide layer (80) (Fig. 11C shows the contact 110 making direct contact with plug 75 through the silicide layer 80. Therefore, the opening 109 must have been etched through the silicide layer 80) to expose the contact plug (75) (Fig. 8, “a contact opening 109 is formed in the third ILD layer”, ¶ [0046]), wherein the silicide layer (80) is used as an etch stop during the etching of the opening (Fig. 8, “the etching operation to form the contact opening 109 stops on the silicide layer 80”, ¶ [0046]); and
forming a conductive feature (Fig. 9, via plug 110, ¶ [0047]) in the opening (109) that electrically contacts the contact plug (75) (Fig. 9, “a via plug 110 is formed in the contact opening 109 so as to be electrically connected to the first metal layer 75”, ¶ [0047]), wherein top surfaces of the conductive feature (110) and the second ILD (90, 100) are level.
Hsu fails to disclose wherein a bottom surface of the silicide layer is lower than a top surface of the gate spacer.
In the similar field of endeavor of manufacturing semiconductor devices, Fig. 24 of Maeda discloses wherein a bottom surface of the silicide layer (Fig. 24, silicide layer SI, ¶ [0091]) is lower than a top surface of the gate spacer (Fig. 24, sidewall spacers SW, ¶ [0079]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method disclosed by Hsu to include the silicide layer as disclosed by Maeda, to simplify production and improve reliability (see Maeda, ¶ [0106]).
Regarding claim 2, Hsu and Maeda together disclose the method of claim 1 as applied above, and Fig. 6 of Hsu further discloses wherein the silicide layer (80) comprises a cobalt silicide (Fig. 6, “a Co silicide layer 80”, ¶ [0039]).
Regarding claim 3, Hsu and Maeda together disclose the method of claim 1 as applied above, and Hsu further discloses wherein etching the opening (109) leaves the contact plug (75) free of the silicide layer (80) (“after the contact opening 109 is formed, the silicide layer 80 is removed”, ¶ [0050]).
Regarding claim 4, Hsu and Maeda together disclose the method of claim 1 as applied above, and Fig. 12 of Hsu further discloses wherein a top surface of the silicide layer (80) protrudes above a top surface of the first ILD (60) (Fig. 12, “the silicide layer 80 protrudes above the upper surface of the second ILD layer 60”, ¶ [0054]).
Regarding claim 7, Hsu and Maeda together disclose the method of claim 1 as applied above, and Fig. 11C of Hsu further discloses wherein the silicide layer (80) laterally surrounds the conductive feature (110) (Fig. 11C, “the via plug 110 passes through the silicide layer 80”, ¶ [0052]).
Regarding claim 8, Hsu and Maeda together disclose the method of claim 1 as applied above, and Fig. 9 of Hsu further discloses wherein the second ILD (90, 100) physically contacts the silicide layer (80) and the first ILD (60).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20170222008 A1) and Maeda (US 20220068706 A1) in further view of Wang et al. (US 20180301371 A1) herein after “Wang”.
Regarding claim 6, Hsu and Maeda together disclose the method of claim 1 as applied above, but Hsu and Maeda fail to disclose further comprising depositing an etch stop layer on the second ILD.
In the similar field of endeavor of transistor formation, Fig. 26 of Wang discloses comprising depositing an etch stop layer (Fig. 26, etch stop layer 122, ¶ [0052]) on the second ILD (Fig. 26, dielectric layer (ILD) 96, ¶ [0042]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the etch stop layer disclosed by Wang, to allow for formation of subsequent interconnects (see Wang, ¶ [0052]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20170222008 A1) and Maeda (US 20220068706 A1) in further view of Cheng et al. (US 20200075720 A1) herein after “Cheng”.
Regarding claim 9, Hsu and Maeda together disclose the method of claim 1 as applied above, but Hsu and Maeda fail to disclose further comprising forming a plurality of nanostructures over the substrate, wherein the gate structure surrounds each of the nanostructures of the plurality of nanostructures.
In the similar field of endeavor of semiconductor fabrication, Fig. 13 of Cheng discloses comprising forming a plurality of nanostructures (Fig. 13, active nanosheet channel layers 112, 114, and 116, ¶ [0038]) over the substrate (Fig. 13, semiconductor substrate 105, ¶ [0036]), wherein the gate structure (Fig. 13, gate dielectric layers 160, work function metal 162, ¶ [0065]) surrounds each of the nanostructures (112, 114, 116) of the plurality of nanostructures (112, 114, 116).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the nanostructures as disclosed by Cheng, to provide increased device width per footprint area (see Cheng, ¶ [0002]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Hsu (US 20170222008 A1) and Maeda (US 20220068706 A1) in further view of Kim et al. (US 20180096935 A1) herein after “Kim”.
Regarding claim 26, Hsu and Maeda together disclose the method of claim 1 as applied above, but Hsu and Maeda fail to disclose forming a gate contact extending through the second ILD to electrically contact the gate structure, wherein the gate contact is free of the silicide layer.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 35 of Kim discloses forming a gate contact (Fig. 35, third contact plug 392, ¶ [0018]) extending through the second ILD (Fig. 35, second insulating interlayer 360, ¶ [0044]) to electrically contact the gate structure (Fig. 35, gate structures 280, ¶ [0018]), wherein the gate contact is free of the silicide layer (Fig. 35, metal silicide pattern 336, ¶ [0043]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Hsu with the gate contact as disclosed by Kim, to ensure electrical isolation of the contacts (see Kim, ¶ [0050]).
Allowable Subject Matter
Claims 10-15, 21-23, 25, and 27 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 10, the prior art of record alone or in combination fails to disclose or fairly suggest “after performing the first etching process, performing a second etching process to etch a second opening in the insulating layer, wherein the second etching process selectively etches the material of the insulating layer at a greater rate than the material of the silicide layer;
after performing the second etching process, performing a third etching process in the second opening, wherein the third etching process etches the silicide layer to extend the second opening through the silicide layer and expose the first conductive feature” in combination with the other limitations of claim 10.
Claims 11-15 are allowed based on their dependency on claim 10.
Regarding claim 21, the prior art of record alone or in combination fails to disclose or fairly suggest “forming a dielectric layer covering and interfacing a top surface of the epitaxial source/drain region;
forming a first contact plug extending through the dielectric layer to physically and electrically contacting the top surface of the epitaxial source/drain region;
forming a silicide layer on a top surface of the first contact plug, wherein the silicide layer directly contacts a sidewall of the dielectric layer” in combination with the other limitations of claim 21.
Claims 22-23, 25, and 27 are allowed based on their dependence on claim 21.
Conclusion
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893