DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-8, 10-14, 21-24, and 26-29 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21-24 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US Publication No. 2020/0373402) in view of Frougier et al. (US Patent No. 9,947,804).
Regarding claim 21, Yang discloses a semiconductor device (Figure 7), comprising:
a plurality of nanostructures (115) on a substrate (210) comprising a bottommost nanostructure (lowest element 115)
a source/drain region (150/250) in contact with the plurality of nanostructures (115), comprising:
a first epitaxial structure (150dN) embedded in the substrate (210)
a nitride layer (155 is part of and connected to source/drain regions 150/250) embedded in the substrate (210) and on the first epitaxial structure (150dN)
a gate structure (120) formed on the plurality of nanostructures (115)
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Yang does not specifically disclose an entirety of the nitride layer is disposed below a top surface of the bottommost nanostructure. However, Frougier discloses an entirety of a nitride layer (130) is below a bottommost nanostructure (lowest nanosheet 116 of stack 114). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the nitride layer of Yang to be below a top surface of the bottommost nanostructure, as taught by Frougier, since it can protect the substrate and transistor sites in short channel regions (col. 17, lines 17-39).
Regarding claim 22, Frougier discloses the nitride layer (130/138) comprises silicon (col. 8, lines 12-34). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Yang et al. in view of Frougier et al.
Regarding claim 23, Yang discloses a plurality of inner spacers (140), wherein an inner spacer of the plurality of inner spacers is formed between adjacent nanostructures (115) of the plurality of nanostructures.
Regarding claim 24, Yang discloses the plurality of inner spacers (140) are alternately disposed on the plurality of nanostructures (115).
Regarding claim 29, Frougier discloses a portion of the topmost surface of the nitride layer (146) is disposed above a bottom surface of the bottommost nanostructure (lowest 114R) and a portion of a bottommost surface of the nitride layer (130/138) is disposed below a bottom surface of the bottommost nanostructure (114R) (Figure 21 left shows 146 above a top surface, and Figure 21 right shows 130 below a bottom surface). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Yang et al. in view of Frougier et al.
Claims 1-5, 10-14 and 26-28 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Publication No. 2021/0210349) in view of Frougier et al. (US Patent No. 9,947,804).
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As to claim 1, Xie teaches a semiconductor device (FIG. 13), comprising: a plurality of nanostructures (nanosheets 106; nanosheets 110; paragraphs [0035] and [0037], respectively) on a substrate (102); a source/drain region (bottom source/drain regions 130; dielectric isolation layer 132; top source/drain regions 134; paragraphs [0052], [0055], and [0056], respectively) in contact with the plurality of nanostructures (106; 110), comprising: a first epitaxial structure (130) on the substrate; a dielectric layer (132; [0055]) on the first epitaxial structure (130); and a second epitaxial structure (134) on the first epitaxial structure (130); and a gate structure (gate insulator 137; work function metal 138; work function metal 142; metal gate 144; paragraphs [0058], [0059], [0062], [0063] respectively) formed on the plurality of nanostructures (106; 110).
Yang does not specifically disclose an entirety of the nitride layer is disposed below a top surface of the bottommost nanostructure. However, Frougier discloses an entirety of a nitride layer (130) is below a bottommost nanostructure (lowest nanosheet 116 of stack 114). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the nitride layer of Yang to be below a top surface of the bottommost nanostructure, as taught by Frougier, since it can protect the substrate and transistor sites in short channel regions (col. 17, lines 17-39).
Regarding claim 2, Frougier discloses the nitride layer (130/138) comprises silicon (col. 8, lines 12-34). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Xie et al. in view of Frougier et al.
Regarding claim 3, Xie further teaches wherein the first epitaxial structure (130) and the second epitaxial structure (134) are formed using different materials (P-FET regions 130 will have different dopants than N-FET regions 134 per “Suitable dopants include, for example, an n-type dopant selected from a group of phosphorus (P), arsenic (As), and antimony (Sb), or a p-type dopant selected from a group of boron (B), gallium (Ga), indium (In), and thallium (TI) at various concentrations.” [0052]).
Regarding claim 4, Xie further teaches the device further comprising a plurality of inner spacers (128), wherein an inner spacer (128) of the plurality of inner spacers (128) is formed between adjacent nanostructures (106; 110) of the plurality of nanostructures (106; 110) (FIG. 13).
Regarding claim 5, Xie further teaches wherein the nitride layer (132) is in contact with an other inner spacer (128) of the plurality of inner spacers (128), wherein the other inner spacer (128) is formed between the substrate (102) and a nanostructure (106, 110) of the plurality of nanostructures (106, 110). The nitride layer (132) is in contact with an inner spacer (128) that exists between a nanostructure (110) and substrate (102). The nitride layer (132) is also in contact with the first epitaxial structure (130), which is in contact with an inner spacer (128) that exists between a nanostructure (106) and substrate (102), thus establishing indirect contact between nitride layer (132) and that inner spacer (128). The nitride layer (132) is also in contact with the second epitaxial structure (134), which is in contact with an inner spacer (128) that exists between a nanostructure (110) and substrate (102), thus establishing indirect contact between nitride layer (132) and that inner spacer (128).
Regarding claim 10, Xie further teaches wherein the second epitaxial structure (134) is in contact with the plurality of nanostructures (110) (FIG. 13).
As to claim 11, Xie teaches a semiconductor device (FIG. 13), comprising: a plurality of nanostructures (106; 110); a gate dielectric layer (137) around a nanostructure (106; 110) (See FIG. 12) of the plurality of nanostructures (106; 110); a gate electrode (138; 142; 144) disposed on the gate dielectric layer (137) and on the plurality of nanostructures (106; 110); and a source/drain region (130; 132; 134) in contact with the plurality of nanostructures (106; 110), comprising: a first epitaxial structure (130) on the substrate; a dielectric layer (132; [0055]) on the first epitaxial structure (130); and a second epitaxial (134) structure on the first epitaxial structure (130).
Yang does not specifically disclose an entirety of the nitride layer is disposed below a top surface of the bottommost nanostructure. However, Frougier discloses an entirety of a nitride layer (130) is below a bottommost nanostructure (lowest nanosheet 116 of stack 114). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have modified the nitride layer of Yang to be below a top surface of the bottommost nanostructure, as taught by Frougier, since it can protect the substrate and transistor sites in short channel regions (col. 17, lines 17-39).
Regarding claim 12, Frougier discloses the nitride layer (130/138) comprises silicon (col. 8, lines 12-34). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Xie et al. in view of Frougier et al.
Regarding claim 13, Xie further teaches the device further comprising a plurality of inner spacers (128), wherein an inner spacer (128) of the plurality of inner spacers (128) is formed between adjacent nanostructures (106; 110) of the plurality of nanostructures (106; 110) (FIG. 13).
Regarding claim 14, Xie further teaches wherein the nitride layer (132) is in contact with an other inner spacer (128) of the plurality of inner spacers (128), wherein the other inner spacer (128) is formed between the substrate (102) and a nanostructure (106, 110) of the plurality of nanostructures (106, 110). Examiner implements the interpretation of claim 14 to mean the same substrate referred to in claim 11, as described in the 112(b) rejection of claim 14 above. The nitride layer (132) is in contact with an inner spacer (128) that exists between a nanostructure (110) and substrate (102). The nitride layer (132) is also in contact with the first epitaxial structure (130), which is in contact with an inner spacer (128) that exists between a nanostructure (106) and substrate (102), thus establishing indirect contact between nitride layer (132) and that inner spacer (128). The nitride layer (132) is also in contact with the second epitaxial structure (134), which is in contact with an inner spacer (128) that exists between a nanostructure (110) and substrate (102), thus establishing indirect contact between nitride layer (132) and that inner spacer (128).
Regarding claim 26, Yang discloses a portion of a topmost surface of the nitride layer (155) is disposed above a bottom surface of the bottommost nanostructure (115).
Regarding claim 27, Frougier discloses a bottommost surface of the nitride layer (130/138) is disposed below a bottom surface of the bottommost nanostructure (116) (Figure 23). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Yang et al. in view of Frougier et al.
Regarding claim 28, Frougier discloses a portion of the topmost surface of the nitride layer (146) is disposed above a bottom surface of the bottommost nanostructure (lowest 114R) and a portion of a bottommost surface of the nitride layer (130/138) is disposed below a bottom surface of the bottommost nanostructure (114R) (Figure 21 left shows 146 above a top surface, and Figure 21 right shows 130 below a bottom surface). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Yang et al. in view of Frougier et al.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Publication No. 2021/0210349) in view of Frougier et al. (US Patent No. 9,947,804) and further in view of Kim et al. (US Publication No. 2021/0217848).
Regarding claim 7, Xie/Frougier discloses the limitations as discussed in the rejection of claim 1 above. Xie/Frougier silent regarding a source/drain contact extending into the second epitaxial structure. However, Kim discloses a source/drain contact (330) which extends into an epitaxial structure (230) of the source/drain region (Figure 31). It would have been obvious to one of ordinary skill in the art at a time before the effective filing date of the invention to have included the source/drain contact of Xie/Frougier to extend into the second epitaxial structure, as taught by Kim, since it can increase the surface area contacting the source/drain region, thereby improving electrical characteristics such as charge carrier flow (paragraph 137).
Regarding claim 8, Kim discloses a silicide layer (320) between the source/drain contact (330) and the epitaxial structure (230). As explained above, it would have been obvious to one of ordinary skill in the art at the time before the effective filing date of the invention to modify the semiconductor package of Xie et al. in view of Frougier et al, and further in view of Kim et al.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Jang et al. (US Publication No. 2020/0220018) discloses epitaxial layers (152A/152B) below a top surface of a bottommost nanostructure (Figure 11H).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/N.R.P/ 3/6/2026Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897