Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/02/2026 has been entered.
Election/Restrictions
Office action Dated 04/25/2025 made the restriction between inventions 1/2 claims 1-16 and invention 3 claims 17-20 Final. And as such claims Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim.
In applicants arguments/Remarks made in Amendment dated 07/25/2025 and applicants arguments/Remarks made in Amendment submitted with the RCE dated 03/02/2026 applicant still maintains that the restriction requirement is still improper and requests that Examiner still examine claims 17-20.
Applicants’ arguments that the restriction is improper because the restriction is hinged on the fact that instead of restricting invention I/II and Invention III as ABbr-Bsp it should instead be related as ABbr-CBsp where there are additional elements in in Invention III which introduce the “C”. Applicant states that because the MPEP doesn’t depict the specific criteria for relating ABbr-CBsp, that a restriction would not be proper. However, this is not true as the MPEP clearly further explains the rational for deciding the criteria for distinctiveness between Combination and subcombination in MPEP § 806.05(c). The two important criteria are that the combination as claimed
does not require the particulars of the subcombination as claimed for patentability (to show novelty and unobviousness)
The subcombination can be shown to have utility either by itself or in another materially different combination.
In Light of this, the “C” that applicant pointed out in the subcombination does not actually function to make the inventions non-distinct. The combination of ABbr still does not require the particulars of CBsp as pointed out in restriction requirement dated December 5 2025, with the “C” as pointed out by the applicant still not present in the combination of ABbr. This makes the inclusion of C, completely moot.
Because of this, Finality of the restriction requirement will remain and claims 17-20 will remain withdrawn from consideration pursuant to 37 CFR 1.142(b).
Response to Arguments and Amendment
Applicant's arguments with respect to the rejection of claim 10 filed 03/02/2026 on Page. 10 of “Applicant Arguments/Remarks Made in an Amendment” have been fully considered but they are not persuasive.
In response to applicant's argument that the planarization process in the reference is for a different purpose than the purpose of the planarization process in the instant application, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
The planarization process being done in both the instant application and the prior art still present a prima facie case of obviousness regardless of the intended purpose of the planarization. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant. See, e.g., In re Kahn, 441 F.3d 977, 987, 78 USPQ2d 1329, 1336 (Fed. Cir. 2006) (motivation question arises in the context of the general problem confronting the inventor rather than the specific problem solved by the invention); Cross Med. Prods., Inc. v. Medtronic Sofamor Danek, Inc., 424 F.3d 1293, 1323, 76 USPQ2d 1662, 1685 (Fed. Cir. 2005) (“One of ordinary skill in the art need not see the identical problem addressed in a prior art reference to be motivated to apply its teachings.”)
It is for these reasons above that the rejection of the Claim 10 will be maintained as Examiner is not convinced that the argument for differential purpose of the planarization makes the instant application novel from the cited art.
Applicant’s arguments, see Page. 10 of “Applicant Arguments/Remarks Made in an Amendment” filed 03/02/2026, with respect to Claim 1 have been fully considered and are persuasive. Examiner Agrees that at the very least the prior art only disclosed a change in atomic mass percentage of Nitrogen and not specifically removing Nitrogen during the Anneal process. Therefore, the 35 U.S.C. 102(a)(1) Rejection of Claim 1 by Wang been withdrawn. However, upon further search and consideration, A new 35 U.S.C. 103 obviousness-based rejection of Claim 1 by Wang in view of Choi has been made.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by United States Patent Application Publication by Wang et al. (US 20190067027 A1; Wang) in view of United States Patent Application Publication Choi et al. (US 20180151376 A1; Choi).
Regarding Claim 1, Wang discloses a method comprising:
etching a semiconductor substrate to form a semiconductor strip and a recess (Para. 23, “In some embodiments, the semiconductor fins 64 [e.g., 64A and 64B] are formed by etching trenches in the substrate 51.”), with a sidewall of the semiconductor strip being exposed to the recess (See Fig. 4, where the fins are exposed to the recess/trenches directly adjacent to the fins);
depositing a dielectric layer (83) into the recess (Fig. 5, where 83 is deposited in the recessed portion);
Examiner Note – Wang, describes 83 as a capping layer and 86 as a dielectric layer. The difference between the terminology in the art is nuanced and a “capping layer” is just a subset of dielectric layers, typically used for structure or sealing but not necessarily. Because the capping layer in the Wang reference comprises the same materials of the dielectric layer of the instant application, it would be reasonable for of ordinary skill in the art that anticipation between the two layers is warranted. The same is true for the capping layer of the instant application and the dielectric layer (86) of the Wang reference.
depositing a capping layer (86) over the dielectric layer, wherein the capping layer extends into the recess (Fig. 6, where 86 is deposited over 83 including in the recess), and the capping layer comprises silicon oxynitride;
filling remaining portions of the recess with dielectric materials (Para. 36, “Next, as illustrated in FIG. 7, an insulation material 62 is formed to fill the trenches 61”);
performing an anneal process (Para. 41, “A top layer 87 (e.g., exterior portion) of the dielectric layer 86 (e.g., silicon nitride) is oxidized after the anneal process 430 and is converted into an oxide (e.g., silicon oxynitride) of the dielectric layer 86”); wherein during the anneal process, atop surface of the semiconductor strip is exposed (Para. 39, where the anneal process 420 cures not only the top portion but also portions below the top. This means that not just the top is exposed to the annealing process when annealing) and
recessing the dielectric materials, the capping layer, and the dielectric layer, wherein remaining portions of the dielectric materials, the capping layer, and the dielectric layer form an isolation region, and wherein a portion of the semiconductor strip protrudes higher than a top surface of the isolation region to form a semiconductor fin (Figs 10-11. For Fig. 10 - the dielectric layer and capping layer is recessed through a dry etch [Para. 49], Fig. 11 – the dielectric materials are then recessed to form an isolation region between the semiconductor fins where the fins protrude higher than the surface of the isolation region).
However, while Wang does perform an anneal process, Wang fails to explicitly disclose that in the performance of the anneal process is done in order to remove nitrogen from the capping layer while the capping layer is exposed.
In a similar field of endeavor, Choi discloses a method of fabricating a semiconductor device (10), where the semiconductor device is semiconductor strip (Fig. 3) which the method of making includes an anneal (A1) of a capping layer (23) that is disposed over a dielectric layer (19a). Choi further discloses that the anneal step is used to remove nitrogen from the capping layer (Para. 20-21, “When the first annealing process A1 is carried out by supplying the first metal-containing layer 23 with hydrogen or nitrogen, it may be possible to remove nitrogen trapped at interfaces between the first metal-containing layer 23 and the gate dielectric layers 19a to 19d, thereby enhancing reliability of the gate dielectric layers 19a to 19d”).
In view of the disclosure of Choi, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Choi to Wang at the time the instant application was filed to incorporate the use of the anneal process in order to remove nitrogen from the capping layer. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand the advantages that removing nitrogen from the capping layer from an anneal process can enhance the reliability of the gate dielectric layers that the capping layer is directly on (Choi: Para 21).
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Wang in view of Choi and further in view of United States Patent Application Publication Kang et al. (US 20180323276 A1; Kang).
Regarding Claim 2, the combination of Wang and Choi discloses the method of claim 1, and further wherein the depositing the capping layer comprises an Atomic Layer Deposition (Wang: Para. 28, “Therefore, the capping layer 83 may also be referred to as a silicon liner. Any suitable deposition method, such as CVD, PVD, atomic layer deposition (ALD), the like, or combinations thereof, may be used to form the capping layer 83”), but Wang and Choi fail to disclose where the ALD cycles comprise pulsing Hexachlorodisilane (HCD) to the semiconductor substrate and purging; pulsing oxygen to the semiconductor substrate and purging; and pulsing ammonia to the semiconductor substrate and purging.
In a similar field of endeavor, the Kang reference discloses depositing a first dielectric (Kang: 108) layer through a plurality of Atomic Layer Deposition (ALD) cycles (Kang: Para. 31, Lines 1-4) wherein each of the ALD cycles comprises:
Pulsing Hexachlorodisilane (HCD) to the semiconductor strip and purging; pulsing oxygen to the semiconductor strip and purging; and pulsing ammonia to the semiconductor strip and purging (Kang: Para 31, Lines 4-9).
In view of the disclosure of Kang, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kang to the combination of Wang and Choi at the time the instant application was filed in order to preform specific steps in atomic layer deposition (ALD). Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand that the ALD process can use alternative gasses (Kang: Para. 31, 9-12).
Claims 3-7 are rejected under 35 U.S.C. 103 as being unpatentable as obvious Wang in view of Choi and further in view of Kao et al. (US 20200161123 A1; Kao)
Regarding Claim 3, the combination of Wang and Choi discloses the method of claim 1, and further comprising:
after the recess is filled with the dielectric materials, performing a planarization process on the dielectric materials, wherein the anneal process is performed through exposed top edges of the capping layer.
However, the Wang reference fails to disclose where the planarization is performed on the capping layer, and the dielectric layer.
In a similar field of endeavor, the Kao reference discloses a planarization process which captures planarizing the layers deposited over the fin (Kao: Figs. 6-7, where layer 34 is planarized).
In view of the disclosure of Kao, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kao to the combination of Wang and Choi at the time the instant application was filed in order to planarize the capping layer and dielectric layer. Accordingly, one would have been motivated to make the modification because of the advantages removing excess dielectric materials and having the vertical portions of the dielectric layer on opposite sides of the sidewalls revealed (Kao: Para. 50)
Regarding Claim 4, Wang, Choi, and Kao discloses the method of claim 3, and wherein the anneal process is performed before the recessing (Wang: anneal process step in Fig. 9, and afterward the recess process step is completed in Fig. 10).
Regarding Claim 5, the combination of Wang and Choi discloses the method of claim 1. The Wang reference also discloses wherein the anneal process includes 2 steps, where the first step is a high-temperature wet anneal process, and the second step of preforming a dry anneal process performed after the high-temperature wet anneal process. However, the wang reference fails to disclose where there is a low-temperature wet anneal process performed at a first temperature.
In a similar field of endeavor, the Kao reference discloses three parts anneal process with the same steps of low temperature wet anneal (Kao: 216), high temperature wet anneal (Kao: 218), and a dry anneal (Kao: 220). Where there is a low-temperature wet anneal process performed at a first temperature (Kao: Para. 38, lines 4-8).
In view of the disclosure of Kao, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kao to the combination of Wang and Choi at the time the instant application was filed in order to perform an additional step in the anneal process where there is a low-temperature wet anneal. Accordingly, one would have been motivated to make the modification because of the advantages of using the low temperature step to have the steam molecules penetrate the dielectric layer and start the partial conversion of the Si-N-C bonds (Kao: Para. 39, lines 10-18).
Regarding Claim 6, Wang, Choi, and Kao disclose the method of claim 5, and wherein the dry anneal process is performed at a third temperature higher than the first temperature and the second temperature. (In wang, the wet anneal process is performed at a range of 500°C to about 700°C and the dry anneal is performed at a range of 600°C to about 800°C. Para. 38).
Regarding Claim 7, Wang, Choi, and Kao disclose the method of claim 5, wherein the low-temperature wet anneal process is performed at the first temperature in a range between about 440°C and about 460°C (Kao: Para 39, Lines 4-7).
Claims 10-11, 14, 16, 22-23, and 27 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Wang in view of Kang.
Regarding Claim 10, Wang discloses a method comprising:
forming a semiconductor strip (Wang: Para. 23, “In some embodiments, the semiconductor fins 64 [e.g., 64A and 64B] are formed by etching trenches in the substrate 51.”);
depositing a first dielectric layer (86) through a plurality of Atomic Layer Deposition (ALD) cycles (Wang: Para. 34, “For example, the dielectric layer 86 may be a silicon nitride (e.g., SiN.sub.x), silicon oxynitride (e.g., SiON), or silicon oxide (e.g., SiO.sub.2) layer formed by CVD, PVD, ALD, the like, or combinations thereof”);
annealing (430) the first dielectric layer (Wang: Fig. 9);
recessing the first dielectric layer, wherein a remaining portion of the first dielectric layer forms a part of an isolation structure, and a portion of the semiconductor strip protrudes higher than a top surface of the isolation structure to form a semiconductor fin (Figs 10-11. For Fig. 10 - the dielectric layer is recessed through a dry etch [Para. 49], Fig. 11 – the dielectric materials are then recessed to form an isolation region between the semiconductor fins where the fins protrude higher than the surface of the isolation region); and
forming a gate stack (68) extending on a sidewall and a top surface of the semiconductor fin (Fig. 1, where the gate stack [68] is over the semiconductor fins underneath).
Wang fails to disclose wherein the deposition of the first dielectric layers are performed in cycles of pulsing Hexachlorodisilane and purging, oxygen and purging, and pulsing ammonia and purging and further fails to disclose where a second dielectric layer is deposited over the first. Furthermore, while Wang does disclose planarization processes to remove portions of the dielectric layers, because there is not a second dielectric layer over the first, there is no planarization on the second dielectric layer over the first.
In a similar field of endeavor, the Kang reference discloses depositing a first dielectric (Kang: 108) layer through a plurality of Atomic Layer Deposition (ALD) cycles (Kang: Para. 31, Lines 1-4) wherein each of the ALD cycles comprises:
pulsing Hexachlorodisilane (HCD) to the semiconductor strip and purging; pulsing oxygen to the semiconductor strip and purging; and pulsing ammonia to the semiconductor strip and purging (Kang: Para 31, Lines 4-9);
depositing a second dielectric (109) layer over the first dielectric layer through a conformal deposition process (Kang: Para. 35),
performing a planarization process to remove a top portion of the second dielectric layer, wherein the top portion of the second dielectric layer overlaps the semiconductor strip (Kang: Para. 49, Fig. 1K, where top portions of second dielectric layer 109 are removed and the top portion of second dielectric layer overlap with the fin);
In view of the disclosure of Kang, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kang to Wang at the time the instant application was filed in order to preform specific steps in atomic layer deposition (ALD), deposit a second dielectric layer over the first dielectric layer and planarize the second dielectric layer. Accordingly, one would have been motivated to make the modification because one of ordinary skill in the art would understand that the ALD process can use alternative gasses (Kang: Para. 31, 9-12), and extra dielectric layers can be used as spacers because of the intensity of that steps of cleaning and annealing can cause (Kang: para 34).
Regarding Claim 11, Wang and Kang discloses the method comprising the method of claim 10, and wherein in the each of the ALD cycles, the oxygen is pulsed after the HCD is pulsed, and the ammonia is pulsed after the oxygen is pulsed (Kang: Para. 32, lines 3-9).
Regarding Claim 14, Wang and Kang discloses the method of claim 10, and further comprising:
before the first dielectric layer (Wang: 86) is deposited, depositing a second dielectric layer (Wang: 83), wherein the second dielectric layer comprises silicon oxide and has a lower nitrogen atomic percentage than the first dielectric layer (Wang: Para. 28, Lines 5-12, When the layer is made of silicon oxide, it will have no nitrogen, giving it a lower nitrogen atomic percentage then the first dielectric layer which was made in part by pulsing ammonia via. ALD).
Regarding Claim 16, Wang and Kang discloses the method of claim 10, and wherein before the annealing, the first dielectric layer has a first nitrogen atomic percentage, and after the annealing, the first dielectric layer has a second nitrogen atomic percentage lower than the first nitrogen atomic percentage.
Because of the structure, different parts of the First dielectric layer will have different amounts of nitrogen removed from the dielectric layer. The closer to the upper surface of where the anneal is, the higher nitrogen concentration, and further away the less nitrogen concentration. Before the anneal process, the layer is uniform in its nitrogen atomic percentage. After the anneal process, layer 68 at the top of the fin has a Si:N:O ratio of 5:2.5:2.5, the center point of the fin has a Si:N:O ratio of 5:3:2.5, and the lower horizontal portion of layer 68 has a Si:N:O ratio of 5:4:2 (Wang: Para. 45). Because the anneal process step is removing nitrogen from the first dielectric layer, there will have a lower atomic nitrogen percentage after annealing.
Regarding Claim 22, Wang and Kang discloses the method of claim 10, and further comprising, before the planarization process, depositing a dielectric fin (Wang: 62; Kang: 307) layer over the second dielectric layer (Both Wang and Kang, deposit a dielectric fin layer. For Wang, it is deposited over the plurality of dielectric layers before the planarization process, however, wang doesn’t anticipate the second dielectric layer and only has it as an obvious combination with Kang).
Regarding Claim 23, Wang and Kang discloses the method of claim 10, wherein the second dielectric layer comprises silicon oxide and has a lower nitrogen atomic percentage than the first dielectric layer (Wang: Para. 42, “the second spacer 109 includes a composition of Si, O, and C”. When the layer is made of silicon oxide, it will have no nitrogen, giving it a lower nitrogen atomic percentage then the first dielectric layer which was made in part by pulsing ammonia via. ALD).
Regarding Claim 27, Wang and Kang disclose the method of claim 10, and further wherein the planarization process is performed through a chemical mechanical polish process. (Kang: Para. 49, “In some embodiments, the series of process steps include film deposition steps, chemical mechanical planarization (CMP) steps…”. Further Wang also discloses that planarization can be a CMP process; Wang: Para. 16, “A planarization process, such as chemical mechanical polish (CMP), may then be performed to level the top surface of the semiconductor material 50A with the top surface of the substrate 50”).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable as obvious by Wang and kang and further in view of Kao.
Regarding Claim 15, Wang and Kang discloses the method of claim 10.
The Wang reference also discloses wherein the anneal process includes 2 steps, where the first step is a high-temperature wet anneal process, and the second step of preforming a dry anneal process performed after the high-temperature wet anneal process but fails to disclose where there is a low-temperature wet anneal process step.
In a similar field of endeavor, the Kao reference discloses a three part anneal process with the steps of low temperature wet anneal (Kao: 216), high temperature wet anneal (Kao: 218), and a dry anneal (Kao: 220). Where there is a low-temperature wet anneal process step (Kao: Para. 38, lines 4-8).
In view of the disclosure of Kao, it would have been obvious for a person of ordinary skill in the art to apply the disclosure of Kao to the combination of Wang and Kang at the time the instant application was filed in order to perform an additional step in the anneal process where there is a low-temperature wet anneal. Accordingly, one would have been motivated to make the modification because of the advantages of using the low temperature step to have the steam molecules penetrate the dielectric layer and start the partial conversion of the Si-N-C bonds (Kao: Para. 39, lines 10-18).
Claims 21 and 24 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Wang in view of Kang, with evidence by NPL publication by Kim et al. (Effect of Gas Annealing on the Electrical Properties of Ni/AlN/SiC. Micromachines (Basel). 2021 Mar 8;12(3):283. doi: 10.3390/mi12030283.; Kim)
Regarding Claim 21, Wang and Kang discloses the method of claim 10, and further wherein the planarization process results in a top surface of the semiconductor strip to be exposed (Kang: Fig. 1K, after the planarization process, the top surface of the semiconductor strip is exposed), and during the annealing the first dielectric layer, the top surface of the semiconductor strip is exposed to a process gas used for the annealing (Regardless of if the annealing process takes before or after the planarization process, process gasses can penetrate the dielectric layer/s which means that the semiconductor strip would be exposed to the process gasses used for annealing, as evidenced by scientific publication by Kim et al, and can be found in the conclusion section).
Regarding Claim 24, Wang and Kang discloses the method of claim 10, and further wherein when the first dielectric layer is annealed, a top surface of the semiconductor strip is exposed to a process gas used for the annealing (Regardless of if the annealing process takes before or after the planarization process, process gasses can penetrate the dielectric layer/s which means that the semiconductor strip would be exposed to the process gasses used for annealing, as evidenced by scientific publication by Kim et al, and can be found in the conclusion section).
Allowable Subject Matter
Claim 25 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 25, the method that the instant application discloses in regard to the deposition of etching a semiconductor substrate, depositing dielectric layers into the recess and depositing the capping layer over the dielectric layer and into the recess and further planarizing these doesn’t appear to be novel in its own right. However, what is novel is where the planarization leads to the semiconductor strip being exposed and while still exposed the anneal process is used onto the exposed semiconductor strip. This is of course only true in the light of the rest of the limitations of claim 1.
For many of the same reasons, claim 26 is also found to contain allowable subject matter.
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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