DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 1/22/26. Currently, claims 1, 3-5, 8-12, 15, 23, and 29-42 are pending. Claims 33-42 are newly added.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 9, 12, 15, 32-37 and 40-42 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US PGPub 2017/0011936, hereinafter referred to as “Lin”).
Lin discloses the semiconductor method as claimed. See figures 1-12 and corresponding text, where Lin teaches, in claim 1, a method for forming a semiconductor device, comprising:
forming a metallization layer (226, 228) on an exterior surface of a wafer (170); (figure 6a; [0055-0058])
singulating the wafer (170) into a plurality of singulated die (220); (figure 9d; [0076]) and
attaching a first of the singulated the die (220) to a chip carrier (242) using the metallization layer (figure 9e; [0077-0079]).
Lin teaches, in claim 4, further comprising forming a diffusion barrier (228) on the exterior surface of the die (figure 9a; [0071-0072]).
Lin teaches, in claim 5, wherein forming the metallization layer comprises forming a metallization layer from one of gold (Au), silver (Ag), copper (Cu), indium (In), bismuth (Bi), tin (Sn), lead tin (PbSn), or tin silver (SnAg) (figure 9a; [0071-0072]).
Lin teaches, in claim 9, wherein attaching the first of the singulated die comprises thermocompression bonding the first of the singulated die to the chip carrier ([0081])
Lin teaches, in claim 12, wherein attaching the first of the singulated die comprises transient liquid phase bonding the first of the singulated die to the chip carrier ([0081], heating above melting point to reflow to form balls).
Lin teaches, in claim 15, a method for forming a semiconductor device, comprising:
forming a metallization layer (226, 228) on an exterior surface of a wafer via chemical vapor deposition (CVD) ([0071]);
singulating the wafer (170) into a plurality of singulated die (220): (figures 6b, 6c and 9d; [0059-0063], [0076]) and
attaching a first of the singulated the die (220) to a chip carrier (242) using the metallization layer (226, 228), wherein the chip carrier (242) is a lead frame or a direct bonded copper substrate (figure 9e; [0077-0081]).
Lin teaches, in claim 32, wherein attaching the first of the singulated die comprises transient liquid phase bonding the first of the singulated die to the chip carrier ([0081], heating above melting point to reflow to form balls).
Lin teaches, in claim 33, wherein the chip carrier is a leadframe or a direct bonded copper substrate and the singulated first of the singulated die is a singulated silicon carbide die ([0055], [0074]).
Lin teaches, in claim 34, wherein the first of the singulated die includes an active layer, and the exterior surface of the wafer is opposite the active layer (figure 9a; [0070-0074]).
Lin teaches, in claim 35, wherein the metallization layer is formed on the exterior surface of the wafer via electroplating ([0073]).
Lin teaches, in claim 36, wherein the metallization layer is formed on the exterior surface of the wafer via electroless plating ([0073]).
Lin teaches, in claim 37, wherein the first of the singulated die includes an active layer, and the exterior surface of the wafer is opposite the active layer (figure 9a; [0070-0074]).
Lin teaches, in claim 40, a method for forming a semiconductor device, comprising:
forming a diffusion barrier (228) on an exterior surface of a singulated semiconductor die (220); (figure 9a; [0070-0074])
forming a metallization layer (226, 228) on the diffusion barrier opposite the exterior surface of the singulated semiconductor die (220); (figure 9d; [0076]) and
attaching the singulated die (220) to a chip carrier (242) using transient liquid phase bonding process, where the transient liquid phase bonding process converts the metallization layer into an intermetallic compound layer (figure 9e; [0077-0081], heating above melting point to reflow to form balls).
Lin teaches, in claim 41, wherein the intermetallic compound layer comprises metal from the metallization layer and material from the diffusion barrier ([0074],[0081]).
Lin teaches, in claim 42, wherein the intermetallic compound layer comprises metal from the metallization layer and material from the chip carrier ([0074], [0081]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 23, 38 and 39 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US PGPub 2017/0011936, hereinafter referred to as “Lin”) in view of Chuang et al. (US PGPub 2022/0336407, hereinafter referred to as “Chuang”).
Lin discloses the semiconductor method substantially as claimed. See figures 1-12 and corresponding text, where Lin teaches, in claim 23, a method for forming a semiconductor device, comprising:
forming a diffusion barrier (228) on an exterior surface of a wafer (170), where the wafer includes a plurality of die (220), a first of the die includes an active layer, and the exterior surface of the wafer is opposite the active layer; (figure 6a; [0055-0058])
forming a metallization layer (226, 228) on the diffusion barrier opposite the exterior surface of the wafer via electroplating or electroless plating (figure 9a; [0070-0074]);
singulating the wafer into a plurality of die (220); (figure 9d; [0076]) and
then attaching a first of the singulated die (220) to a chip carrier (242) using the metallization layer (226, 228), wherein attaching the die comprises diffusion bonding the die to the chip carrier or thermocompression bonding the die to the chip carrier (([0055], [0074], [0081]).
However, Lin fails to teach, in claim 23, the metallization layer comprising a gold-free bond layer having a thickness less than approximately 5 microns (µm), but more than 0.01 µm.
Chuang teaches, in claim 23, wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm ([0033]). In addition, Chuang provides the advantages of providing and adhesive layer (implied metallization) between the chip and the bonding layer prevents peeling this results in better bonding ([0067]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm, in the method of Lin, according to the teachings of Chuang, with the motivation of preventing peeling between the bonding layer and the chip.
Lin teaches, in claim 38, wherein the chip carrier is a leadframe or a direct bonded copper substrate and the first of the singulated die is a silicon carbide die ([0055], [0081]).
Lin teaches, in claim 39, wherein the first of the singulated die includes an active layer, and the exterior surface of the wafer is opposite the active layer (figure 9a; [0070-0074]).
Claim(s) 3, 8, 10, and 29-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US PGPub 2017/0011936, hereinafter referred to as “Lin”) as applied to claims 1 and 15 above, and further in view of Chuang et al. (US PGPub 2022/0336407, hereinafter referred to as “Chuang”).
Lin discloses the semiconductor method substantially as claimed. See the rejection above.
Lin fails to explicitly teach, in claim 3, wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm.
Chuang teaches, in claim 3, wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm ([0033]). In addition, Chuang provides the advantages of providing and adhesive layer (implied metallization) between the chip and the bonding layer prevents peeling this results in better bonding ([0067]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm, in the method of Lin, according to the teachings of Chuang, with the motivation of preventing peeling between the bonding layer and the chip.
Lin fails to teach, in claim 8, wherein attaching the first of the singulated die comprises diffusion bonding the first of the singulated die to the chip carrier.
Chuang teaches, in claim 8, wherein attaching the die comprises diffusion bonding the die to the chip carrier (figure 2; [0042-0044]). In addition, Chuang provides the advantages of providing and adhesive layer (implied metallization) between the chip and the bonding layer prevents peeling this results in better bonding ([0067]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein attaching the die comprises diffusion bonding the die to the chip carrier, in the method of Lin, according to the teachings of Chuang, with the motivation of preventing peeling between the bonding layer and the chip.
Lin fails to teach, in claim 10, wherein attaching the first of the singulated die comprises reducing atmospheric pressure during attaching.
Chuang teaches, in claim 10, wherein attaching the die comprises reducing atmospheric pressure during attaching ([0047]). In addition, Chuang provides the advantages of providing and adhesive layer (implied metallization) between the chip and the bonding layer prevents peeling this results in better bonding ([0067]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein attaching the die comprises reducing atmospheric pressure during attaching, in the method of Lin, according to the teachings of Chuang, with the motivation of preventing peeling between the bonding layer and the chip.
Lin fails to explicitly teach, in claim 29, wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (pm) but more than 0.01 pm.
Chuang teaches, in claim 29, wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm ([0033]). In addition, Chuang provides the advantages of providing and adhesive layer (implied metallization) between the chip and the bonding layer prevents peeling this results in better bonding ([0067]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate wherein forming the metallization layer comprises forming a metallization layer having a thickness less than approximately 5 microns (µm) but more than 0.01 µm, in the method of Lin, according to the teachings of Chuang, with the motivation of preventing peeling between the bonding layer and the chip.
Lin in view of Chuang teaches, in claim 30, further comprising forming a diffusion barrier on the exterior surface of the die (figure 9a; [0070-0074], Lin).
Lin in view of Chuang teaches, in claim 31, wherein attaching the first of the singulated die comprises thermocompression bonding the first of the singulated die to the chip carrier ([0081], Lin).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US PGPub 2017/0011936, hereinafter referred to as “Lin”) as applied to claim 1 above, and further in view of Yu et al. (US PGPub 2009/0224371, hereinafter referred to as “Yu”).
Lin discloses the semiconductor method substantially as claimed. See the rejection above.
However,Lin fails to show, in claim 11, wherein the diffusion bonding comprises diffusion bonding at less than approximately 250 oC.
Yu teaches, in claim 11, uses a similar method that includes a diffusion bonding step starting at 250 degrees ([0045]). In addition, Yu provides the advantages of creating and oxidation/corrosion protective layer, thus improving reliability of the bonding process.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to incorporate wherein the diffusion bonding comprises diffusion bonding at less than approximately 250 oC, in the method of Lin, according to the teachings of Yu, with the motivation of improving reliability of the bonding process.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-5, 8-12, 15, 23, and 29-42 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant’s amendment has necessitated new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 May 14, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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