Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claims 1-2, 5-6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (PGPub No. 20060133009) in further view of Cheng (PGPub No. 20100044833) and Chen (US Patent No. 10998397).
Regarding claim 1, Choi teaches a semiconductor device comprising: a wafer (Fig. 7 points to a ceramic substrate (wafer) including the ceramic portion 101.); a plurality of powering redistribution layers disposed on the wafer; and a plurality of grounding redistribution layers disposed on the wafer (Id. points to a plurality of first electrode branches 201 (powering redistribution layers) and a plurality of second electrode branches 203 (grounding redistribution layers).).
Choi fails to teach wherein at least one of: the powering redistribution layers comprising a first powering redistribution layer, a second powering redistribution layer, and a third powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer and a second grounding redistribution layer, the first powering redistribution layer, the first grounding redistribution layer, the second powering redistribution layer, the second grounding redistribution layer, and the third powering redistribution layer are elongated in a first direction and are sequentially arranged in parallel in a second direction perpendicular to the first direction, the semiconductor device further comprising a first powering bridge connecting a first end of the first powering redistribution layer and a first end of the second powering redistribution layer and a second powering bridge connecting a second end of the second powering redistribution layer and a second end of the third powering redistribution layer , the first grounding redistribution layer separated from and surrounded by the first powering redistribution layers, the first powering bridge, and the second powering redistribution layer on three sides to form a first capacitor, the second grounding redistribution layer separated from and surrounded by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer on three sides to form a second capacitor; and the powering redistribution layers comprising a first powering redistribution layer and a second powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer, a second grounding redistribution layer, and a third grounding redistribution layer, the first grounding redistribution layer, the first powering redistribution layer, the second grounding redistribution layer, the second powering redistribution layer, and the third grounding redistribution layer are elongated in the first direction and are sequentially arranged in parallel in the second direction, the semiconductor device further comprising a first grounding bridge connecting a first end of the first grounding redistribution layer and a first end of the second grounding redistribution layer and a second grounding bridge connecting a second end of the second grounding redistribution layer and a second end of the third grounding redistribution layer, the first powering redistribution layer separated from and surrounded by the first grounding redistribution layers and one of, the second grounding bridge, and the second grounding redistribution layer on three sides to form the first capacitor, and the second powering redistribution layer separated from and surrounded by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer on three sides to form the second capacitor.
Cheng teaches wherein at least one of: the powering redistribution layers comprising a first powering redistribution layer, a second powering redistribution layer, and a third powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer and a second grounding redistribution layer (Fig. 1 points to an integrated capacitor comprising a comb-shaped metal patterns 10/12 (the grounding redistribution layers) and a meandering metal pattern 14 (the powering redistribution layers).), the first powering redistribution layer, the first grounding redistribution layer, the second powering redistribution layer, the second grounding redistribution layer, and the third powering redistribution layer are elongated in a first direction and are sequentially arranged in parallel in a second direction perpendicular to the first direction (Id. points to finger electrodes 104 (first grounding redistribution layer) and 114 (second grounding redistribution layer), which are parallel to the vertical portions of the metal pattern 14 (first powering redistribution layer; second powering redistribution layer; third powering redistribution layer).), the semiconductor device further comprising a first powering bridge connecting a first end of the first powering redistribution layer and a first end of the second powering redistribution layer and a second powering bridge connecting a second end of the second powering redistribution layer and a second end of the third powering redistribution layer (Id. points to the horizontal portions of the metal pattern 14 (first powering bridge; second powering bridge).), the first grounding redistribution layer separated from and surrounded by the first powering redistribution layers, the first powering bridge, and the second powering redistribution layer on three sides to form a first capacitor (Id. points to an area (first capacitor) comprising the finger electrode 104 (first grounding redistribution layer) surrounded by the metal pattern 14 (first powering redistribution layer; first powering bridge; second powering redistribution layer).), the second grounding redistribution layer separated from and surrounded by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer on three sides to form a second capacitor (Id. points to an area (second capacitor) comprising the finger electrode 114 (second grounding redistribution layer) surrounded by the metal pattern 14 (second powering redistribution layer; second powering bridge; third powering redistribution layer).); and the powering redistribution layers comprising a first powering redistribution layer and a second powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer, a second grounding redistribution layer, and a third grounding redistribution layer ([0020] points to the metal pattern 14 having a polarity that is opposite to that of the two comb-shaped metal patterns 10 and 12. Thus, it is considered obvious that Fig. 1 further points to an alternative integrated capacitor comprising a comb-shaped metal patterns 10/12 (the powering redistribution layers) and a meandering metal pattern 14 (the grounding redistribution layers).), the first grounding redistribution layer, the first powering redistribution layer, the second grounding redistribution layer, the second powering redistribution layer, and the third grounding redistribution layer are elongated in the first direction and are sequentially arranged in parallel in the second direction (Fig. 1 points to finger electrodes 104 (first powering redistribution layer) and 114 (second powering redistribution layer), which are parallel to the vertical portions of the metal pattern 14 (first grounding redistribution layer; second grounding redistribution layer; third grounding redistribution layer).), the semiconductor device further comprising a first grounding bridge connecting a first end of the first grounding redistribution layer and a first end of the second grounding redistribution layer and a second grounding bridge connecting a second end of the second grounding redistribution layer and a second end of the third grounding redistribution layer (Id. points to the horizontal portions of the metal pattern 14 (first grounding bridge; second grounding bridge).), the first powering redistribution layer separated from and surrounded by the first grounding redistribution layers and one of, the second grounding bridge, and the second grounding redistribution layer on three sides to form the first capacitor (Id. points to an area (first capacitor) comprising the finger electrode 104 (first powering redistribution layer) surrounded by the metal pattern 14 (first grounding redistribution layer; first grounding bridge; second grounding redistribution layer).), and the second powering redistribution layer separated from and surrounded by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer on three sides to form the second capacitor (Id. points to an area (second capacitor) comprising the finger electrode 114 (second powering redistribution layer) surrounded by the metal pattern 14 (second grounding redistribution layer; second grounding bridge; third grounding redistribution layer).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Choi and Cheng, such that the powering and grounding redistribution layers are arranged in interdigitated/comb-meander patterns in order to create capacitors that maintain their level of capacitance while taking up a smaller floor area.
Choi et al. still fails to teach wherein the first grounding redistribution layer does not extend beyond a first region enclosed at least by the first powering redistribution layer, the first powering bridge, and the second powering redistribution layer, and wherein the second grounding redistribution layer does not extend beyond a second region enclosed at least by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer, and wherein the first powering redistribution layer does not extend beyond a first region enclosed at least by the first grounding redistribution layer, the first grounding bridge, and the second grounding redistribution layer, and wherein the second powering redistribution layer does not extend beyond a second region enclosed at least by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer.
Chen teaches wherein the first grounding redistribution layer does not extend beyond a first region enclosed at least by the first powering redistribution layer, the first powering bridge, and the second powering redistribution layer (Fig. 4 points to a capacitor structure 400 comprising a metal finger 401 (first grounding redistribution layer), a first side metal finger 408 (first powering redistribution layer), and a second side metal finger 409 (second powering redistribution layer), with said side metal fingers being connected by a horizontal portion (first powering bridge). Col. 5, lines 32-36 further points to an alternative capacitor structure 100 where the length of each metal finger may be decreased or minimized to further reduce the capacitance.), and wherein the second grounding redistribution layer does not extend beyond a second region enclosed at least by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer (Id. It is considered obvious that the structure previously discussed could be duplicated in order to form additional capacitor structures.), and wherein the first powering redistribution layer does not extend beyond a first region enclosed at least by the first grounding redistribution layer, the first grounding bridge, and the second grounding redistribution layer (Fig. 4 points to a capacitor structure 400 comprising a metal finger 401 (first powering redistribution layer), a first side metal finger 408 (first grounding redistribution layer), and a second side metal finger 409 (second grounding redistribution layer), with said side metal fingers being connected by a horizontal portion (first grounding bridge). Col. 5, lines 32-36 further points to an alternative capacitor structure 100 where the length of each metal finger may be decreased or minimized to further reduce the capacitance.), and wherein the second powering redistribution layer does not extend beyond a second region enclosed at least by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer (Id. It is considered obvious that the structure previously discussed could be duplicated in order to form additional capacitor structures.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Choi et al. and Chen, such that the lengths the inner grounding/powering redistribution layers are decreased so as not to extend beyond the surrounding powering/grounding redistribution layers, respectively, in order to further reduce the capacitance of the overall structure.
Regarding claim 2, Choi teaches wherein the powering redistribution layers and the grounding redistribution layers are alternatively arranged (Fig. 7 and [0033] point to a structure in which the first electrode branches 201 (the powering redistribution layers) and the second electrode branches 203 (the grounding redistribution layers) are patterned in an alternating sequence.).
Regarding claim 5, Choi teaches wherein a material of the powering redistribution layers is identical to a material of the grounding redistribution layers ([0026 points to each of the first and second electrode layers 201 (the powering redistribution layers) and 203 (the grounding redistribution layers) comprising a conductive metal such as copper).
Regarding claim 6, Choi teaches wherein a material of the powering redistribution layers and a material of the grounding redistribution layers comprise aluminum or copper ([0026 points to Each of the first and second electrode layers 201 (the powering redistribution layers) and 203 (the grounding redistribution layers) comprising a conductive metal such as copper).
Regarding claim 10, Choi teaches a semiconductor device comprising: a wafer (Fig. 7 points to a ceramic substrate (wafer) including the ceramic portion 101.); a plurality of powering redistribution layers disposed on the wafer; a plurality of grounding redistribution layers disposed on the wafer; and wherein the powering redistribution layers and the grounding redistribution layers are bar-shaped (Id. points to a plurality of first electrode branches 201 (powering redistribution layers) and a plurality of second electrode branches 203 (grounding redistribution layers).).
Choi fails to teach wherein at least one of: the powering redistribution layers comprising a first powering redistribution layer, a second powering redistribution layer, and a third powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer and a second grounding redistribution layer, the first powering redistribution layer, the first grounding redistribution layer, the second powering redistribution layer, the second grounding redistribution layer, and the third powering redistribution layer are elongated in a first direction and are sequentially arranged in parallel in a second direction perpendicular to the first direction, the semiconductor device further comprising a first powering bridge connecting a first end of the first powering redistribution layer and a first end of the second powering redistribution layer and a second powering bridge connecting a second end of the second powering redistribution layer and a second end of the third powering redistribution layer , the first grounding redistribution layer separated from and surrounded by the first powering redistribution layers, the first powering bridge, and the second powering redistribution layer on three sides to form a first capacitor, the second grounding redistribution layer separated from and surrounded by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer on three sides to form a second capacitor; and the powering redistribution layers comprising a first powering redistribution layer and a second powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer, a second grounding redistribution layer, and a third grounding redistribution layer, the first grounding redistribution layer, the first powering redistribution layer, the second grounding redistribution layer, the second powering redistribution layer, and the third grounding redistribution layer are elongated in the first direction and are sequentially arranged in parallel in the second direction, the semiconductor device further comprising a first grounding bridge connecting a first end of the first grounding redistribution layer and a first end of the second grounding redistribution layer and a second grounding bridge connecting a second end of the second grounding redistribution layer and a second end of the third grounding redistribution layer, the first powering redistribution layer separated from and surrounded by the first grounding redistribution layers and one of, the second grounding bridge, and the second grounding redistribution layer on three sides to form the first capacitor, and the second powering redistribution layer separated from and surrounded by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer on three sides to form the second capacitor.
Cheng teaches wherein at least one of: the powering redistribution layers comprising a first powering redistribution layer, a second powering redistribution layer, and a third powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer and a second grounding redistribution layer (Fig. 1 points to an integrated capacitor comprising a comb-shaped metal patterns 10/12 (the grounding redistribution layers) and a meandering metal pattern 14 (the powering redistribution layers).), the first powering redistribution layer, the first grounding redistribution layer, the second powering redistribution layer, the second grounding redistribution layer, and the third powering redistribution layer are elongated in a first direction and are sequentially arranged in parallel in a second direction perpendicular to the first direction (Id. points to finger electrodes 104 (first grounding redistribution layer) and 114 (second grounding redistribution layer), which are parallel to the vertical portions of the metal pattern 14 (first powering redistribution layer; second powering redistribution layer; third powering redistribution layer).), the semiconductor device further comprising a first powering bridge connecting a first end of the first powering redistribution layer and a first end of the second powering redistribution layer and a second powering bridge connecting a second end of the second powering redistribution layer and a second end of the third powering redistribution layer (Id. points to the horizontal portions of the metal pattern 14 (first powering bridge; second powering bridge).), the first grounding redistribution layer separated from and surrounded by the first powering redistribution layers, the first powering bridge, and the second powering redistribution layer on three sides to form a first capacitor (Id. points to an area (first capacitor) comprising the finger electrode 104 (first grounding redistribution layer) surrounded by the metal pattern 14 (first powering redistribution layer; first powering bridge; second powering redistribution layer).), the second grounding redistribution layer separated from and surrounded by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer on three sides to form a second capacitor (Id. points to an area (second capacitor) comprising the finger electrode 114 (second grounding redistribution layer) surrounded by the metal pattern 14 (second powering redistribution layer; second powering bridge; third powering redistribution layer).); and the powering redistribution layers comprising a first powering redistribution layer and a second powering redistribution layer, the grounding redistribution layers comprising a first grounding redistribution layer, a second grounding redistribution layer, and a third grounding redistribution layer ([0020] points to the metal pattern 14 having a polarity that is opposite to that of the two comb-shaped metal patterns 10 and 12. Thus, Fig. 1 further points to a reconfigured integrated capacitor comprising a comb-shaped metal patterns 10/12 (the powering redistribution layers) and a meandering metal pattern 14 (the grounding redistribution layers).), the first grounding redistribution layer, the first powering redistribution layer, the second grounding redistribution layer, the second powering redistribution layer, and the third grounding redistribution layer are elongated in the first direction and are sequentially arranged in parallel in the second direction (Fig. 1 points to finger electrodes 104 (first powering redistribution layer) and 114 (second powering redistribution layer), which are parallel to the vertical portions of the metal pattern 14 (first grounding redistribution layer; second grounding redistribution layer; third grounding redistribution layer).), the semiconductor device further comprising a first grounding bridge connecting a first end of the first grounding redistribution layer and a first end of the second grounding redistribution layer and a second grounding bridge connecting a second end of the second grounding redistribution layer and a second end of the third grounding redistribution layer (Id. points to the horizontal portions of the metal pattern 14 (first grounding bridge; second grounding bridge).), the first powering redistribution layer separated from and surrounded by the first grounding redistribution layers and one of, the second grounding bridge, and the second grounding redistribution layer on three sides to form the first capacitor (Id. points to an area (first capacitor) comprising the finger electrode 104 (first powering redistribution layer) surrounded by the metal pattern 14 (first grounding redistribution layer; first grounding bridge; second grounding redistribution layer).), and the second powering redistribution layer separated from and surrounded by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer on three sides to form the second capacitor (Id. points to an area (second capacitor) comprising the finger electrode 114 (second powering redistribution layer) surrounded by the metal pattern 14 (second grounding redistribution layer; second grounding bridge; third grounding redistribution layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Choi and Cheng, such that the powering and grounding redistribution layers are arranged in interdigitated/comb-meander patterns in order to create capacitors that maintain their level of capacitance while taking up a smaller floor area.
Choi et al. still fails to teach wherein the first grounding redistribution layer does not extend beyond a first region enclosed at least by the first powering redistribution layer, the first powering bridge, and the second powering redistribution layer, and wherein the second grounding redistribution layer does not extend beyond a second region enclosed at least by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer, and wherein the first powering redistribution layer does not extend beyond a first region enclosed at least by the first grounding redistribution layer, the first grounding bridge, and the second grounding redistribution layer, and wherein the second powering redistribution layer does not extend beyond a second region enclosed at least by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer.
Chen teaches wherein the first grounding redistribution layer does not extend beyond a first region enclosed at least by the first powering redistribution layer, the first powering bridge, and the second powering redistribution layer (Fig. 4 points to a capacitor structure 400 comprising a metal finger 401 (first grounding redistribution layer), a first side metal finger 408 (first powering redistribution layer), and a second side metal finger 409 (second powering redistribution layer), with said side metal fingers being connected by a horizontal portion (first powering bridge). Col. 5, lines 32-36 further points to an alternative capacitor structure 100 where the length of each metal finger may be decreased or minimized to further reduce the capacitance.), and wherein the second grounding redistribution layer does not extend beyond a second region enclosed at least by the second powering redistribution layer, the second powering bridge, and the third powering redistribution layer (Id. It is considered obvious that the structure previously discussed could be duplicated in order to form additional capacitor structures.), and wherein the first powering redistribution layer does not extend beyond a first region enclosed at least by the first grounding redistribution layer, the first grounding bridge, and the second grounding redistribution layer (Fig. 4 points to a capacitor structure 400 comprising a metal finger 401 (first powering redistribution layer), a first side metal finger 408 (first grounding redistribution layer), and a second side metal finger 409 (second grounding redistribution layer), with said side metal fingers being connected by a horizontal portion (first grounding bridge). Col. 5, lines 32-36 further points to an alternative capacitor structure 100 where the length of each metal finger may be decreased or minimized to further reduce the capacitance.), and wherein the second powering redistribution layer does not extend beyond a second region enclosed at least by the second grounding redistribution layer, the second grounding bridge, and the third grounding redistribution layer (Id. It is considered obvious that the structure previously discussed could be duplicated in order to form additional capacitor structures.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Choi et al. and Chen, such that the lengths the inner grounding/powering redistribution layers are decreased so as not to extend beyond the surrounding powering/grounding redistribution layers, respectively, in order to further reduce the capacitance of the overall structure.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. in further view of Hummler (PGPub No. 20070042591).
Regarding claim 3, Hummler teaches the semiconductor device of claim 1, further comprising a plurality of central pads respectively disposed in centers of the powering redistribution layers and the grounding redistribution layers (Fig. 1 points to a semiconductor device 10 comprising redistribution layer 11 including center pads 12 (central pads).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Choi et al. with those of Hummler, such that a plurality of central pads is formed in order to allow the redistribution layers to receive signals from certain locations on the device.
Regarding claim 4, Hummler teaches the semiconductor device of claim 1, further comprising a plurality of redistribution pads respectively disposed on opposite ends of the powering redistribution layers and on opposite ends of the grounding redistribution layers (Fig. 1 points to edge pads 14 (plurality of redistribution pads).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Choi et al. with those of Hummler, such that a plurality of redistribution pads is formed in order to allow the redistribution layers to redistribute signals from certain locations on the device to alternative locations.
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/04/2026, with respect to the objections of newly amended claims 1 and 10 have been fully considered and are persuasive. The objections of said claims have been withdrawn.
Applicant’s arguments, see Remarks, filed 01/04/2026, with respect to the rejection(s) of newly amended claim(s) 1 and 10 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Choi et al. in further view of Chen (US Patent No. 10998397).
Applicant's arguments filed 01/04/2026 with regards to the use of reference Chen (which was discussed in advance during the interview conducted on 12/16/2025) have been fully considered but they are not persuasive. Specifically, Applicant argues that Chen would be an improper reference to use for newly amended claims 1 and 10 due to 1) Chen failing to disclose “how to decrease the length of the metal finger” and 2) a lack of motivation to combine Chen with Choi and Cheng.
Regarding the first argument, Examiner argues that Applicant has applied an interpretation of Chen that is narrower than what it actually supported by the reference. As discussed above, Col. 5, lines 32-36 of Chen points to each metal finger (grounding redistribution layer; powering redistribution layer) having a length which may be decreased in order to reduce capacitance. While Chen does not specifically disclose a numerical range which a metal finger may be decreased by, it does show in multiple figures, such as Figs. 3-4, a region (first region; second region) defined by two side metal fingers (powering redistribution layer; grounding redistribution layer), and dummy metal fingers with a length that does not extend beyond said region. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the rejections of amended claims 1 and 10.
Regarding the second argument, Examiner argues that the lack of motivation to combine Chen with Choi and Cheng presented by Applicant is incorrectly supported by an intended use argument. In response to applicant's argument that Chen fails to solve the technical problem of “how to increase decoupling capacitance” as mentioned in the present application’s Remarks and paragraphs [0002] and [0037] of the specification, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. Additionally, all three references discuss capacitor structures and/or the methods of manufacturing the same, which is considered enough motivation for one of ordinary skill in the art to combine said references. Thus, Applicant’s argument is considered unpersuasive and fails to overcome the rejections of amended claims 1 and 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899