DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on October 24, 2025. Claims 15 and 21 have been amended. No new claims have been added. Claims 1-7 have been canceled. Currently, claims 8-27 are pending.
Applicant’s amendment to claim 21 successfully overcomes the 112(a) rejection of claim 21 and dependent claims set forth in the previous Office Action.
Applicant’s amendment to claim 21 successfully overcomes the 112(b) rejection of claims 21, 25 and dependent claims set forth in the previous Office Action.
Response to Arguments
Applicant has presented no arguments regarding the rejection of claim 27 under U.S.C. 112B and has neither submitted any amendments to the claim. Accordingly, the 112b rejection is maintained.
Applicant’s arguments with respect to claims 15 and 21 have been considered but are moot because the new ground of rejection as applied to the newly added claim limitations does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 27 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 27, the limitation, “wherein a negative charge of the passivation layer..” is indefinite because the mechanism by which the passivation layer acquires a “negative charge” is not clear. The independent claim only mentions an “amorphous boron material or a boron material” which does not inherently have a negative charge as a bulk material in the way as implied by the dependent claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 15-17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2009/0315137 A1; hereafter Kwon) in view of Cheng et al. (US 20150115397 A1; hereafter Cheng), Muramatsu al. (US 2018/0286899 A1; hereafter Muramatsu) and Hong et al. (US 2020/0111821 A1; hereafter Hong).
Regarding claim 15, Kwon teaches a method (see Figures 2 and 3A-3F), comprising:
forming, in a substrate, a photodiode for a pixel sensor of a pixel array (see e.g., the pixel array unit comprising unit pixels PX where photodiodes 140 and 150 are formed in the substrate 100, Paras [0028] – [0029], Figures 2 and 3F);
forming, in the substrate, a drain region for the pixel sensor (see e.g., forming in the substrate the floating diffusion region shared by the drains of the transfer transistors, Paras [0028] - [0029], Figure 3F);
forming, in the substrate, a trench adjacent to the photodiode and the drain region (see e.g., pixel trench 100a’ formed in the substrate 100 adjacent to the photodiodes 140 and 150, Paras [0028] - [0029], Figure 3F);
forming a boron on sidewalls of the trench and on a bottom surface of the trench (see e.g., The channel stop impurity region 106 conformally surrounds the bottom and the sidewall of the pixel trench 100a', and the dark current and noise caused by an interfacial surface defect of the pixel trench 100a' can be decreased. Boron (p-type dopant material) is doped into the channel stop impurity region 106, Para [0048], Figure 3F);
forming a layer on the boron; and (see e.g., oxide layer 108, which maybe a thermal oxide layer, formed within the pixel trench 100a’ on the channel stop impurity region 106, Para [0051], Figure 3F)
filling the trench with an oxide material over the layer to form a deep trench isolation (DTI) structure (see e.g., a gap-filling material layer 107 formed within the impurity-doped pixel trench 100a. The gap-filling material layer 107 may comprise an insulating material, such as for example, a High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide’, Para [0053], Figure 3F).
Kwon does not explicitly teach
“forming, in the substrate and a deep p-well (DPW) region,…. wherein the trench is in direct contact with the substrate and the DPW region”;
In a similar field of endeavor Hong teaches
forming, in the substrate and a deep p-well (DPW) region,…. wherein the trench is in direct contact with the substrate and the DPW region (see e.g., device isolation region 53 in the substrate 1 which is doped with p-type impurities. The deep pixel isolation section DTI is in direct contact with the substrate 1 and the device isolation region 53, Paras [0077], [0025], Figure 21)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hong’s teachings of forming, in the substrate and a deep p-well (DPW) region,…. wherein the trench is in direct contact with the substrate and the DPW region in the method of Kwon in order to isolate photodiodes.
Kwon does not explicitly teach
“forming a boron layer on sidewalls of the trench and on a bottom surface of the trench;
performing an annealing operation to anneal the boron layer after forming the boron layer;
forming a layer on the boron layer after performing the annealing operation;”
In a similar field of endeavor Muramatsu teaches
forming a boron layer on sidewalls of the trench and on a bottom surface of the trench (see e.g., boron layer 11 is formed on the inner surface 9a of the trench 9 by vapor phase growth method, para [0027], Figures 2 and 5);
performing an annealing operation to anneal the boron layer after forming the boron layer (see e.g., a thermal process is performed after forming the boron layer 11 which causes boron to diffuse into a portion of the semiconductor substrate, Paras [0022], [0025], Figures 2 and 6);
forming a layer on the boron layer after performing the annealing operation; and (see e.g., a silicon oxide layer 7 is formed on the boron layer 11 after the thermal process, Paras [0020], Figures 2 and 7).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Muramatsu’s teachings of forming a boron layer on sidewalls of the trench and on a bottom surface of the trench; performing an annealing operation to anneal the boron layer after forming the boron layer; forming a layer on the boron layer after performing the annealing operation in the method of Kwon in order to reduce crosstalk.
Kwon does not explicitly teach
“forming a silicon layer…
filling the trench with an oxide material over the silicon layer…”
In a similar field of endeavor Cheng teaches
forming a silicon layer …(see e.g., trench lined with boron-doped Si epitaxial layer 111a, pure Si epitaxial layer 111b, Paras [0016] – [0018], Figure 1C)
filling the trench with an oxide material over the silicon layer…(see e.g., dielectric material 112 maybe silicon oxide filled in the trench over the Si epitaxial layer 111b, Paras [0015] –[0016], Figure 1C)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of forming a silicon layer…
filling the trench with an oxide material over the silicon layer in the method of Kwon in order to meet different device requirements such as junction, leakage and strain engineering.
Regarding claim 16, Kwon, as modified by Hong, Muramatsu and Cheng, teaches the limitations of claim 15 as mentioned above. Kwon does not explicitly teach
“wherein forming the silicon layer comprises: depositing the silicon layer at a temperature that is in a range of approximately 250 degrees Celsius to approximately 450 degrees Celsius”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cheng teaches
wherein forming the silicon layer comprises: depositing the silicon layer at a temperature that is in a range of approximately 250 degrees Celsius to approximately 450 degrees Celsius (see e.g., Si epitaxial layer 311b is formed at a temperature range from about 400.degree. C. to 800.degree. C, Para [0028], Figure 3C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of wherein forming the silicon layer comprises: depositing the silicon layer at a temperature that is in a range of approximately 250 degrees Celsius to approximately 450 degrees Celsius in the method of Kwon in order to epitaxially grow the Si epitaxial layer.
Regarding claim 17, Kwon, as modified by Hong, Muramatsu and Cheng, teaches the limitations of claim 15 as mentioned above. Kwon does not explicitly teach
“wherein forming the silicon layer comprises: depositing the silicon layer at a pressure that is in a range of approximately 10 torr to approximately 500 torr.”
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cheng teaches
wherein forming the silicon layer comprises: depositing the silicon layer at a pressure that is in a range of approximately 10 torr to approximately 500 torr (see e.g., epitaxial layer 311b is formed at a a pressure range from about 5 torr to about 500 torr, Para [0028], Figure 3C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of wherein forming the silicon layer comprises: depositing the silicon layer at a pressure that is in a range of approximately 10 torr to approximately 500 torr in the method of Kwon in order to epitaxially grow the Si epitaxial layer.
Regarding claim 19, Kwon, as modified by Hong, Muramatsu and Cheng, teaches the limitations of claim 15 as mentioned above. Kwon does not explicitly teach
“wherein forming the boron layer comprises: forming the boron layer to a thickness that is in a range of approximately 1 nanometer to approximately 5 nanometers”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Muramatsu teaches
wherein forming the boron layer comprises: forming the boron layer to a thickness that is in a range of approximately 1 nanometer to approximately 5 nanometers (see e.g., The boron layer 11 is formed isotropically with a thickness of a few nm to several tens nm on the inner surface 9a of the trench 9 by a vapor phase growth method such as chemical vapor deposition (CVD) epitaxial growth or the like, Para [0025], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Muramatsu’s teachings of wherein a thickness of the boron layer is in a range of approximately 1 nanometer to approximately 5 nanometers in the method of Kwon in order to meet device requirements.
Regarding claim 20, Kwon, as modified by Hong, Muramatsu and Cheng, teaches the limitations of claim 15 as mentioned above. Kwon does not explicitly teach
“wherein forming the silicon layer comprises: forming the silicon layer to a thickness that is in a range of approximately 1 nanometer to approximately 5 nanometers”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cheng teaches
wherein a thickness of the silicon layer is in a range of approximately 1 nanometer to approximately 5 nanometers (see e.g., the pure Si epitaxial layer 111b has a thickness ranging from 1nm to about 10nm, Para [0017], Figure 1C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of wherein a thickness of the silicon layer is in a range of approximately 1 nanometer to approximately 5 nanometers in the method of Kwon in order to meet different device requirements such as junction, leakage and strain engineering.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2009/0315137 A1; hereafter Kwon) in view of Cheng et al. (US 20150115397 A1; hereafter Cheng), Muramatsu al. (US 2018/0286899 A1; hereafter Muramatsu), Hong et al. (US 2020/0111821 A1; hereafter Hong) and further in view of Nakazawa et al. (US 2011/0207267 A1; hereafter Nakazawa).
Regarding claim 18, Kwon, as modified by Hong, Muramatsu and Cheng, teaches the limitations of claim 15 as mentioned above. Kwon does not explicitly teach
“wherein performing the annealing operation comprises: using a laser-based surface annealing technique to perform the annealing operation.”
In a similar field of endeavor Nakazawa teaches
wherein performing the annealing operation comprises: using a laser-based surface annealing technique to perform the annealing operation (see e.g., laser annealing boron ion implantation layers, Para [0088]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was filed to implement Nakazawa teachings’ of wherein performing the annealing operation comprises: using a laser-based surface annealing technique to perform the annealing operation in the method of Kwon as laser annealing represents one of various well-known options available for performing annealing.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2009/0315137 A1; hereafter Kwon) in view of Hong et al. (US 2020/0111821 A1; hereafter Hong) and Mohammadi, et al., (2017). A doping-less junction-formation mechanism between n-silicon and an atomically thin boron layer. Scientific Reports. 7. 13247. 10.1038/s41598-017-13100-0; hereafter Mohammadi.
Regarding claim 21, Kwon teaches a method (see Figures 3A-3F), comprising:
forming a trench, adjacent to a photodiode and a drain region, in a substrate (see e.g., pixel trench 100a’ formed in the substrate 100 adjacent to the photodiodes 140 and 150 and the floating diffusion region shared by the drains of the transfer transistors, Paras [0028] - [0029], Figure 3F)
wherein the substrate comprises the photodiode, drain region (see e.g., the substrate 100 comprises the photodiodes 140 and 150 and the floating diffusion region FD shared by the drains of the transfer transistors, Paras [0028] - [0029], Figure 3F),
forming a passivation layer, comprising an amorphous boron material or a boron material, in the trench, (see e.g., The channel stop impurity region 106 conformally surrounds the bottom and the sidewall of the pixel trench 100a', and the dark current and noise caused by an interfacial surface defect of the pixel trench 100a' can be decreased. Boron is doped into the channel stop impurity region 106, Para [0048], Figure 3F);
forming a capping layer on the passivation layer (see e.g., oxide layer 108, which maybe a thermal oxide layer, formed within the pixel trench 100a’ on the channel stop impurity region, Para [0051], Figure 3F.); and
filling the trench with an oxide material over the capping layer to form a deep trench isolation (DTI) structure (see e.g., a gap-filling material layer 107 formed within the impurity-doped pixel trench 100a. The gap-filling material layer 107 may comprise an insulating material, such as for example, a High Density Plasma-Chemical Vapor Deposition (HDP-CVD) oxide’, Para [0053], Figure 3F).
Kwon does not explicitly teach
“forming a trench,… in a substrate and at least partially in a deep p-well (DPW) region,
wherein a top portion of the trench is in direct contact with the substrate and a bottom portion of the trench is in direct contact with the DPW region,
wherein the substrate comprises …the DPW region;”
In a similar field of endeavor Hong teaches
forming a trench,… in a substrate and at least partially in a deep p-well (DPW) region, (see e.g., the deep pixel isolation section (DTI) formed in the substrate 1 is partially in the device isolation region 53 which is doped with p-type impurities, Paras [0077], [0025], Figure 21);
wherein a top portion of the trench is in direct contact with the substrate and a bottom portion of the trench is in direct contact with the DPW region (see e.g., the top portion of the DTI is in direct contact with the substrate 1 and the bottom portion of the DTI is in direct contact with the device isolation region 53, Figure 21),
wherein the substrate comprises …the DPW region (see e.g., the device isolation region 53 is formed in the substrate 1, Figure 21);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hong’s teachings of forming a trench,… in a substrate and at least partially in a deep p-well (DPW) region, wherein a top portion of the trench is in direct contact with the substrate and a bottom portion of the trench is in direct contact with the DPW region, wherein the substrate comprises …the DPW region in the method of Kwon in order to isolate photodiodes.
Kwon does not explicitly teach
“wherein the amorphous boron material or the boron material are bonded directly to silicon of the substrate to form a depletion region in the substrate;”
In a similar field of endeavor Mohammadi teaches
wherein the amorphous boron material or the boron material are bonded directly to silicon of the substrate to form a depletion region in the substrate (see e.g., amorphous boron is deposited over silicon to form a boron-silicon interface. At the interface, various chemical bonds and an interface B atom may be connected to one or two Si atoms beyond the B-B bonds. Therefore, the interfacial B has three to five neighbors, similar to both those in the amorphous bulk and those in the crystalline B phases. This chemically strong Si-B bonding indicates a strong mechanical Si-B interface. The B-Si junction formation can be described with the charge transfer which occurs at the c-Si/a-B interface. The notable difference in electronegativity (2.04 for B and 1.90 for Si) indicates ionicity of the Si-B bonds. For c-Si/a-B interface systems, the charge transfers mainly from the interface Si atoms to the neighboring B. Statistics show that lost electron values of the interface Si ions range from 0.40 to 0.97 e/Si with an average value of 0.76 e/Si, Results and Discussion, Figure 2)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Mohammadi’s teachings of wherein the amorphous boron material or the boron material are bonded directly to silicon of the substrate to form a depletion region in the substrate in the method of Kwon in order to achieve a stable interface.
Claims 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2009/0315137 A1; hereafter Kwon) in view of Hong et al. (US 2020/0111821 A1; hereafter Hong) and Mohammadi, et al., (2017). A doping-less junction-formation mechanism between n-silicon and an atomically thin boron layer. Scientific Reports. 7. 13247. 10.1038/s41598-017-13100-0; hereafter Mohammadi and further in view of Muramatsu al. (US 2018/0286899 A1; hereafter Muramatsu).
Regarding claim 22, Kwon, as modified by Hong and Mohammadi, teaches the limitations of claim 21 as mentioned above. Kwon does not explicitly teach
“wherein the passivation layer comprises a boron layer”.
In a similar field of endeavor Muramatsu teaches
wherein the passivation layer comprises a boron layer (see e.g., boron layer 11 formed on an inner surface 9a of the trench 9 by a vapor phase growth method. The boron layer 11 is formed to continuously cover the entire inner surface 9a of the trench 9, Para [0022], Figure 2).
Muramatsu is being used to only teach the concept that a boron layer can be formed on an inner surface of a trench.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Muramatsu’s teachings of a wherein the passivation layer comprises a boron layer in the method of Kwon in order to provide p-type dopants.
Regarding claim 23, Kwon, as modified by Hong, Mohammadi and Muramatsu, teaches the limitations of claim 21 as mentioned above. Kwon does not explicitly teach
“wherein a thickness of the boron layer is in a range of approximately 1 nanometer to approximately 5 nanometers”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Muramatsu teaches
wherein a thickness of the boron layer is in a range of approximately 1 nanometer to approximately 5 nanometers (see e.g., The boron layer 11 is formed isotropically with a thickness of a few nm to several tens nm on the inner surface 9a of the trench 9 by a vapor phase growth method such as chemical vapor deposition (CVD) epitaxial growth or the like, Para [0025], Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Muramatsu’s teachings of wherein a thickness of the boron layer is in a range of approximately 1 nanometer to approximately 5 nanometers in the method of Kwon in order to introduce enough dopants to form a required depletion region width.
Claims 24-27 are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al. (US 2009/0315137 A1; hereafter Kwon) in view of Hong et al. (US 2020/0111821 A1; hereafter Hong) and Mohammadi, et al., (2017). A doping-less junction-formation mechanism between n-silicon and an atomically thin boron layer. Scientific Reports. 7. 13247. 10.1038/s41598-017-13100-0; hereafter Mohammadi and further in view of Cheng et al. (US 20150115397 A1; hereafter Cheng).
Regarding claim 24, Kwon, as modified by Hong and Mohammadi, teaches the limitations of claim 21 as mentioned above. Kwon does not explicitly teach
“wherein the capping layer is a silicon layer”.
In a similar field of endeavor Cheng teaches
wherein the capping layer is a silicon layer (see e.g., trench lined with boron-doped Si epitaxial layer 111a, pure Si epitaxial layer 111b and a protection layer 130 such as silicon oxide. The dielectric material 112, silicon oxide, is filled over the pure Si epitaxial layer 111b, Paras [0016] - [0018], Figure 1C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of wherein the capping layer is a silicon layer in the method of Kwon in order to meet different device requirements such as junction, leakage and strain engineering.
Regarding claim 25, Kwon, as modified by Hong, Mohammadi and Cheng, teaches the limitations of claim 24 as mentioned above. Kwon does not explicitly teach
“wherein a thickness of the silicon layer is in a range of approximately 1 nanometer to approximately 5 nanometers”.
Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Cheng teaches
wherein a thickness of the silicon layer is in a range of approximately 1 nanometer to approximately 5 nanometers (see e.g., the pure Si epitaxial layer 111b has a thickness ranging from 1nm to about 10nm, Para [0017], Figure 1C).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Cheng’s teachings of wherein a thickness of the silicon layer is in a range of approximately 1 nanometer to approximately 5 nanometers in the method of Kwon in order to meet different device requirements such as junction, leakage and strain engineering.
Regarding claim 26, Kwon, as modified by Hong, Mohammadi and Cheng, teaches the limitations of claim 24 as mentioned above. Kwon does not explicitly teach
“wherein the depletion region is configured to resist photon penetration into the DTI structure”.
In a similar field of endeavor Mohammadi teaches
wherein the depletion region is configured to resist photon penetration into the DTI structure (see e.g., amorphous boron is deposited over silicon to form a boron-silicon interface. At the interface, various chemical bonds and an interface B atom may be connected to one or two Si atoms beyond the B-B bonds. Therefore, the interfacial B has three to five neighbors, similar to both those in the amorphous bulk and those in the crystalline B phases. This chemically strong Si-B bonding indicates a strong mechanical Si-B interface. The B-Si junction formation can be described with the charge transfer which occurs at the c-Si/a-B interface. The notable difference in electronegativity (2.04 for B and 1.90 for Si) indicates ionicity of the Si-B bonds. For c-Si/a-B interface systems, the charge transfers mainly from the interface Si atoms to the neighboring B. Statistics show that lost electron values of the interface Si ions range from 0.40 to 0.97 e/Si with an average value of 0.76 e/Si, Results and Discussion, Figure 2);
Mohammadi teaches a similar structure therefore the outcome should also be similar.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Mohammadi’s teachings of wherein the depletion region is configured to resist photon penetration into the DTI structure in the method of Kwon in order to prevent electrical crosstalk.
Regarding claim 27, Kwon, as modified by Hong, Mohammadi and Cheng, teaches the limitations of claim 26 as mentioned above. Kwon does not explicitly teach
“wherein a negative charge of the passivation layer is configured to facilitate formation of the depletion region.”
In a similar field of endeavor Mohammadi teaches
wherein a negative charge of the passivation layer is configured to facilitate formation of the depletion region (see e.g., amorphous boron is deposited over silicon to form a boron-silicon interface. At the interface, various chemical bonds and an interface B atom may be connected to one or two Si atoms beyond the B-B bonds. Therefore, the interfacial B has three to five neighbors, similar to both those in the amorphous bulk and those in the crystalline B phases. This chemically strong Si-B bonding indicates a strong mechanical Si-B interface. The B-Si junction formation can be described with the charge transfer which occurs at the c-Si/a-B interface. The notable difference in electronegativity (2.04 for B and 1.90 for Si) indicates ionicity of the Si-B bonds. For c-Si/a-B interface systems, the charge transfers mainly from the interface Si atoms to the neighboring B. Statistics show that lost electron values of the interface Si ions range from 0.40 to 0.97 e/Si with an average value of 0.76 e/Si, Results and Discussion, Figure 2).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Mohammadi’s teachings of wherein a negative charge of the passivation layer is configured to facilitate formation of the depletion region in the method of Kwon in order to prevent electrical crosstalk.
Allowable Subject Matter
Claims 8-14 are allowed.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 8, Kwon (US 2009/0315137 A1) discloses a method (see e.g., Figures 3A-3F), but fails to disclose the specific characteristic recited in the claims of the instant invention e.g., the combination of claimed features of forming in a substrate, a photodiode for a pixel sensor, forming in the substrate a drain region for the pixel sensor, forming in the substrate a trench adjacent to the photodiode and the drain region in conjunction with “forming an amorphous boron layer on sidewalls of the trench and on a bottom surface of the trench”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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