Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the filing of the Applicant Arguments/Remarks Made in an Amendment on 01/15/2026. Currently, claims 1-5, 7-13 and 15-20 are pending in the application. Claims 6 and 14 have been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-13 and 15-16 are rejected under 35 U.S.C. 103 as being obvious over Wang et al (US 20190109096 A1).
Regarding claim 1, Figures 8 of Wang discloses a package structure with a wettable side surface, comprising:
a first dielectric layer (123, [0032]) provided with a package cavity (for 30), first side wall bonding pads (119, [0035]) being in contact with outermost side walls of the first dielectric layer and located outside the package cavity as outermost side wall bonding pads of the package structure;
a chip (30, [0036]) packaged inside the package cavity, pins (101) on an active surface of the chip facing a first surface of the first dielectric layer; and
a circuit layer (131) arranged on the first surface of the first dielectric layer (123) and connected to the first side wall bonding pads (119) and the pins (101) on the active surface of the chip, wherein a functional area (surface of 30 at 101) is arranged on the active surface of the chip, and the functional area is exposed out of the first dielectric layer (123), the active surface of the chip is exposed and the pins (101) on the active surface of the chip are exposed out of the first dielectric layer (123).
Wang does not explicitly teach that the functional area is exposed out of the first dielectric layer (123), the active surface of the chip is exposed and the pins (101) on the active surface of the chip are exposed out of the first dielectric layer (123) so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection.
However, the above limitation does not distinguish the present invention over the prior art of Wang which teaches the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Regarding claim 2, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 1, wherein the circuit layer (131, [0034]) is directly connected to the first side wall bonding pads (119) or connected to the first side wall bonding pads via second electrically conductive through-hole posts, and the circuit layer (131) is further directly connected to the pins (101) on the active surface of the chip (30) or connected to the pins on the active surface of the chip via first electrically conductive through- hole posts.
Regarding claim 3, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 2, wherein the circuit layer (131) is provided in plural (considering the layer directly on 101), and two adjacent circuit layers are connected via third electrically conductive through-hole posts (133, [0033]).
Regarding claim 4, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 1, wherein a heat dissipation layer (109+121, [0036], considering metal coating and bonding layer acting as heat dissipation on a broadest reasonable interpretation) is arranged on a second surface of the first dielectric layer, and the heat dissipation layer is directly connected to a heat dissipation surface of the chip (30) or connected to the heat dissipation surface of the chip via first thermally conductive through-hole posts.
Regarding claim 5, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 1, wherein the circuit layer (131) is provided with bottom bonding pads (137, [0035]), and at least one of the first side wall pads and the bottom pads (137) is placed with solder balls (143).
Regarding claim 7, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 1, wherein a transparent second surface protective layer (132, [0033], considering the materials having some transparency on a broadest reasonable interpretation since the claim in not explicit regarding transparency) is arranged on the active surface of the chip (30).
Regarding claim 8, Figures 8 of Wang discloses that the package structure with a wettable side surface according to claim 1, wherein a non-transparent second surface protective layer (132) is arranged on the active surface of the chip, and a window (at 132) corresponding to the functional area (top surface area of 30 at 101) is arranged on the second surface protective layer.
Regarding claim 9, Figures 8 of Wang discloses a vertical package module, comprising a packaging structure with a wettable side surface comprising:
a first dielectric layer (123, [0030]) provided with a package cavity (for 30), first side wall bonding pads (119, [0035]) being in contact with outermost side walls of the first dielectric layer (123) and located outside the package cavity as outermost side wall bonding pads of the package structure;
a chip (30, [0036]) packaged inside the package cavity, pins (101, [0017]) on an active surface of the chip facing a first surface of the first dielectric layer; and
a circuit layer (131, [0033]) arranged on the first surface of the first dielectric layer and connected to the first side wall bonding pads (119) and the pins (101) on the active surface of the chip, wherein a functional area (surface of 30 at 101) is arranged on the active surface of the chip, and the functional area is exposed out of the first dielectric layer (123), the active surface of the chip is exposed and the pins (101) on the active surface of the chip are exposed out of the first dielectric layer (123).
Wang does not explicitly teach that the functional area is exposed out of the first dielectric layer (123), the active surface of the chip is exposed and the pins (101) on the active surface of the chip are exposed out of the first dielectric layer (123) so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection.
However, the above limitation does not distinguish the present invention over the prior art of Wang which teaches the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Regarding claim 10, Figures 8 of Wang discloses that the vertical package module according to claim 9, wherein the circuit layer (131) is directly connected to the first side wall bonding pads (119) or connected to the first side wall bonding pads via second electrically conductive through-hole posts, and the circuit layer (131) is further directly connected to the pins on the active surface of the chip or connected to the pins (101) on the active surface of the chip via first electrically conductive through-hole posts (between 101 and 131).
Regarding claim 11, Figures 8 of Wang discloses that the vertical package module according to claim 10, wherein the circuit layer (131, [0033]) is provided in plural (considering layer directly on 101), and two adjacent circuit layers are connected via third electrically conductive through-hole posts (133, [0033]).
Regarding claim 12, Figures 8 of Wang discloses that the vertical package module according to claim 9, wherein a heat dissipation layer (109, conductive coating, works a heat dissipation on a broadest reasonable interpretation, [0019]) is arranged on a second surface of the first dielectric layer, and the heat dissipation layer (109) is directly connected to a heat dissipation surface of the chip (30) or connected to the heat dissipation surface of the chip via first thermally conductive through-hole posts.
Regarding claim 13, Figures 8 of Wang discloses that the vertical package module according to claim 9, wherein the circuit layer (131) is provided with bottom bonding pads (137), and at least one of the first side wall pads and the bottom pads (137) is placed with solder balls (143).
Regarding claim 15, Figures 8 of Wang discloses that the vertical package module according to claim 9, wherein a transparent second surface protective layer (132, [0033], considering the material of 132 has some transparency on a broadest reasonable interpretation since the claim is explicit regarding transparency) is arranged on the active surface of the chip.
Regarding claim 16, Figures 8 of Wang discloses that the vertical package module according to claim 9, wherein a non-transparent second surface protective layer (132, [0033]) is arranged on the active surface of the chip, and a window (at 132) corresponding to the functional area (top area of 30 at 101) is arranged on the second surface protective layer.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being obvious over GONG et al (US 20160181202 A1).
Regarding claim 1, Figure 14 of GONG discloses a package structure with a wettable side surface, comprising:
a first dielectric layer (504, [0039]) provided with a package cavity (for 502), first side wall bonding pads (1101, [0058]) being in contact with outermost side walls of the first dielectric layer and located outside the package cavity as outermost side wall bonding pads of the package structure;
a chip (502, [0039]) packaged inside the package cavity, pins (402, [0034]) on an active surface of the chip facing a first surface of the first dielectric layer; and
a circuit layer (713, [0043]) arranged on the first surface of the first dielectric layer and connected to the first side wall bonding pads (1101) and the pins (402) on the active surface of the chip (502), wherein a functional area (surface of 502 at 402) is arranged on the active surface of the chip, and the functional area is exposed out of the first dielectric layer (504), the active surface of the chip is exposed and the pins (402) on the active surface of the chip are exposed out of the first dielectric layer (504).
GONG does not explicitly teach that the functional area is exposed out of the first dielectric layer, the active surface of the chip is exposed and the pins on the active surface of the chip are exposed out of the first dielectric layer so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection.
However, the above limitation does not distinguish the present invention over the prior art of GONG which teaches the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Regarding claim 9, Figure 14 of GONG discloses a vertical package module, comprising a packaging structure with a wettable side surface comprising:
a first dielectric layer (504, [0039]) provided with a package cavity (for 502), first side wall bonding pads (1101, [0058]) being in contact with outermost side walls of the first dielectric layer and located outside the package cavity as outermost side wall bonding pads of the package structure;
a chip (502, [0039]) packaged inside the package cavity, pins (402, [0034]) on an active surface of the chip facing a first surface of the first dielectric layer; and
a circuit layer (713, [0043]) arranged on the first surface of the first dielectric layer and connected to the first side wall bonding pads (1101) and the pins (402) on the active surface of the chip (502), wherein a functional area (surface of 502 at 402) is arranged on the active surface of the chip, and the functional area is exposed out of the first dielectric layer (504), the active surface of the chip is exposed and the pins (402) on the active surface of the chip are exposed out of the first dielectric layer (504).
GONG does not explicitly teach that the functional area is exposed out of the first dielectric layer, the active surface of the chip is exposed and the pins on the active surface of the chip are exposed out of the first dielectric layer so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection.
However, the above limitation does not distinguish the present invention over the prior art of GONG which teaches the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Claims 17 and 19 are rejected under 35 U.S.C. 103 as being obvious over Pagaila et al (US 20090294914 A1).
Regarding claim 17, Figure 13 of Pagaila discloses a vertical package module, comprising:
a printed circuit board (362, [0065]);
package units (350, [0065]), each being provided with second outermost side wall bonding pads (168, under 354, [0065]) and soldered on the printed circuit board via the second outermost side wall bonding pads, first surfaces (side surfaces of 350) of the package units being perpendicular to the printed circuit board; and
packaged devices (366, [0065]) with a functional area, each of the packaged devices being packaged in a respective one of the package units and electrically connected to the second outermost side wall bonding pads (layer under 354), and a functional area of each of the packaged devices facing a respective first surface of a respective one of the package units (considering bottom area of 366 facing the top side of 350 on a broadest reasonable interpretation since the functional area is not structurally defined in the claim).
Figure 13 of Pagaila does not teach plurality of package units and plurality of packaged devices.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the vertical package module with plurality of package units and plurality of packaged devices in order to form a module with multiple integrated devices to save space and cost for making higher capacity, since the court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In reHarza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Further, Figure 13 of Pagaila does not explicitly teach that the functional area of each of the packaged devices being exposed to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection.
However, the above limitation does not distinguish the present invention over the prior art of Pagaila which teaches the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Regarding claim 19, Figure 13 of Pagaila discloses that the vertical package module according to claim 17, wherein an upper surface or a lower surface of the printed circuit board (362) is provided with a projecting part (372).
Allowable Subject Matter
Claims 18 and 20 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a vertical package module, comprising:
The vertical package module according to claim 17, wherein an indentation is formed in a surface or side of the printed circuit board, first bonding pads are arranged in the indentation, and the second outermost side wall bonding pads are connected to the first bonding pads by welding.
Regarding claim 20, there is no prior art available nor obvious motivation to combine elements of prior art which teaches a vertical package module, comprising:
The vertical package module according to claim 19, wherein second bonding pads are arranged on the projecting part, each of the package units is further provided with bottom bonding pads, and the bottom bonding pads are connected to the second bonding pads by welding.
Response to Arguments
Applicant's arguments filed on 01/15/2026 have been fully considered but they are not persuasive.
Applicant’s main argument regarding claims 1, 9 and 17 include: The prior arts of record do not teach “the functional area is exposed out of the first dielectric layer, the active surface of the chip is exposed and the pins on the active surface of the chip are exposed out of the first dielectric layer so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection” in claims 1 and 9, and further “wherein a functional area is arranged on the active surface of the chip, and the functional area is exposed out of the first dielectric layer, the active surface of the chip is exposed and the pins on the active surface of the chip are exposed out of the first dielectric layer, so as to facilitate completion of functions of signal transmission, signal reception, signal conduction and signal detection” in claim 17.
In response, the Examiner respectfully disagrees and points out that these above limitation does not distinguish the present invention over the prior arts of record which teach the structure as claimed, wherein the structure is capable of performing the above function. Moreover, it has been held that claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). Further, The Examiner notes that where the Patent Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact, be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on. (In re Swinehart and Sfiligoj, 169 USPQ 226 (C.C.P.A. 1971)).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday to Friday from 8:00 AM to 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAJA AHMAD/
Primary Examiner, Art Unit 2813