DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 8/8/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-16, and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (EP 3648172 A1) in view of Stephenson et al. (US 2019/0279897 A1).
Regarding claim 1, Lee discloses a method comprising:
forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
forming a dopant diffusion liner (151) (figure 11A, ¶ 77) adjacent at least one of the source and drain regions.
Lee fails to teach:
a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Stephenson teaches:
a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60),
Therefore, it would have been obvious to one of ordinary skill in the art before, the effective filing date of the claimed invention, to combine the references above, because the liner is a barrier to dopant diffusion.
Stephenson further discloses forming a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see figure 3).
Regarding claim 2, Stephenson further discloses the dopant diffusion liner comprises respective portions adjacent each of the source and drain regions (figure 6, liner 25 as a source/ drain contact).
Regarding claim 4, Stephenson further discloses forming a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 5, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 6, Stephenson further discloses forming a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 7, Lee further discloses wherein the gate (125) comprises a metal (¶ 45).
Regarding claim 8, Stephenson further discloses wherein the base semiconductor portion comprises silicon (¶ 40).
Regarding claim 9, Stephenson further discloses wherein the at least one non-semiconductor monolayer comprises oxygen (¶ 40).
Regarding claim 10, Lee teaches forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
Lee fails to teach:
a first superlattice within at least one of the nanostructures, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Stephenson teaches forming a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60), further comprising a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. (see figure 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references above, because the liner is a barrier to dopant diffusion.
Regarding claim 11, Stephenson further discloses forming a second superlattice embedded in the semiconductor substrate extending between the source and drain regions, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 12, Stephenson further discloses forming a third superlattice on the semiconductor substrate beneath the source region, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 13, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the drain region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 14, Lee further discloses the gate (125) comprises a metal (¶ 45).
Regarding claim 15, Lee teaches forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
forming a dopant diffusion liner (151) (figure 11A, ¶ 77) adjacent at least one of the source and drain regions.
Lee fails to teach:
forming a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.
Stephenson teaches
a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60), wherein the semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen. (¶ 40)
Therefore, it would have been obvious to one of ordinary skill in the art before, the effective filing date of the claimed invention, to combine the references above, because the liner is a barrier to dopant diffusion.
Stephenson further discloses forming a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. (see figure 3).
Regarding claim 18, Stephenson further discloses forming a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 19, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 20, Stephenson further discloses forming a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 21, Lee further discloses wherein the gate (125) comprises a metal (¶ 45).
Response to Arguments
Applicant's arguments filed 8/8/2025 have been fully considered but they are not persuasive.
Applicant argues that Stephenson does not disclose the specific placement of the superlattice. This argument is not persuasive as Stephenson is relied upon for disclosing the composition of the superlattice.
Applicant further argues that neither Lee nor Stephenson individually discloses all of the claim limitations. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant further alleges unexpected results. This argument is not persuasive there is no discussion of “unexpected results” within the Application as originally filed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A CULBERT whose telephone number is (571)272-4893. The examiner can normally be reached M-F 9-5.
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/CHRISTOPHER A CULBERT/ Examiner, Art Unit 2815