DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to Amendments filed 4/9/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 2, 4-16, and 18-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding independent claims 1, 10, and 15, each of these claims has been amended to require the second (or first) superlattice structure to provide work function tuning so that the nanostructure has a lower threshold voltage than it would without the nanostructure (i.e., removing the nanostructure increases the threshold voltage of the nanostructure). This language is indefinite as one having ordinary skill in the art would not know how to interpret the nanostructure having any threshold voltage (let alone a greater threshold voltage) if the nanostructure itself does not even exist. For the purpose of this Office action, “forming a second [or first] superlattice within at least one of the nanostructures to provide work function tuning for the gate-all-around device so that the at least one nanostructure has a lower threshold voltage (Vt) than it would without the at least one nanostructure” is interpreted as “forming a second [or first] superlattice within at least one of the nanostructures”.
Claims 2, 4-9, 11-14, 16, and 18-21 depend from one of claims 1, 10, and 15 and are, therefore, also rejected.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 4-16, and 18-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (EP 3648172 A1) in view of Stephenson et al. (US 2019/0279897 A1).
Regarding claim 1, Lee discloses a method comprising:
forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
forming a dopant diffusion liner (151) (figure 11A, ¶ 77) adjacent at least one of the source and drain regions.
Lee fails to teach:
a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Stephenson teaches:
a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60),
Therefore, it would have been obvious to one of ordinary skill in the art before, the effective filing date of the claimed invention, to combine the references above, because the liner is a barrier to dopant diffusion.
Stephenson further discloses forming a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see figure 3).
Regarding claim 2, Stephenson further discloses the dopant diffusion liner comprises respective portions adjacent each of the source and drain regions (figure 6, liner 25 as a source/ drain contact).
Regarding claim 4, Stephenson further discloses forming a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 5, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 6, Stephenson further discloses forming a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 7, Lee further discloses wherein the gate (125) comprises a metal (¶ 45).
Regarding claim 8, Stephenson further discloses wherein the base semiconductor portion comprises silicon (¶ 40).
Regarding claim 9, Stephenson further discloses wherein the at least one non-semiconductor monolayer comprises oxygen (¶ 40).
Regarding claim 10, Lee teaches forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement.
Lee fails to teach:
a first superlattice within at least one of the nanostructures, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
Stephenson teaches forming a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60), further comprising a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. (see figure 3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the references above, because the liner is a barrier to dopant diffusion.
Regarding claim 11, Stephenson further discloses forming a second superlattice embedded in the semiconductor substrate extending between the source and drain regions, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 12, Stephenson further discloses forming a third superlattice on the semiconductor substrate beneath the source region, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 13, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the drain region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 14, Lee further discloses the gate (125) comprises a metal (¶ 45).
Regarding claim 15, Lee teaches forming source and drain regions (Figure 11A, 161 and 162) on a semiconductor substrate (figure 11A, element 100);
forming a plurality of semiconductor nanostructures (S1-S4), (¶ 78) extending between the source and drain regions;
forming a gate (figure 11A, 120) surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement; and
forming a dopant diffusion liner (151) (figure 11A, ¶ 77) adjacent at least one of the source and drain regions.
Lee fails to teach:
forming a dopant diffusion liner adjacent at least one of the source and drain regions and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions.
Stephenson teaches
a superlattice structure comprising energy band-modifying layers (Figure 3, 50), these layers are monolayers of non-semiconductor material. (¶ 55-60), wherein the semiconductor device of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen. (¶ 40)
Therefore, it would have been obvious to one of ordinary skill in the art before, the effective filing date of the claimed invention, to combine the references above, because the liner is a barrier to dopant diffusion.
Stephenson further discloses forming a second superlattice within at least one of the nanostructures, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions. (see figure 3).
Regarding claim 18, Stephenson further discloses forming a third superlattice embedded in the semiconductor substrate extending between the source and drain regions, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 19, Stephenson further discloses forming a fourth superlattice on the semiconductor substrate beneath the source region, the fourth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 20, Stephenson further discloses forming a fifth superlattice on the semiconductor substrate beneath the drain region, the fifth superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non- semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions (see Figure 3, setting “n’” to be sufficiently large).
Regarding claim 21, Lee further discloses wherein the gate (125) comprises a metal (¶ 45).
Response to Arguments
Applicant's arguments filed 4/9/2026 have been fully considered but they are not persuasive.
Applicant argues that Lee in view of Stephenson does not disclose the newly added threshold voltage limitations in claims 1, 10, and 15. This argument is not persuasive as the newly added limitations are indefinite, as discussed in the 35 U.S.C. § 112 rejections above.
Applicant further argues that the reason for incorporating the superlattice architecture of Stephenson is different than the reason for using a superlattice architecture set forth in Applicant’s Specification. This argument is not persuasive as “It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant” (MPEP 2144(IV)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.C/ Examiner, Art Unit 2815
/JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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