DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14, 16-21, 23-28, 35, and 36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chun et al. (US 2020/0251407) in view of Ting et al. (US 2019/0148329) and Hsia et al. (US 2011/0266674).
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With regard to claim 14, Chun teaches, in Fig 1B annotated and reproduced here, forming one or more redistribution layers (RDLs of 145, [0033], see annotated Figure 1B reproduced above) that include one or more electrically-conductive traces (Ts of 147, [0033], see annotated Figure 1B reproduced above) on a top surface of a silicon substrate (SS of 139 and the top surface of SS, [0032], see annotated Figure 1B reproduced above); forming a passivation layer (topmost occurrence of 145, [0033]) including pad structures (PS of 149/147, [0033], see annotated Figure 1B reproduced above) over the one or more redistribution layers; and forming a set of interconnect structures (IS of 143/141/147, [0032-0033], see annotated Figure 1B
reproduced above) that pass through a buffer layer (BL of 139, [0032], see annotated Figure 1B reproduced above) comprising an inorganic material ([0032]) and the silicon substrate to make
electrical contact with the one or more electrically-conductive traces ([0035-0037]).
However, Chun docs not explicitly teach that the set of interconnect structures are tapered; and wherein forming the set of tapered interconnect structures uses a laser plug process; wherein forming, using the laser plug process, the set of tapered interconnect structures includes: forming through-holes from a bottom surface of the silicon substrate to the top surface of the silicon substrate using a laser, forming the buffer layer on the bottom surface of the silicon substrate, and plugging the through-holes using a plating process.
Ting teaches, in Fig 5, a set of interconnect structures (26/32/36 and their respective vias) that are tapered ([0018]) as a natural consequence of processing constraints ([0018]) and provide alternative connections for device dies to package substrates and/or printed circuit boards, effectively reducing the high costs associated with the formation of traditional interconnection structure, such as interposers ([0054]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine Chun's method with the formation of tapered interconnect structures of Ting to provide alternative connections for device dies to package substrates and/or printed circuit boards, effectively reducing the high costs associated with the formation of traditional interconnection structure, such as interposers.
Chun/Ting do not explicitly teach that forming the set of tapered interconnect structures uses a laser plug process; wherein forming, using the laser plug process, the set of tapered interconnect structures includes: forming through-holes from a bottom surface of the silicon substrate to the top surface of the silicon substrate using a laser, forming the buffer layer on the bottom surface of the silicon substrate, and plugging the through-holes using a plating process.
Hsia teaches, in Figs 2 and 4A-4E, that forming the set of tapered (of Ting) interconnect structures uses a laser plug process ([0023]-[0026]); wherein forming, using the laser plug process, the set of tapered interconnect structures includes: forming through-holes (31/101) from a bottom surface of the silicon substrate to the top surface of the silicon substrate using a laser (inverted orientation from Fig 4E, see Fig 4F, [0038]), forming the buffer layer (122) on the bottom surface of the silicon substrate, and plugging (114) the through-holes using a plating process ([0033]) "thereby allowing for improved etching rates and smooth sidewall formation" ([0023]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine Chun/Ting's method with the formation interconnect structures using a laser plug process of Hsia to allow for improved etching rates and smooth sidewall formation.
With regard to claim 16, Hsia teach, Figs 4B and 4D, wherein forming the through-holes
comprises: forming the through-holes by pulsing the laser ([0023-0026, 0032]) on the bottom surface of the silicon substrate (top surface of 110 shown in the figures, prior to the inversion at Fig 4F akin to SS of Chun, [0029]) prior to forming the buffer layer (122 akin to BL of Chun, [0035]).
With regard to claim 17, Chun teaches, Fig 1B annotated and reproduced above see claim 14, wherein forming the set of tapered interconnect structures comprises: a first width at a bottom surface of the buffer layer and a second width at the top surface of the silicon substrate, wherein the second width is lesser relative to the first width (see figure).
With regard to claim 18, Chun teaches, in Fig 1B, wherein the buffer layer comprises: forming the buffer layer by depositing a silicon nitride material ([0032]).
Hsia teaches, in Fig 4D, depositing a silicon nitride material (122, [0035]) on the bottom surface of the silicon substrate (110 with 120 and their top surface shown in the figures, prior to the inversion at Fig 4F akin to SS of Chun, [0029, 0030]).
With regard to claim 19, Chun teaches, in Fig 1B annotated and reproduced above, wherein the set of tapered interconnect structures corresponds to a first set of interconnect structures (rightmost occurrence of IS); and wherein the method further comprises: attaching a substrate (SUB, [0032], see annotated Figure 1B reproduced above) to a bottom surface of the buffer layer (bottom surface of BL) using a second set of interconnect structures (IS2 of 143/141, [0032], see annotated Figure 1B reproduced above).
With regard to claim 20, Chun teaches, in Fig 1B, wherein the set of tapered interconnect structures corresponds to a first set of interconnect structures (rightmost occurrence of IS); and wherein the method further comprises: attaching an integrated circuit die ("modules that may be installed in the sockets 103", [0035]) to a top surface of the passivation layer (top surface of topmost occurrence of 145) using a second set of interconnect structures (105, [0036-0037]).
With regard to claim 21, Chun teaches, in Fig 1B annotated and reproduced above see claim 14, forming one or more redistribution layers (RDLs of 145, [0033], sec annotated Figure 1B reproduced above) over a silicon layer (SS of 139, [0032], see annotated Figure 1B reproduced above); forming a passivation layer (topmost occurrence of 145, [0033]) over the one or more redistribution layers; forming through-holes ("openings", [0033]) through the silicon layer; forming a buffer layer (BL of 139, [0032], see annotated Figure 1B reproduced above) on a bottom surface of the silicon layer (bottom surface of SS); and forming interconnect structures (IS of 143/141/147, [0032-0033], see annotated Figure 1B reproduced above) in the through-holes.
However, Chun does not explicitly teach that the through-holes are formed from a backside of the silicon layer to an opposite side of the silicon layer using a combination of laser power and pulse timing/duration parameters; and that the interconnect structures are formed in the through holes by plugging the through holes using a plating process; and that the interconnect structures are tapered.
Ting teaches, in Fig 5, forming tapered interconnect structures (26/32/36 and their respective vias, [0018]) as a natural consequence of processing constraints ([0018]) and provide alternative connections for device dies to package substrates and/or printed circuit boards, effectively reducing the high costs associated with the formation of traditional interconnection structure, such as interposers ([0054]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine Chun's method with the formation of tapered interconnect structures of Ting to provide alternative connections for device dies to package substrates and/or printed circuit boards, effectively reducing the high costs associated with the formation of traditional interconnection structure, such as interposers.
However, Chun/Ting does not explicitly teach that the through-holes are formed from a backside of the silicon layer to an opposite side of the silicon layer using a combination of laser power and pulse timing/duration parameters; and that the interconnect structures are formed in the through holes by plugging the through holes using a plating process.
Hsia teaches, in Figs 2 and 4A-4F, that the through-holes (31/101, [0025, 0032]) are formed from a backside of the silicon layer (portion of 110 remaining at Fig 4E and its top surface akin to SS of Chun, [0029]) to an opposite side of the silicon layer (bottom surface in Fig 4E) using a combination of laser power and pulse timing/duration parameters ([0023]); and that the interconnect structures (114) are formed in the through holes by plugging the through holes using a plating process ([0033]) "thereby allowing for improved etching rates and smooth sidewall formation" ([0023]).
Therefore, it would have been obvious to the ordinary artisan at the time of filing to combine Chun/Ting's method with the formation of through-holes using a laser of Hsia to allow for improved etching rates and smooth sidewall formation.
With regard to claim 23, Chun/Hsia teaches, in Fig 4D of Hsia, wherein the forming the buffer layer comprises: depositing the buffer layer (122 of Hsia akin to BL of Chun, [0035] of Hsia) on the bottom surface of the silicon layer (110 with 120 and their topmost surface of Hsia akin to SS of Chun, [0029-0030] of Hsia); and removing one or more portions of the buffer layer ([0032] of Chun).
With regard to claim 24, Chun/Ting/Hsia teaches most of the limitations of this claim, as set forth above with regard to claim 21. However, Chun/Ting does not explicitly teach wherein the tapered interconnect structures comprise a length of less than 50 microns. Hsia teaches wherein the tapered interconnect structures comprise a length ("diameter", "depth", "aspect ratio", [0025]) which the skilled artisan would know too that the length would influence the formation of high-aspect-ratio vias ([0005]) and, in turn, impact the overall device size ([0002]).
The specific claimed length, absent any criticality, is only considered to be the "optimum" length disclosed by Hsia that a person having ordinary skill in the art would have been able to determine using routine experimentation (see In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)) based, among other things, on the desired aspect ratio, device size, manufacturing costs, etc. (see In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e. results which are different in kind and not in degree from the results of the prior art, will be obtained as long as the length is used, as already suggested by Hsia.
Since the applicant has not established the criticality (see next paragraph) of the length stated and since these lengths are in common use in similar devices in the art, it would have been obvious to one of ordinary skill in the art at the time of the invention to use these values in the device of Hsia.
Please note that the specification contains no disclosure of either the critical nature of the claimed lengths or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
With regard to claim 25, Hsia teaches, in Fig 4C, wherein forming the buffer layer (122 together with 114a, [0033, 0035]) on the bottom surface of the silicon layer comprises: forming the buffer layer on side surfaces of the through-holes (101, [0033], see Figure).
With regard to claim 26, Chun teaches, in Fig 1B annotated and reproduced above see claim 14, wherein forming the one or more redistribution layers comprises: forming electrically conductive traces (Ts, [0033], see annotated Figure 1B reproduced above) and another set of interconnect structures (IS2 of 143/141, [0032], see annotated Figure 1B reproduced above).
With regard to claim 27, Chun teaches, in Fig 1B annotated and reproduced above see claim 14, wherein a depth (D, see annotated Figure 1B reproduced above) of the through-holes corresponds to surfaces of the other set of interconnect structures (depth D of the through-holes aligns with and terminates at the surfaces of the interconnect structures).
With regard to claim 28, Chun/Hsia teaches, in Fig 1B of Chun and Fig 4D of Hsia, wherein forming the buffer layer comprises: depositing the buffer layer (122 of Hsia akin to BL of Chun, [0035] of Hsia) on the bottom surface of the silicon layer (110 with 120 and their top surface shown in the figures, prior to the inversion at Fig 4F of Hsia akin to SS of Chun, [0029-0030] of Hsia); and removing one or more portions of the buffer layer from the surfaces of the other set of interconnect structures ([0032] of Chun).
With regard to claim 35, Chun teaches, in Fig 1B annotated and reproduced above see claim 14, that the passivation layer includes one or more pad structures (PS of 149/147, [0033], see annotated Figure 1B reproduced above) within a dielectric material.
With regard to claim 36, Chun/Hsia teaches, in Fig 4C of Hsia, that forming the buffer layer (122 together with 114a, [0033, 0035]) on the bottom surface of the silicon layer comprises: depositing the buffer layer on inner surfaces of the through-holes (101, [0033], see Figure); and removing one or more portions of the buffer layer from the surfaces of the other set of interconnect structures ([0032] of Chun).
Allowable Subject Matter
Claim 37 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to anticipate or render obvious claimed limitations of wherein forming the through-holes comprises: ablating surfaces of the other set of interconnect structures, as set forth in claim 38, when taken in concert with all the other limitations of the claim, the base claim 21, and the intervening claim 26.
Response to Arguments
Applicant’s arguments, see remarks on pages 9 and 10, filed 7/7/2025, with respect to the rejections under 35 U.S.C. § 112 have been fully considered and are persuasive. The rejections under 35 U.S.C. § 112 of claims 14, 16-21, and 23-28 has been withdrawn.
Applicant's arguments concerning rejections under 35 U.S.C. § 103 in the remarks filed 7/7/2025 at pages 10-11 have been fully considered but they are not persuasive. The arguments are mere assertions that the various combinations of references fail to teach all the limitations of the claims in general terms and are thus fully addressed in the rejections set forth above or prior Office Actions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/RAJ R GUPTA/Primary Examiner, Art Unit 2893
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