DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
2. Applicant’s amendment to the claims, filed on March 17, 2026, is acknowledged. Entry of amendment is accepted and made of record.
Response to Arguments/Remarks
3. Applicant’s arguments/remarks, see pgs. 9-12, with respect to the immediate allowance of the current application have been fully considered but are not persuasive.
Pertaining to the Applicant's arguments/remarks, see pgs. 9-12:
The Examiner notes that upon detailed consideration that the amendments to at least the independent claims do not put the case into condition for allowance. Particularly, the claims as currently recited do not provide details pertaining to the “a surface of a package” with sufficient detail such as to overcome the cited prior arts of record. As seen in “Labeled Fig. 1” the package can be defined as the lower boxed elements having an uppermost surface which is in direct contact with the die-attach interface.
It was discussed with Applicant’s Representative Peter D. Siddoway, however, that the direct contact between element 30 and a top surface of the package substrate element 200 as seen in the Applicant’s Fig. 6 or a coplanar relationship between the bottom surface of element 30 and a top surface of the package substrate element 200 would overcome the cited prior arts of record.
Note by the Examiner
4. For clarity, the reference to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 &/or 103 rejections have been provided in parenthesis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-5, 10, 13-14, 16-19, 21 are rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang
[Radulescu et al. (US 2014/0264868 A1), hereinafter as R1 and Boyd et al. (US 2005/0151268 A1), hereinafter as B1 are utilized herein as evidence]
6. Regarding Claim 1, Hagleitner discloses a semiconductor die (see Figs. 1A-B, 2 and [0022] “semiconductor die”) comprising:
a silicon carbide (SiC) substrate (element 30, see [0024] “substrate 30 is preferably formed of SiC”) having a first surface (top surface) including a semiconductor layer (element 32, see [0024] “semiconductor body 32”) thereon and a second surface (bottom surface) that is opposite the first surface; and
a metal stack (element 18 and solder, see [0024] “back-side metallization 18”, see [0029] “the back-side metallization layer 18 is Gold (Au), and the solder used to solder the back-side metallization 18 to the mounting substrate is Gold-Tin (AuSn)”) having an upper surface that attaches to the second surface of the SiC substrate and a lower surface that is opposite the upper surface (see Fig. 2), the metal stack comprising a solder layer (see [0029]) and a noble metal layer (element 18) on the solder layer, wherein the noble metal layer comprises a final metal layer on the lower surface of the SiC substrate (see Fig. 2), the noble metal layer in electrical contact with a surface of a package (see [0027] “The exposed portion of the back-side metallization 18 is electrically and mechanically connected to a mounting substrate”).
Hagleitner does not explicitly disclose the solder is eutectic or a near eutectic; wherein the final metal layer is on the lower surface of the metal stack; wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack; the die-attach interface in direct contact with a surface of a package.
PNG
media_image1.png
1083
1046
media_image1.png
Greyscale
Huang discloses the solder is eutectic or a near eutectic (see Fig. 1 and “Labeled Fig. 1” above die attach of the die element 110 connecting to element “Metal stack”, see [0047] “This attach is usually achieved by attaching the die's metal stack 108 to the submount's metal stack 110” [0064] “the die attach is performed with use of solder alloys. These alloys may include eutectic or near-eutectic gold-tin alloys”); wherein the final metal layer is on the lower surface of the metal stack (lowermost metal layer of the metal stack); wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack (see “Labeled Fig. 1” above; the die-attach interface in direct contact with a surface of a package (see “Labeled Fig. 1” above, the package is defined as the lower box from a bottom of element 101 to a top of element 106; note, the manner in which the claim is currently recited and the plain and ordinary meaning as one of ordinary skill in the art would understand may be interpreted as presented in the “Labeled Fig. 1” without particular constraint on the boundaries without further details on boundaries or elements of the package).
The die attach eutectic solder and direct contact with a package as taught by Huang is incorporated as a eutectic solder between the die and the metal layers of the metal stack and direct contact with a package of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Huang with Hagleitner because the combination allows for a controlled area for the chip mounting interface, and provides strong reliable electrically and thermally conductive solder joint interface for mounting of the die (see Huang [0047, 0064]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a die and a metal stack for another to obtain predictable results (see Huang Fig. 1 and [0047, 0064]; also see evidentiary reference R1 Fig. 3 which shows a lowermost wafer-level die attach metallization element 20 below back side metallization element 30 and semiconductor element 24 configuration to be a known alternative, and see evidentiary reference B1 Fig. 5A showing a noble metal gold element 512 with a solder element 509 to be a known mounting structure).
7. Regarding Claim 2, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the eutectic or a near eutectic solder layer comprises a eutectic or a near eutectic material (see Huang [0064] “the die attach is performed with use of solder alloys. These alloys may include eutectic or near-eutectic gold-tin alloys”).
8. Regarding Claim 3, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the final metal layer comprises gold (Au) or silver (Ag) (see Huang [0064] “These alloys may include eutectic or near-eutectic gold-tin alloys”).
9. Regarding Claim 4, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the final metal layer (same gold final metal layer as the applicant’s invention which has an inherent material property configured to be compatible for attachment, and see Hagleitner [0029]) comprises a material that is compatible with any one of a eutectic solder material, a sintering material, and a glue material for attachment of the semiconductor die to a package (the limitations “for attachment” do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art; furthermore, the Examiner notes that the claims and specification do not define a degree of compatibility or specify a determination of compatibility).
10. Regarding Claim 5, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the eutectic or a near eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 80/20 (see Huang [0064] “gold-tin alloys such as an alloy containing about 80% gold by weight and 20% tin by weight”), (ii) copper (Cu) and Sn having a respective ratio by weight percent of about 6/94, (iii) silver (Ag) and Sn having a respective ratio by weight percent of about 10/90, and (iv) Au and germanium (Ge) having a respective ratio by weight percent of about 20/80.
11. Regarding Claim 13, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the final metal layer (same gold final metal layer as the applicant’s invention which has an inherent material property configured to diffuse into the eutectic solder, and see Hagleitner [0029]) is configured to (the configured to limitations and product-by-process limitations do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art) diffuse into the eutectic or a near eutectic solder layer during at least a partial phase transition of the eutectic or a near eutectic solder layer from a solid to a liquid state that happens during a die attach that allows the attachment of the semiconductor die to a surface of a package comprising at least one of gold (Au), silver (Ag), or copper (Cu).
12. Regarding Claim 14, Hagleitner and Huang disclose the semiconductor die of claim 13, wherein the eutectic or a near eutectic solder layer is configured to (the configured to limitations and product-by-process limitations do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art) go through the at least partial phase transition from solid to the liquid state at a temperature range of about 200° C to about 450° C.
13. Regarding Claim 16, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the final metal layer is configured to (the configured to limitations and product-by-process limitations do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art), stay intact during a die attach at a temperature below a eutectic melting point of the eutectic or a near eutectic solder layer that allows attachment of the semiconductor die with at least one of a silver (Ag), gold (Au), and copper (Cu) sintering material or a glue material to a surface of a package comprising at least one of gold (Au), silver (Ag), and copper (Cu).
14. Regarding Claim 17, Hagleitner and Huang disclose the semiconductor die of claim 16, wherein the eutectic or a near eutectic solder layer is configured to (the configured to limitations and product-by-process limitations do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art) not go through the at least partial phase transition to a liquid state at a temperature range of about 100° C to lower than the eutectic melting point of the eutectic or a near eutectic solder layer.
15. Regarding Claim 18, Hagleitner and Huang disclose the semiconductor die of claim 17, wherein the final metal layer is configured to (the configured to limitations and product-by-process limitations do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art) allow attachment of the semiconductor die with at least one of a Ag, a Au, and a Cu sintering material or at least one of a conductive or a non-conductive glue material at a temperature of about 200° C.
16. Regarding Claim 19, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the semiconductor layer comprises a group III nitride layer (see Hagleitner [0024] “semiconductor body 32 may be formed of one or more layers of GaN and/or AlGaN”).
17. Regarding Claim 21, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the semiconductor die comprises a high electron mobility transistor (HEMT) die (see Hagleitner [0022] “High Electron Mobility Transistor (HEMT)”) and wherein the semiconductor layer comprises a gallium nitride (GaN) layer (see Hagleitner [0024] “semiconductor body 32 may be formed of one or more layers of GaN and/or AlGaN”).
18. Regarding Claim 23, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the semiconductor die further comprises at least one via (see Hagleitner element 20, see [0023] “via 20”) extending through the SiC substrate from the second surface thereof toward the first surface thereof, wherein the metal stack conformally extends along the second surface of the SiC substrate and within the via along sidewall surfaces thereof such that the via is unfilled (see Hagleitner Fig. 2).
19. Claims 6-8, 15 are rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Horigane et al. (JP 2006110626 A, see attached document), hereinafter as Horigane
20. Regarding Claim 6, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 75/25, (ii) copper (Cu) and Sn having a respective ratio by weight percent of about 4/96, (iii) silver (Ag) and Sn having a respective ratio by weight percent of about 8/92, and (iv) Au and germanium (Ge) having a respective ratio by weight percent of about 17/83.
Horigane discloses wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 75/25 (see page 4 “Au composition ratio in the range of 65 to 80 weight percent and the Sn composition ratio in the range of 20 to 35 weight percent”).
The weight percentage ratio as taught by Horigane is incorporated as the weight percentage ratio of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Horigane with Hagleitner because the combination provides prevention of oxidation and stable melting characteristics at the time of use (see Horigane page. 4), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold tin solder composition ratio for another to obtain predictable results (see Horigane pg. 4).
21. Regarding Claim 7, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 70/30, (ii) copper (Cu) and Sn having a respective ratio by weight percent of about 2/98, (iii) silver (Ag) and Sn having a respective ratio by weight percent of about 5/95, and (iv) Au and germanium (Ge) having a respective ratio by weight percent of about 14/86.
Horigane discloses wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 70/30 (see page 4 “Au composition ratio in the range of 65 to 80 weight percent and the Sn composition ratio in the range of 20 to 35 weight percent”).
The weight percentage ratio as taught by Horigane is incorporated as the weight percentage ratio of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Horigane with Hagleitner because the combination provides prevention of oxidation and stable melting characteristics at the time of use (see Horigane page. 4), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold tin solder composition ratio for another to obtain predictable results (see Horigane pg. 4).
22. Regarding Claim 8, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 65/35, (ii) copper (Cu) and Sn having a respective ratio by weight percent of about 0/100, (iii) silver (Ag) and Sn having a respective ratio by weight percent of about 0/100, and (iv) Au and germanium (Ge) having a respective ratio by weight percent of about 10/90.
Horigane discloses wherein the eutectic solder layer comprises at least one of (i) gold (Au) and tin (Sn) having a respective ratio by weight percent of about 65/35 (see page 4 “Au composition ratio in the range of 65 to 80 weight percent and the Sn composition ratio in the range of 20 to 35 weight percent”).
The weight percentage ratio as taught by Horigane is incorporated as the weight percentage ratio of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Horigane with Hagleitner because the combination provides prevention of oxidation and stable melting characteristics at the time of use (see Horigane page. 4), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold tin solder composition ratio for another to obtain predictable results (see Horigane pg. 4).
23. Regarding Claim 15, Hagleitner and Huang disclose the semiconductor die of claim 13.
Hagleitner and Huang do not explicitly disclose wherein the eutectic solder layer comprises a combination of gold (Au) and tin (Sn) in a ratio by weight percent of Au/Sn in a range of about 65/35 to about 80/20, and wherein the eutectic solder layer is configured to have the phase transition to the liquid state at a temperature of about 278° C.
Horigane discloses wherein the eutectic solder layer comprises a combination of gold (Au) and tin (Sn) in a ratio by weight percent of Au/Sn in a range of about 65/35 to about 80/20 (see page 4 “Au composition ratio in the range of 65 to 80 weight percent and the Sn composition ratio in the range of 20 to 35 weight percent”; See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The weight percentage ratio as taught by Horigane is incorporated as the weight percentage ratio of Hagleitner, wherein the combination further discloses wherein the eutectic solder layer is configured to have the phase transition to the liquid state at a temperature of about 278° C (the combination of prior art disclose the same eutectic solder layer material which has the same inherent material properties configured to have the function limitation characteristics as claimed).
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Horigane with Hagleitner because the combination provides prevention of oxidation and stable melting characteristics at the time of use (see Horigane page. 4), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold tin solder composition ratio for another to obtain predictable results (see Horigane pg. 4).
24. Claims 9 and 11 are rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Thompson et al. (US 2006/0270194 A1), hereinafter as Thompson
25. Regarding Claim 9, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the final metal layer has a thickness of about 500 nm.
Thompson discloses wherein the final metal layer has a thickness of about 500 nm (see Fig. 2 and [0013] “layer 130 of barrier metal is comprised of titanium, nickel-vanadium, and gold … gold material having a thickness of approximately 0.5 microns”).
The thickness of the final metal layer as taught by Thompson is incorporated as a thickness of the final metal layer of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate of Thompson with Hagleitner because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold final metal layer backside metallization thickness through a substrate to connect between an upper and lower component for another to obtain predictable results (see Thompson [0013]).
26. Regarding Claim 11, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the final metal layer has a thickness in a range between about 500 nm and about 1000 nm.
Thompson discloses wherein the final metal layer has a thickness in a range between about 500 nm and about 1000 nm (see Fig. 2 and [0013] “layer 130 of barrier metal is comprised of titanium, nickel-vanadium, and gold … gold material having a thickness of approximately 0.5 microns”).
The thickness of the final metal layer as taught by Thompson is incorporated as a thickness of the final metal layer of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate of Thompson with Hagleitner because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold final metal layer backside metallization thickness through a substrate to connect between an upper and lower component for another to obtain predictable results (see Thompson [0013]).
27. Claim 10 is rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Kosaka et al. (US 2019/0259662 A1), hereinafter as Kosaka.
28. Regarding Claim 10, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang as previously combined do not disclose wherein the final metal layer has a thickness in a range between about 50 and less than about 500 nm.
Kosaka discloses wherein the final metal layer has a thickness in a range between about 50 and less than about 500 nm (see Fig. 1, 4A-F element 24, see [0024] “the Au layers, 24 and 20” and [0016] “third metal layer 24 has a thickness of 20 to 200 nm”;
See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)")
The final metal layer thickness of Kosaka is incorporated as the final metal layer thickness of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Kosaka with Hagleitner because the combination provides mechanical and electrical connection of an n-shaped electrical connection through a substrate to connect an upper and lower component (see Kosaka Figs. 1A-B and [0015-0017]), and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known gold metal layer thickness for another in a similar device to obtain predictable results (see Kosaka Figs. 1A-B and [0016]).
29. Claim 12 is rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of EID et al. (US 2020/0235716 A1), hereinafter as EID
30. Regarding Claim 12, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the eutectic solder layer has a thickness of about 3600 nm.
EID discloses wherein the eutectic solder layer has a thickness of about 3600 nm (see Fig. 1 element 108 and [0036] “Seal frame 108 … eutectic solder, (e.g., gold tin) … a thickness between 0.5-10 microns”).
The thickness of the eutectic solder layer as taught by EID is incorporated as the eutectic solder layer of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of EID with Hagleitner because the combination provides mechanical and electrical connection between the upper mounted component and the lower substrate (see EID Fig. 1 and [0036]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known eutectic solder for bonding an upper component to a lower substrate to obtain predictable results (see Hagleitner [0029] “the back-side metallization layer 18 is Gold (Au), and the solder used to solder the back-side metallization 18 to the mounting substrate is Gold-Tin (AuSn)” and EID [0036]).
31. Claim 24 is rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Ketterson (US 2020/0176393 A1)
[Trang et al. (US 2020/0027850 A1), hereinafter as Trang is utilized herein as evidence.]
32. Regarding Claim 24, Hagleitner and Huang disclose the semiconductor die of claim 1.
Hagleitner and Huang do not explicitly disclose wherein the semiconductor die comprises an RF transistor formed as part of a monolithic microwave integrated circuit (MMIC), and wherein the MMIC comprises vias connected to a circuit element of the RF transistor.
Ketterson discloses wherein the semiconductor die comprises an RF transistor formed as part of a monolithic microwave integrated circuit (MMIC), and wherein the MMIC comprises vias connected to a circuit element of the RF transistor (see Fig. 2 and [0030] “RF circuits”, [0032] “MMIC circuit package 10”, [0034] “active side 36 (e.g., transistor sources or emittors … RF inputs or outputs”, and [0033] “vias 52”).
The type of semiconductor device as taught by Ketterson is incorporated as a type of device of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Ketterson because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of semiconductor device of the die for another to obtain predicable results (also see evidentiary reference Trang [0152] disclosing HEMT transistors not limited to such devices and can be applied for RF transistor technologies and with MMIC, and see Hagleitner [0022] for HEMT transistors)
33. Parallel rejection of claims 1, 20, and 22 rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang.
34. Regarding Claim 1, Hagleitner discloses a semiconductor die (see Figs. 1A-B, 2 and [0022] “semiconductor die”) comprising:
a silicon carbide (SiC) substrate (lower portion of element 30 excluding an upper portion, see [0024] “substrate 30 is preferably formed of SiC”) having a first surface (top surface) including a semiconductor layer (upper portion of element 30 excluding the lower portion of element 30) thereon and a second surface (bottom surface) that is opposite the first surface; and
a metal stack (element 18 and solder, see [0024] “back-side metallization 18”, see [0029] “the back-side metallization layer 18 is Gold (Au), and the solder used to solder the back-side metallization 18 to the mounting substrate is Gold-Tin (AuSn)”) having an upper surface that attaches to the second surface of the SiC substrate and a lower surface that is opposite the upper surface (see Fig. 2), the metal stack comprising a solder layer (see [0029]) and a noble metal layer (element 18) on the solder layer, wherein the noble metal layer comprises a final metal layer on the lower surface (see Fig. 2); the noble metal layer in electrical contact with a surface of a package (see [0027] “The exposed portion of the back-side metallization 18 is electrically and mechanically connected to a mounting substrate”).
Hagleitner does not explicitly disclose the solder is eutectic; wherein the final metal layer is on the lower surface of the metal stack; the die-attach interface in direct contact with a surface of a package.
Hagleitner does not explicitly disclose the solder is eutectic or a near eutectic; wherein the final metal layer is on the lower surface of the metal stack; wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack; the die-attach interface in direct contact with a surface of a package.
Huang discloses the solder is eutectic or a near eutectic (see Fig. 1 and “Labeled Fig. 1” above die attach of the die element 110 connecting to element “Metal stack”, see [0047] “This attach is usually achieved by attaching the die's metal stack 108 to the submount's metal stack 110” [0064] “the die attach is performed with use of solder alloys. These alloys may include eutectic or near-eutectic gold-tin alloys”); wherein the final metal layer is on the lower surface of the metal stack (lowermost metal layer of the metal stack); wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack (see “Labeled Fig. 1” above; the die-attach interface in direct contact with a surface of a package (see “Labeled Fig. 1” above, the package is defined as the lower box from a bottom of element 101 to a top of element 106; note, the manner in which the claim is currently recited and the plain and ordinary meaning as one of ordinary skill in the art would understand may be interpreted as presented in the “Labeled Fig. 1” without particular constraint on the boundaries without further details on boundaries or elements of the package).
The die attach eutectic solder and direct contact with a package as taught by Huang is incorporated as a eutectic solder between the die and the metal layers of the metal stack and direct contact with a package of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Huang with Hagleitner because the combination allows for a controlled area for the chip mounting interface, and provides strong reliable electrically and thermally conductive solder joint interface for mounting of the die (see Huang [0047, 0064]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a die and a metal stack for another to obtain predictable results (see Huang Fig. 1 and [0047, 0064]).
35. Regarding Claim 20, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the semiconductor layer comprises a SiC layer (see Hagleitner the upper portion of element 30 is SiC).
36. Regarding Claim 22, Hagleitner and Huang disclose the semiconductor die of claim 1, wherein the semiconductor die comprises a metal-oxide-semiconductor field effect transistor (MOSFET) die (see Hagleitner [0022] “Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)”) and wherein the semiconductor layer comprises a SiC layer (the upper portion of element 30 is SiC).
37. Claims 25-26, 28-31, 33, and 35 are rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Radulescu et al. (US 2014/0264868 A1), hereinafter as Radulescu, in view of Mieczkowski et al. (US 2013/0256841 A1), hereinafter as Mieczkowski
[Radulescu et al. (US 2014/0264868 A1), hereinafter as R1 and Boyd et al. (US 2005/0151268 A1), hereinafter as B1 are utilized herein as evidence]
38. Regarding Claim 25, Hagleitner discloses a semiconductor die (see Figs. 1A-B, 2 and [0022] “semiconductor die”) comprising:
a silicon carbide (SiC) substrate (element 30, see [0024] “substrate 30 is preferably formed of SiC”) having a first surface (top surface) including a semiconductor layer (element 32, see [0024] “semiconductor body 32”) thereon and a second surface (bottom surface) that is opposite the first surface; and
a metal stack (element 18 and solder, see [0024] “back-side metallization 18”, see [0029] “the back-side metallization layer 18 is Gold (Au), and the solder used to solder the back-side metallization 18 to the mounting substrate is Gold-Tin (AuSn)”) having an upper surface that attaches to the second surface of the SiC substrate and a lower surface that is opposite the upper surface (see Fig. 2), the metal stack comprising a final metal layer comprising gold (Au) (element 18) on the lower surface of the SiC substrate, a solder layer (see [0029]) on the final metal layer, the noble metal layer in electrical contact with a surface of a package (see [0027] “The exposed portion of the back-side metallization 18 is electrically and mechanically connected to a mounting substrate”).
Hagleitner does not explicitly disclose the solder is eutectic; the final metal layer is on the lower surface of the metal stack; a barrier layer on the eutectic solder layer, and a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer; wherein the final metal layer forms a die-attach interface on the lower surface of the metal stack; the die-attach interface in direct contact with a surface of a package.
PNG
media_image1.png
1083
1046
media_image1.png
Greyscale
Huang discloses the solder is eutectic (see Fig. 1 die attach of the die element 110 connecting to element “Metal stack”, see [0047] “This attach is usually achieved by attaching the die's metal stack 108 to the submount's metal stack 110” [0064] “the die attach is performed with use of solder alloys. These alloys may include eutectic or near-eutectic gold-tin alloys”); wherein the final metal layer is wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack (see “Labeled Fig. 1” above) the die-attach interface in direct contact with a surface of a package (see “Labeled Fig. 1” above, the package is defined as the lower box from a bottom of element 101 to a top of element 106; note, the manner in which the claim is currently recited and the plain and ordinary meaning as one of ordinary skill in the art would understand may be interpreted as presented in the “Labeled Fig. 1” without particular constraint on the boundaries without further details on boundaries or elements of the package).
The die attach eutectic solder and direct contact with a package as taught by Huang is incorporated as a eutectic solder between the die and the metal layers of the metal stack and direct contact with a package of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Huang with Hagleitner because the combination allows for a controlled area for the chip mounting interface, and provides strong reliable electrically and thermally conductive solder joint interface for mounting of the die (see Huang [0047, 0064]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a die and a metal stack for another to obtain predictable results (see Huang Fig. 1 and [0047, 0064]; also see evidentiary reference R1 Fig. 3 which shows a lowermost wafer-level die attach metallization element 20 below back side metallization element 30 and semiconductor element 24 configuration to be a known alternative, and see evidentiary reference B1 Fig. 5A showing a noble metal gold element 512 with a solder element 509 to be a known mounting structure).
Hagleitner and Huang do not explicitly disclose a barrier layer on the eutectic solder layer, and a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer.
Radulescu discloses a barrier layer on the eutectic solder layer (see Fig. 3 elements 36, 40 and see [0038]).
The barrier layer as taught by Radulescu is incorporated as a barrier layer of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Radulescu with Hagleitner because the combination provides prevention of diffusion of metal (see Radulescu [0038]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a back-side metallization with a tin gold solder for another in a similar device to obtain predictable results.
Hagleitner and Huang and Radulescu do not explicitly disclose a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer.
Mieczkowski discloses a metal interlayer comprising nickel contacting the solder layer (see Fig. 8 element 28 and see [0037] “barrier layer 28 may include … nickel chromium (NiCr)”).
The metal interlayer comprising nickel as taught by Mieczkowski is incorporated with Hagleitner, wherein the combination discloses a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer (see Mieczkowski [0038] “solder 22 is used to electrically and mechanically couple the external barrier layer 28, which is directly or indirectly coupled to the back side metallization structure 18 of the module 20. As those skilled in the art will appreciate, various intermediate layers may be provided as desired between any of the illustrated layers”)
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Mieczkowski with Hagleitner because the combination prevents cracking and prevents diffusion (see Mieczkowski [0036]).
39. Regarding Claim 26, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the final metal layer (same gold final metal layer as the applicant’s invention which has an inherent material property configured to be compatible for attachment, and see Hagleitner [0029]) comprises a material that is compatible with any one of a eutectic solder material, a sintering material, and a glue material during attachment of the die to a package (the limitations “during attachment” do not require additional structural features to distinguish from the gold final metal layer and eutectic solder taught by the prior art; furthermore, the Examiner notes that the claims and specification do not define a degree of compatibility or specify a determination of compatibility).
40. Regarding Claim 28, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 24, wherein the sintering material comprises at least one of silver (Ag), gold (Au), and copper (Cu) (the final metal layer is the same gold material as the applicant’s invention which has an inherent material property configured to be compatible with the claimed sintering material).
41. Regarding Claim 29, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the metal interlayer and the final metal layer are configured to (the same nickel containing and gold metal interlayer and final metal layer has an inherent material property configured to diffuse perform the claimed functions as claimed) diffuse into the eutectic solder layer during at least a partial phase transition of the eutectic solder layer from a solid to a liquid state that happens during die attach that allows the attachment of the semiconductor die to a surface of a package comprising at least one of Au, silver (Ag), or copper (Cu).
42. Regarding Claim 30, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the metal interlayer and the final metal layer are configured to (the same nickel containing and gold metal interlayer and final metal layer has an inherent material property configured to diffuse perform the claimed functions as claimed) stay intact, during die attach at a temperature below a eutectic melting point of the eutectic solder layer that allows attachment of the semiconductor die with a silver (Ag) sintering material or a glue material to a surface of a package comprising at least one of Au, silver (Ag), and copper (Cu).
43. Regarding Claim 31, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the semiconductor layer comprises a group III nitride layer (see Hagleitner [0024] “semiconductor body 32 may be formed of one or more layers of GaN and/or AlGaN”).
44. Regarding Claim 33, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the semiconductor die comprises a high electron mobility transistor (HEMT) die (see Hagleitner [0022] “High Electron Mobility Transistor (HEMT)”) and wherein the semiconductor layer comprises a gallium nitride (GaN) layer (see Hagleitner [0024] “semiconductor body 32 may be formed of one or more layers of GaN and/or AlGaN”)
45. Regarding Claim 35, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the semiconductor die further comprises at least one via (see Hagleitner element 20, see [0023] “via 20”) extending through the SiC substrate from the second surface thereof toward the first surface thereof, wherein the metal stack conformally extends along the second surface of the SiC substrate and within the via along sidewall surfaces thereof such that the via is unfilled (see Hagleitner Fig. 2).
46. Regarding Claim 27, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the eutectic solder layer comprises gold (Au) and tin (Sn) having a ratio by weight percent of Au/Sn in a range between about 65/35 and about 80/20 (see Huang [0064] “gold-tin alloys such as an alloy containing about 80% gold by weight and 20% tin by weight”).
47. Parallel rejection of claims 25, 32, and 34 rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Radulescu et al. (US 2014/0264868 A1), hereinafter as Radulescu, in view of Mieczkowski et al. (US 2013/0256841 A1), hereinafter as Mieczkowski
[Radulescu et al. (US 2014/0264868 A1), hereinafter as R1 and Boyd et al. (US 2005/0151268 A1), hereinafter as B1 are utilized herein as evidence]
48. Regarding Claim 25, Hagleitner discloses a semiconductor die (see Figs. 1A-B, 2 and [0022] “semiconductor die”) comprising:
a silicon carbide (SiC) substrate (lower portion of element 30 excluding an upper portion, see [0024] “substrate 30 is preferably formed of SiC”) having a first surface (top surface) including a semiconductor layer (upper portion of element 30 excluding the lower portion of element 30) thereon and a second surface (bottom surface) that is opposite the first surface; and
a metal stack (element 18 and solder, see [0024] “back-side metallization 18”, see [0029] “the back-side metallization layer 18 is Gold (Au), and the solder used to solder the back-side metallization 18 to the mounting substrate is Gold-Tin (AuSn)”) having an upper surface that attaches to the second surface of the SiC substrate and a lower surface that is opposite the upper surface (see Fig. 2), the metal stack comprising a final metal layer comprising gold (Au) (element 18) on the lower surface of the SiC substrate, a solder layer (see [0029]) on the final metal layer; the noble metal layer in electrical contact with a surface of a package (see [0027] “The exposed portion of the back-side metallization 18 is electrically and mechanically connected to a mounting substrate”).
Hagleitner does not explicitly disclose the solder is eutectic; the final metal layer is on the lower surface of the metal stack; a barrier layer on the eutectic solder layer, and a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer; the die-attach interface in direct contact with a surface of a package.
PNG
media_image1.png
1083
1046
media_image1.png
Greyscale
Huang discloses the solder is eutectic or a near eutectic (see Fig. 1 and “Labeled Fig. 1” above die attach of the die element 110 connecting to element “Metal stack”, see [0047] “This attach is usually achieved by attaching the die's metal stack 108 to the submount's metal stack 110” [0064] “the die attach is performed with use of solder alloys. These alloys may include eutectic or near-eutectic gold-tin alloys”); wherein the final metal layer is on the lower surface of the metal stack (lowermost metal layer of the metal stack); wherein the noble metal layer forms a die-attach interface on the lower surface of the metal stack (see “Labeled Fig. 1” above; the die-attach interface in direct contact with a surface of a package (see “Labeled Fig. 1” above, the package is defined as the lower box from a bottom of element 101 to a top of element 106; note, the manner in which the claim is currently recited and the plain and ordinary meaning as one of ordinary skill in the art would understand may be interpreted as presented in the “Labeled Fig. 1” without particular constraint on the boundaries without further details on boundaries or elements of the package).
The die attach eutectic solder and direct contact with a package as taught by Huang is incorporated as a eutectic solder between the die and the metal layers of the metal stack and direct contact with a package of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Huang with Hagleitner because the combination allows for a controlled area for the chip mounting interface, and provides strong reliable electrically and thermally conductive solder joint interface for mounting of the die (see Huang [0047, 0064]); furthermore, the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a die and a metal stack for another to obtain predictable results (see Huang Fig. 1 and [0047, 0064]; also see evidentiary reference R1 Fig. 3 which shows a lowermost wafer-level die attach metallization element 20 below back side metallization element 30 and semiconductor element 24 configuration to be a known alternative, and see evidentiary reference B1 Fig. 5A showing a noble metal gold element 512 with a solder element 509 to be a known mounting structure).
Hagleitner and Huang do not explicitly disclose a barrier layer on the eutectic solder layer, and a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer.
Radulescu discloses a barrier layer on the eutectic solder layer (see Fig. 3 elements 36, 40 and see [0038]).
The barrier layer as taught by Radulescu is incorporated as a barrier layer of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Radulescu with Hagleitner because the combination provides prevention of diffusion of metal (see Radulescu [0038]); and the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known interface between a back-side metallization with a tin gold solder for another in a similar device to obtain predictable results.
Hagleitner and Huang and Radulescu do not explicitly disclose a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer.
Mieczkowski discloses a metal interlayer comprising nickel contacting the solder layer (see Fig. 8 element 28 and see [0037] “barrier layer 28 may include … nickel chromium (NiCr)”).
The metal interlayer comprising nickel as taught by Mieczkowski is incorporated with Hagleitner, wherein the combination discloses a metal interlayer comprising nickel between the eutectic solder layer and the barrier layer (see Mieczkowski [0038] “solder 22 is used to electrically and mechanically couple the external barrier layer 28, which is directly or indirectly coupled to the back side metallization structure 18 of the module 20. As those skilled in the art will appreciate, various intermediate layers may be provided as desired between any of the illustrated layers”)
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Mieczkowski with Hagleitner because the combination prevents cracking and prevents diffusion (see Mieczkowski [0036]).
49. Regarding Claim 32, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the semiconductor layer comprises a SiC layer (upper portion of element 30 is SiC).
50. Regarding Claim 34, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25, wherein the semiconductor die comprises a metal-oxide-semiconductor field effect transistor (MOSFET) die (see Hagleitner [0022] “Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET)”) and wherein the semiconductor layer comprises a SiC layer (the upper portion of element 30 is SiC).
51. Claim 36 are rejected under 35 U.S.C. 103 as obvious over Hagleitner et al. (US 2014/0175664 A1), hereinafter as Hagleitner, in view of Huang et al. (US 2020/0313049 A1), hereinafter as Huang, in view of Radulescu et al. (US 2014/0264868 A1), hereinafter as Radulescu, in view of Mieczkowski et al. (US 2013/0256841 A1), hereinafter as Mieczkowski, in view of Ketterson (US 2020/0176393 A1)
[Trang et al. (US 2020/0027850 A1), hereinafter as Trang is utilized herein as evidence.]
52. Regarding Claim 36, Hagleitner, Huang, Radulescu, and Mieczkowski disclose the semiconductor die of claim 25.
Hagleitner, Huang, Radulescu, and Mieczkowski do not explicitly disclose wherein the semiconductor die comprises an RF transistor formed as part of a monolithic microwave integrated circuit (MMIC), and wherein the MMIC comprises vias connected to a circuit element of the RF transistor.
Ketterson discloses wherein the semiconductor die comprises an RF transistor formed as part of a monolithic microwave integrated circuit (MMIC), and wherein the MMIC comprises vias connected to a circuit element of the RF transistor (see Fig. 2 and [0030] “RF circuits”, [0032] “MMIC circuit package 10”, [0034] “active side 36 (e.g., transistor sources or emittors … RF inputs or outputs”, and [0033] “vias 52”).
The type of semiconductor device as taught by Ketterson is incorporated as a type of device of Hagleitner.
It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to incorporate the teachings of Ketterson because the combination is simple substitution of one known element for another to obtain predictable results – simple substitution of one known type of semiconductor device of the die for another to obtain predicable results (also see evidentiary reference Trang [0152] disclosing HEMT transistors not limited to such devices and can be applied for RF transistor technologies and with MMIC, and see Hagleitner [0022] for HEMT transistors)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMUEL PARK whose telephone number is (303)297-4277. The examiner can normally be reached on Normal Schedule: M-F Sometime between 6:30 a.m. - 7:00 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H. Loke can be reached on (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SAMUEL PARK/Examiner, Art Unit 2818
Prosecution Insights