DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 4 2026 has been entered.
Claim Objections
Claims 1, 13, 8, and 33 are objected to because of the following informalities:
Claims 1 and 13 read “a first upper horizontally-extending portion adjoined to a top end the first vertically-extending portion” and should read as “a first upper horizontally-extending portion adjoined to a top end of the first vertically-extending portion”.
Claim 8 reads “the plan view” and should read as “a plan view”, “a plan view” is first recited in claim 7, but claim 8 depends on claim 1.
Claim 33 reads “first lateral extent” which has no antecedent basis. The Examiner will interpret the first lateral extend as the first gate length.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 21, 27-28, and 33 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lai et al. (“Lai” US 2020/0083380).
Regarding claim 21, Lai discloses:
A semiconductor device comprising a field effect transistor (Figure 10), wherein the field effect transistor comprises:
a source region and a drain region (242, 244) located within an insulating matrix layer (130 and region of 252 labeled in annotated Figure 10), wherein a top surface of the source region and a top surface of a drain region are located within a first horizontal plane including a top surface of the insulating matrix layer (demonstrated in annotated Figure 10), and a bottom surface of the source region (242) is in contact with the insulating matrix layer (shown in Figure 10) and a bottom surface of the drain region (244) is in contact with the insulating matrix layer (shown in Figure 10);
a U-shaped channel plate (262) comprising a first vertically-extending portion contacting a sidewall of the source region (242), a second vertically-extending portion contacting a sidewall of the drain region (244, Figure 10), a lower horizontally-extending portion connecting bottom ends of the first vertically- extending portion and the second vertically-extending portion (shown in annotated Figure 10) and having a bottom surface located at, or below, a second horizontal plane including bottom surfaces of the source region and the drain region (242, 244, at the second horizontal plane), a first upper horizontally-extending portion comprising a first upper semiconductor sidewall having a bottom edge located at, and in contact with, a planar top surface of the source region (242, shown in Figure 10, contact is made through intervening layer 252), and a second upper horizontally-extending portion comprising a second upper semiconductor sidewall having a bottom edge located at a planar top surface of the drain region (244, shown in Figure 10), wherein a region of the first upper horizontally-extending portion (left upper horizontally-extending portion of the channel plate 262) that contacts the planar top surface of the source region (242) within the first horizontal plane (the segment of the source region 242 contacting the first upper horizontally extending portion is located within the first horizontal plane) has a same material composition as a region of the lower horizontally-extending portion (portion of the channel plate 262 directly contacting the top surface of 130, since the channel 262 is shown as comprising a stacked material structure of oxide layers, see para. [0029], it is clear that the same material in a region of the channel plate contacting the source region 242 is the same material as a region of the channel plate contacting the insulating matrix layer portion 130) that contacts a recessed surface of the insulating matrix layer (130 and lateral portions of 252 make a recessed structure, the bottom surface of the recess being the upper surface of 130 between the lateral portions of 252) within the second horizontal plane (see Figure 10 and annotated Figure 10 below), wherein an entirety of a bottom surface of the lower horizontally-extending portion of the U-shaped channel plate is in contact with the insulating matrix layer (shown in annotated Figure 10); and
a U-shaped gate dielectric (264a) directly contacting inner sidewalls of the first vertically- extending portion and the second vertically-extending portion (shown in Figure 10) and directly contacting a top surface of the lower horizontally- extending portion (shown in Figure 10) and comprising a first upper-horizontally extending gate dielectric portion (264a, upper left portion) overlying the first upper horizontally-extending portion of the U-shaped channel plate (shown in Figure 10) and having a first dielectric sidewall that is vertically coincident with the first upper semiconductor sidewall (shown in annotated Figure 10), and further comprising a second upper horizontally- extending gate dielectric portion (264a, upper right portion) overlying the second upper horizontally-extending portion of the U-shaped channel plate (shown in Figure 10) and having a second dielectric sidewall (labeled in annotated Figure 10) that is vertically coincident with the second upper semiconductor sidewall (shown in annotated Figure 10).
Regarding claim 27, Lai discloses:
The semiconductor device of Claim 21, wherein the first dielectric sidewall and the second dielectric sidewall (sidewalls of U-shaped gate dielectric’s upper-horizontally extending portions) are perpendicular to a lateral separation direction (horizontal direction shown in Figure 10) between the source region and the drain region (242, 244), and are laterally offset from all sidewalls (lateral, vertically-extending sidewalls) of the source region and the drain region (242, 244) that are perpendicular to the lateral separation direction (shown in Figure 10).
Regarding claim 28, Lai discloses:
The semiconductor device of Claim 27, wherein the gate electrode has a lateral extent (264b, 264c) along the lateral separation direction (horizontal direction in Figure 10) that is less than a lateral distance between the first dielectric sidewall and the second dielectric sidewall (sidewalls of U-shaped gate dielectric’s upper-horizontally extending portions) along the lateral separation direction (horizontal direction, shown in Figure 10).
Regarding claim 33, Lai discloses:
The semiconductor device of Claim 21, further comprising a gate electrode (264c) overlying the U-shaped gate dielectric (264a), wherein the gate electrode (264c) comprises:
a lower gate electrode portion (rectangular portion between sidewalls of the U-shaped gate dielectric 264a) laterally extending between vertically-extending portions of the U-shaped gate dielectric (264a) that are laterally spaced from each other along a first horizontal direction (horizontal direction in Figure 10) and having a first gate length along the first horizontal direction (here, the gate length is effectively the distance between the inner surfaces of the vertically-extending portions of the U-shaped gate dielectric 264a, see Figure 10);
an upper gate electrode portion (portion of the gate electrode 264c that extends horizontally over the U-shaped gate dielectric 264a and the channel plate 262) extending over the first upper-horizontally extending gate dielectric portion and the second upper horizontally-extending portion (upper horizontally extending portions of the gate dielectric 264a, see Figure 10) and having a lateral extent along the first horizontal direction (horizontal direction in Figure 10) that is greater than the first lateral extent (first gate length, see Figure 10) and is less than a lateral spacing along the first horizontal direction (horizontal direction in Figure 10) between the first dielectric sidewall of the first upper-horizontally extending gate dielectric portion and the second dielectric sidewall of the second upper horizontally-extending gate dielectric portion (see Figure 10, which shows the upper portion of the gate electrode has a length in the horizontal direction less than the spacing between the outer, lateral sidewalls of the upper horizontally extending portions of the U-shaped gate dielectric).
Claim Rejections - 35 USC § 103
Claims 1-2, 4, 11, 26, and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (“Lai” US 2020/0083380) and Kim et al. (“Kim” US 2022/0246738)
Regarding claim 1, Lai discloses:
A semiconductor device comprising a field effect transistor (Figure 10), wherein the field effect transistor comprises:
a source region and a drain region (242, 244) located within an insulating matrix layer (130 and lateral, vertically-extending regions of 252, labeled in annotated Figure 10), wherein a top surface of the source region and a top surface of a drain region (242, 244) are located within a first horizontal plane including a top surface of the insulating matrix layer (demonstrated in annotated Figure 10, the first horizontal plane is the plane with top surfaces of the source/drain regions 242, 244), and a bottom surface of the source region (242) is in contact with the insulating matrix layer (shown in Figure 10) and a bottom surface of the drain region (244) is in contact with the insulating matrix layer (130, shown in Figure 10);
a U-shaped channel plate (262) comprising a first vertically-extending portion comprising a first semiconductor sidewall (left side vertically-extending sidewall, labeled in annotated Figure 10) extending straight from a bottom edge thereof to a top edge thereof and contacting a sidewall of the source region (242, shown in Figure 10) and contacting a first sidewall of the insulating matrix layer (portion of top surface of 130 contacting the first vertically-extending portion is considered the first sidewall of the insulating matrix layer, Figure 10 shows the bottom of the left side vertically-extending semiconductor sidewall of the U-shaped channel plate 262 contacts this segment or first sidewall of the insulating matric layer portion 130), a second vertically-extending portion (right side vertically-extending sidewall) comprising a second semiconductor sidewall (labeled in annotated Figure 10) extending straight from a bottom edge thereof to a top edge thereof and contacting a sidewall of the drain region (244, shown in Figure 10) and contacting a second sidewall (portion of top surface of insulating matrix layer portion 130, Figure 10 shows the bottom of the right side semiconductor sidewall of the U-shaped channel plate contacts a second sidewall portion of the insulating matrix layer 130) of the insulating matrix layer (130/portion of 252), and a lower horizontally-extending portion (lower portion on top of the insulating matrix layer portion 130) connecting bottom ends of the first vertically-extending portion and the second vertically-extending portion (shown in Figure 10) and having a bottom surface located at, or below, a second horizontal plane (the second horizontal plane is the plane where the top surface of 130 meets the bottom surface of the source/drain regions 242, 244) including bottom surfaces of the source region and the drain region (bottom surface of lower horizontally extending portion is coplanar with the bottom surfaces of the source and drain region 242, 244, shown in Figure 10), wherein an entirety of a bottom surface of the lower horizontally-extending portion of the U-shaped channel plate (262) is in contact with the insulating matrix layer (in contact with portion 130 of the insulating matrix layer 130/portions of 252, see Figure 10); and
a U-shaped gate dielectric (264a) contacting inner sidewalls of the first vertically-extending portion and the second vertically-extending portion (shown in Figure 10) and contacting a top surface of the lower horizontally- extending portion (shown in Figure 10); and
a gate electrode (264b, 264c) contacting inner sidewalls of the U-shaped gate dielectric (264a) and a top surface of a horizontally-extending bottom portion of the U-shaped gate dielectric (shown in Figure 10).
Lai does not disclose that the source region comprises a combination of a source metallic fill material portion and a source metallic liner having a U-shaped vertical cross-sectional profile and laterally surrounding the source metallic fill material portion, wherein a top surface of the source metallic fill material portion, a top surface of the source metallic liner, and a top surface of a drain region are located within a first horizontal plane including a top surface of the insulating matrix layer.
Kim discloses in Figure 11L a source region (CA) comprising a combination of a source metallic fill material portion (156, para. [0147]) and a source metallic liner (154, para. [0146]) having a U-shaped vertical cross-sectional profile (see Figure 11L) and laterally surrounding the source metallic fill material portion (156, see Figure 11L), wherein a top surface of the source metallic fill material portion (156), a top surface of the source metallic liner (154), and a top surface of a drain region (also CA, see Figure 2A) are located within a first horizontal plane including a top surface of the insulating matrix layer (top insulation layer 142, see Figure 2A and 11L).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Kim into the teachings of Lai to include the claimed structure above. The structure was known in the art before the effective filing date of the present invention, and one would be motivated to combine the structures for the purpose of using a conductive barrier layer (154 of Kim) resulting in the predictable result, with no change in the device’s function, of reducing interdiffusion of materials. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
The combination of Lai and Kim discloses a first upper horizontally-extending portion (of the U-shaped channel plate 262, see portion extending horizontally, on top of the source region) adjoined to a top end the first vertically-extending portion (left side vertically-extending sidewall of the channel plate 262) and contacting a top surface segment of the source metallic liner (incorporated by Kim) within the first horizontal plane (plane including top surfaces of the source/drain regions is where the top surface of the metallic liner would reside by incorporation of the source taught by Kim into the source taught by Lai), and a second upper horizontally-extending portion (of the U-shaped channel plate 262, see portion extending horizontally, on top of the drain region) adjoined to a top end of the second vertically-extending portion (right side vertically extending sidewall of the channel plate 262) and contacting a top surface segment of the drain region (244) within the first horizontal plane (the segment of the drain region 244 contacting the second upper horizontally extending portion is within the second horizontal plane).
Since the source region of Kim has been incorporated into the source of Lai, the combination of teachings would include the metallic liner having a top surface coplanar with the top surface of the source metallic fill where the upper horizontally extending portion of the channel plate (262) of Lai contacts the metallic liner of the source region as incorporated by Kim.
Regarding claim 2, Lai discloses:
The semiconductor device of Claim 1, wherein:
a top surface of the U- shaped gate dielectric (264a) is located at, or above, the first horizontal plane (above, shown in annotated Figure 10); and
top surfaces of the first vertically-extending portion and the second vertically-extending portion of the U-shaped channel plate (262, see Figure 10) are located at, or above, the first horizontal plane (top surfaces of the portions of the channel plate 262 overlying the source/drain regions has a top surface above the top surfaces of the source/drain regions, which defines the first horizontal plane).
Regarding claim 4, Lai discloses:
The semiconductor device of Claim 1, further comprising a dielectric isolation layer (portion of 254 below the horizontal plane including the top surface of the gate electrode 264c, shown in annotated Figure 10 below) overlying the source region and the drain region (242, 244), wherein a top surface of the gate electrode (264b, 264c) is located within a horizontal plane including a top surface of the dielectric isolation layer (demonstrated in annotated Figure 10), wherein:
wherein a top surface of the U-shaped gate dielectric (264a) is located below the horizontal plane including the top surface of the dielectric isolation layer (the top surface of the dielectric isolation layer is coplanar with the top surface of the gate electrode 264c, 264b, which is above the topmost surface of the gate dielectric 264a, shown in annotated Figure 10); and
the dielectric isolation layer (portion of 254 below the horizontal plane including the top surface of the gate electrode 264c, 264b, annotated Figure 10) laterally surrounds the source region and the drain region (242, 244) and contacts sidewalls of the source region and the drain region (contact between 254 and the sidewalls of the source/drain regions 242, 244, is through the portions of 252 considered as a portion of the insulating matrix layer, shown in annotated Figure 10).
Regarding claim 11, Lai discloses:
The semiconductor device of Claim 1, wherein:
the U-shaped gate dielectric (262a) contacts an entirety of top surfaces of the U-shaped channel plate (262, shown in Figure 10); and
the U-shaped gate dielectric (262a) comprises horizontally-extending gate dielectric top portions that overlie peripheral portions of the source region and the drain region (242, 244, shown in Figure 10).
Regarding claim 26, Lai discloses:
The semiconductor device of Claim 1, wherein:
the U-shaped channel plate further comprises a first upper horizontally-extending portion (labeled in annotated Figure 10) comprising a first upper semiconductor sidewall having a bottom edge located at a planar top surface of the source region (242), and a second upper horizontally-extending portion (labeled in annotated Figure 10) comprising a second upper semiconductor sidewall having a bottom edge located at a planar top surface of the drain region (244); and
the U-shaped gate dielectric comprises a first upper-horizontally extending gate dielectric portion (labeled in annotated Figure 10) overlying the first upper horizontally-extending portion of the U-shaped channel plate (shown in annotated Figure 10) and having a first dielectric sidewall that is vertically coincident with the first upper semiconductor sidewall (shown in Figure 10), and further comprising a second upper horizontally-extending gate dielectric portion (labeled in annotated Figure 10) overlying the second upper horizontally-extending portion of the U-shaped channel plate and having a second dielectric sidewall that is vertically coincident with the second upper semiconductor sidewall (shown in Figure 10).
Regarding claim 31, the combination of Lai and Kim discloses wherein a region of the first upper horizontally-extending portion (left upper horizontally-extending portion of the channel plate 262) that contacts the planar top surface segment of the source metallic liner (as incorporated by Kim into the source of Lai) within the first horizontal plane (the segment of the source region 242 with the liner incorporated by Kim, contacting the first upper horizontally extending portion is located within the first horizontal plane) has a same material composition as a region of the lower horizontally-extending portion (portion of the channel plate 262 directly contacting the top surface of 130, since the channel 262 is shown as comprising a stacked material structure of oxide layers, see para. [0029], it is clear that the same material in a region of the channel plate contacting the source region 242 is the same material as a region of the channel plate contacting the insulating matrix layer portion 130) that contacts a recessed surface of the insulating matrix layer (130 and lateral portions of 252 make a recessed structure, the bottom surface of the recess being the upper surface of 130 between the lateral portions of 252) within the second horizontal plane (see Figure 10 and annotated Figure 10 below)
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lai and Kim as applied to claim 1 above, and further in view of Sharma et al. (“Sharma” US 2019/0305137).
Regarding claim 12, Lai does not disclose a capacitor structure including a first capacitor plate, a node dielectric, and a second capacitor plate, wherein the first capacitor plate is electrically connected to the source region.
Sharma discloses a semiconductor device (Figure 22A), further comprising a capacitor structure (2310, 2311, 2312, para. [0082]-[0084], Figure 23) including a first capacitor plate (2310, para. [0082]), a node dielectric (2312, para. [0084]), and a second capacitor plate (2311, para. [0082]), wherein the first capacitor plate (2310, para. [0082]) is electrically connected to the source region (209, para. [0082], Figure 22A, Figure 23 shows electrical connection between first capacitor plate 2310 and source region 209).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present invention to incorporate the teachings of Sharma into the teachings of Lai to include the semiconductor device of claim 1, further comprising a capacitor structure including a first capacitor plate, a node dielectric, and a second capacitor plate, wherein the first capacitor plate is electrically connected to the source region. The ordinary artisan would have been motivated to modify Lai in the above manner for the purpose of applying the semiconductor device to certain applications with storage capacitors (para. [0084]), such as memory devices.
Claims 13, 15, 29, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Lai et al. (“Lai” US 2020/0083380), Sharma et al. (“Sharma” US 2019/0305137), and Yamazaki et al. (“Yamazaki” US 2012/0187410).
Regarding claim 13, Lai discloses:
A semiconductor device [comprising a two-dimensional array of field effect transistors], wherein each of the field effect transistors comprises:
a source region and a drain region (242, 244) located within an insulating matrix layer (130 and region of 252 labeled in annotated Figure 10), wherein a top surface of the source region and a top surface of a drain region are located within a first horizontal plane including a top surface of the insulating matrix layer (demonstrated in annotated Figure 10), and a bottom surface of the source region (242) is in contact with the insulating matrix layer (shown in Figure 10) and a bottom surface of the drain region (244) is in contact with the insulating matrix layer (shown in Figure 10);
a U-shaped channel plate (262) comprising a first vertically-extending portion comprising a first semiconductor sidewall (labeled in annotated Figure 10) extending straight from a bottom edge thereof to a top edge thereof and contacting a sidewall of the source region (242, shown in Figure 10) and contacting a first sidewall of the insulating matrix layer (portion of top surface of 130, Figure 10 shows the bottom of the semiconductor sidewall of the U-shaped channel plate contacts a first sidewall of the insulating matrix layer 130), a second vertically-extending portion (labeled in annotated Figure 10) extending straight from a bottom edge thereof to a top edge thereof and contacting a sidewall of the drain region (244, shown in Figure 10) and contacting a second sidewall (portion of top surface of 130, Figure 10 shows the bottom of the semiconductor sidewall of the U-shaped channel plate contacts a second sidewall of the insulating matrix layer 130) of the insulating matrix layer, and a lower horizontally-extending portion (see Figure 10) connecting bottom ends of the first vertically-extending portion and the second vertically-extending portion (shown in Figure 10), a first upper horizontally-extending portion (top left horizontally extending portion of the channel plate 262) adjoined to a top end the first vertically-extending portion (left side vertically-extending portion of the channel plate 262) and contacting a top surface segment of the source region (242, contact is made through the intervening layer 252) within the first horizontal plane (the segment in contact with the first upper-horizontally extending portion is within the first horizontal plane since it is the top surface of the source region itself), and a second upper horizontally-extending portion (right side upper horizontally-extending portion of the channel plate 262) adjoined to a top end of the second vertically-extending portion (ride side vertically extending portion of the channel plate 262) and contacting a top surface segment of the drain region (244) within the first horizontal plane (the segment in contact with the second upper-horizontally extending portion is within the first horizontal plane since it is the top surface of the drain region itself), wherein an entirety of a bottom surface of the lower horizontally-extending portion of the U-shaped channel plate (262) is in contact with the insulating matrix layer (in contact with 130 portion in Figure 10);
a U-shaped gate dielectric (264a) contacting inner sidewalls of the U-shaped channel plate (262, shown in Figure 10); and
a gate electrode (264b, 264c) contacting inner sidewalls of the U-shaped gate dielectric (264a, shown in Figure 10),
Lai does not disclose a two-dimensional array of field effect transistors and wherein the field effect transistors are laterally spaced among one another by a dielectric isolation layer overlying each of the source regions and the drain regions.
Sharma discloses a semiconductor device (Figure 23) comprising a two-dimensional array of field effect transistors (100, para. [0081]) and wherein the field effect transistors (100) are laterally spaced among one another by a dielectric isolation layer (2303, 135, and thin dielectric layer in annotated Figure 23) overlying each of the source regions (209, para. [0044], Figure 22A) and the drain regions (210, para. [0044], Figure 22A) and contacting sidewalls of each of the source regions (209) and the drain regions (210) (Figure 23 shows the dielectric isolation layer 2303, 135, and thin layer above laterally surrounding and contacting sidewalls of the source region 109 and drain region 110).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present invention to incorporate the teachings of Lai into the teachings of Sharma to include transistor structure disclosed in Lai with predictable results. The transistor disclosed in Lai was known in the art before the effective filing date of the invention. Simple substitution of the transistor disclosed in Sharma with the transistor of Lai would yield predictable results, such as a simplified process due to the U-shaped channel of Lai and Sharma (Lai, para. [0004]). See MPEP 2143 Rationale B.
Lai and Sharma do not disclose that the lower horizontally extending portion of the U-shaped channel plate has a bottom surface located below a second horizontal plane including bottom surfaces of the source region and the drain region.
However, Yamazaki discloses in Figure 1A a bottom surface of the lower horizontally-extending portion of the U-shaped channel plate (oxide semiconductor layer 144) is located below the second horizontal plane including bottom surfaces of the source/drain regions (142a/142b, see Figure 1A).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Yamazaki into the teachings of Lai to include the recessed gate structure as claimed above and taught by Yamazaki for the purpose of reducing short channel effects (Yamazaki, abstract).
Regarding claim 15, Sharma discloses:
The semiconductor device (Figure 23) of Claim 13, further comprising a two-dimensional array of capacitor structures (20, para. [0082]), wherein a capacitor structure (2311, 2312, 2310, para. [0082]-[0084], Figure 23) of the two-dimensional array of capacitor structures (20) comprises a first capacitor plate (2310, para. [0082]) that is electrically connected to a source region (para. [0082]) of a respective one of the field effect transistors (100, Figure 23 shows the electrical connection between the first capacitor plate 2310 and source region 109) within the two-dimensional array of field effect transistors (Figure 23), a node dielectric (2312, para. [(0084]), and a second capacitor plate (2311, para. [0082]).
The ordinary artisan would have been motivated to modify Lai to include a two-dimensional array of capacitor structures, wherein each of the capacitor structures comprises a first capacitor plate that is electrically connected to a source region of a respective one of the field effect transistors within the two-dimensional array of field effect transistors, a node dielectric, and a second capacitor plate for the purpose of applying the semiconductor device to certain applications with storage capacitors (para. [0084]), such as memory devices.
Regarding claim 29, Lai discloses:
The semiconductor device of Claim 13, wherein the U-shaped channel plate (262) comprises a first upper horizontally-extending portion (top left horizontally extending portion of 262) that is adjoined to a top end of the first vertically-extending portion (left portion of the vertically extending portion of 262) of the U-shaped channel plate (262) and has a bottom surface that is in contact with a planar top surface of the source region (242, Figure 10 shows the first upper-horizontally extending portion of the U-shaped channel plate has a bottom surface in contact with the top surface of the source region through the intervening layer 252).
Regarding claim 32, Lai discloses wherein a region of the first upper horizontally-extending portion (left upper horizontally-extending portion of the channel plate 262) that contacts the planar top surface of the source region (242) within the first horizontal plane (the segment of the source region 242 contacting the first upper horizontally extending portion is located within the first horizontal plane) has a same material composition as a region of the lower horizontally-extending portion (portion of the channel plate 262 directly contacting the top surface of 130, since the channel 262 is shown as comprising a stacked material structure of oxide layers, see para. [0029], it is clear that the same material in a region of the channel plate contacting the source region 242 is the same material as a region of the channel plate contacting the insulating matrix layer portion 130) that contacts a recessed surface of the insulating matrix layer (130 and lateral portions of 252 make a recessed structure, the bottom surface of the recess being the upper surface of 130 between the lateral portions of 252) within the second horizontal plane (see Figure 10 and annotated Figure 10 below)
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Lai, Sharma, and Yamazaki as applied to claim 13 above, and further in view of Fujita et al. (“Fujita” US 2023/0111003) and Nakamura et al. (“Nakamura” US 2002/0080294).
Regarding claim 14, Sharma discloses:
the semiconductor device of claim 13, wherein: the two-dimensional array of field effect transistors (100, Figure 23) is arranged as a rectangular array extending along a first horizontal direction (HD1, annotated Figure 23) and along a second horizontal direction (HD2, annotated Figure 23);
Sharma and Lai do not disclose:
the gate electrode arranged along the second horizontal direction is merged as a respective gate electrode line that continuously extends along the second horizontal direction.
Fujita discloses:
the gate electrode (52, 54S, Figures 8A-8D) arranged along the second horizontal direction (hd2, Figure 8B) is merged as a respective gate electrode line (52, 54S) that continuously extends along the second horizontal direction (hd2, para. [0168], Figure 8B).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present invention to incorporate the teachings of Fujita into the teachings of Sharma to include a continuous, shared gate electrode extending along a second horizontal direction of the field effect transistor array for the purpose of reducing processing complexity and material use (Nakamura, para. [0059]).
Claim 30 is rejected under 35 U.S.C. 103 as being unpatentable over Lai and Nagai as applied to claim 21 above and further in view of Yamazaki et al. (“Yamazaki” US 2012/0187410).
Regarding claim 30, Lai does not disclose that the bottom surface of the lower horizontally-extending portion of the U-shaped channel plate is located below the second horizontal plane.
However, Yamazaki disclose in Figures 1A a bottom surface of the lower horizontally-extending portion of the U-shaped channel plate (oxide semiconductor layer 144) is located below the second horizontal plane (plane including bottom surfaces of the source/drain regions 142a/142b, see Figure 1A).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Yamazaki into the teachings of Lai and Nagai to include the recessed gate structure as claimed above and taught by Yamazaki for the purpose of reducing short channel effects (Yamazaki, abstract).
Annotated Figures
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Allowable Subject Matter
Claims 7 and 8 are allowed.
The prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art to the claimed limitations (which has been made of record, specifically Ohno et al. US 2023/0012834) fail to disclose (by themselves or in combination) the limitations of claims 7 and 8 in combination with the additionally claimed features.
Regarding claim 7, the features are drawn to at least Figures 23B, 23D, and 23E of the instant application. The claim essentially requires that the gate electrode (35) extends laterally (horizontally in Figure 23E) outside of the gate dielectric (30, shown in at least Figure 23E) where the portion of the gate electrode (35) extending laterally outside of the gate dielectric (30) has a greater length (gl2, see Figure 23D) than the length (gl1, see Figure 23B) of the portion of the gate electrode (35) within the gate dielectric (30) and the channel plate (20). Specifically:
a first portion of the gate electrode (35) located between the first vertically-extending portion and the second vertically-extending portion (of the channel plate 20, see Figure 23B) has a first gate length (gl1) along the first horizontal direction (horizontal direction in Figure 23B), and has a first top surface segment located within a horizontal plane including a top surface of the isolation dielectric layer (see Figure 23B); and
a second portion of the gate electrode (350) laterally extending outside an area of the U-shaped gate dielectric (30) in a plan view and laterally offset from the first portion along the second horizontal direction (into the page in Figure 23B) has a second gate length (gl2) along the first horizontal direction that is greater than the first gate length (gl1), and has a second top surface segment located within the horizontal plane including the top surface of the isolation dielectric layer (see Figure 23B).
Regarding what the closest prior art discloses, Ohno et al. discloses in para. [0031] that the gate structure (116, which includes the gate electrode 114 and the gate dielectric) may extend along the y-direction shown in Figures 4 and 5. This configuration as disclosed by Ohno does not teach or suggest a portion of the gate electrode extending outside of the gate dielectric as claim 7 requires, and the other closest and cited prior art does not suggest a motivation as to why an ordinary artisan would modify the teachings of Ohno to require a portion of the gate electrode extending laterally outside the gate dielectric.
Regarding claim 8, the features are drawn to at least Figured 23B, 23D, and 23E of the instant application. The claim essentially requires that the gate electrode (35) laterally extends outside of the gate dielectric (30, shown in at least Figure 23E) where the portion of the gate electrode (35) extending laterally outside of the gate dielectric (30) contacts the insulating matrix layer (60) and has a greater depth (gd2) than the depth (gd1) of the portion of the gate electrode (35) within the gate dielectric (30). Specifically:
a first portion of the gate electrode (35) located between the first vertically-extending portion and the second vertically-extending portion (of the channel plate 20) has a first gate depth (gd1) along a vertical direction, and has a first top surface segment located within a horizontal plane including a top surface of the isolation dielectric layer (see Figure 23E); and a second portion of the gate electrode (35) laterally (horizontally in Figure 23E) extending outside the area of the U- shaped gate dielectric (20) in the plan view has a second gate depth (gd2) along the vertical direction that is greater than the first gate depth (gd2) and is in contact with a recessed surface of the insulating matrix layer (see Figure 23E), and has a second top surface segment located within the horizontal plane including the top surface of the isolation dielectric layer (see Figure 23E).
Similarly in regards to claim 7, Ohno et al. discloses in para. [0031] that the gate structure (116, which includes the gate electrode 114 and the gate dielectric) may extend along the y-direction shown in Figures 4 and 5. This configuration as disclosed by Ohno does not teach or suggest a portion of the gate electrode extending laterally outside of the gate dielectric as claim 8 requires, and the other closest and cited prior art does not suggest a motivation as to why an ordinary artisan would modify the teachings of Ohno to require a portion of the gate electrode extending laterally outside the gate dielectric, thereby having a greater depth than the portion of the gate electrode within the gate dielectric.
Thus, the Applicant's claims 7 and 8 are determined to be novel and non-obvious.
Response to Arguments
Applicant’s arguments with respect to the prior art rejections of record have been considered but are moot because the new ground of rejection does not rely on the same interpretation of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899
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