DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 25-29 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention. The amendment introduces the following subject matter: “a source contact and a drain contact spaced apart in a lateral direction.” Applicant has not pointed out, and there does not appear to be, support for this subject matter in the specification, claims, or drawings as originally filed. When filing an amendment an applicant should show support in the original disclosure for new or amended claims. See MPEP §§ 714.02 and 2163.06 (“Applicant should specifically point out the support for any amendments made to the disclosure.”). To comply with the written description requirement of 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph, … each claim limitation must be expressly, implicitly, or inherently supported in the originally filed disclosure.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10-14, 18-20, and 22-24 are rejected under 35 U.S.C. 103 as being unpatentable over Diaz et al. (US 2016/0093745) in view of Naylor et al. (US 2021/0083122).
With regard to claim 10, Diaz teaches, in Fig 7I, a device, comprising:
a dielectric (710 formed from 701, see [0072-0073]) extending from a first source/drain contact (740a, 740b, [0083-0084]) to a second source drain contact (740a, 740b, [0084]);
a 2D material (720, [0018, 0075]) around the dielectric (710) and extending from the first source/drain contact (740a) to the second source drain contact (740b); and
an active gate (730, [0080]) around the 2D material (720).
Diaz does not explicitly teach a conductive oxide material on a portion of the dielectric, also does not disclose wherein the 2D material (720) is interposed between the conductive oxide material and the active gate (730).
Naylor teaches a conductive oxide material acting as seed material for a 2D material ([0045-0047]) to “reduce electrical leakage to/from one or more of the transistor terminals stemming from either surface states of the channel semiconductor material or compositional changes within the channel semiconductor material” ([0025]).
It would have been obvious to one have ordinary skill in the art at the time of filing to that an alternate way of creating the 2D material in Diaz would be to instead use a conductive seed material of Naylor to create the dielectric in Diaz, thus resulting in the 2D material being interposed between the conductive oxide material (seed material in Naylor) and the active gate in Diaz, because as alternative method of creating the 2D material, Naylor teaches it reduces electrical leakage to/from one or more of the transistor terminals. Furthermore, one of ordinary skill in the art would have been capable of applying this known technique to a known device and the results would have been predictable to one of ordinary skill in the art.
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Regarding claim 11, Diaz in view of Naylor teaches claim 10, and further teaches in Fig 7H, wherein the active gate is isolated from the first source/drain contact by a dielectric material (735, [0081-0083], not included in Fig 7I but present in cross-sectional view 7H).
Regarding claim 12, Diaz in view of Naylor teaches claim 10 and wherein the active gate comprises in Fig 7I of Diaz,
a high-k dielectric material (731, [0080] of Diaz; 315 [0064] of Naylor) around a portion of the 2D material (see Figure of Diaz); and
a gate metal (732, [0080] of Diaz; 220, [0064] of Naylor) around a portion of the dielectric material (see Figure of Diaz).
Regarding claim 13, Diaz in view of Naylor teaches claim 10, in Fig 7I of Diaz, wherein the conductive oxide material is formed around the dielectric (using Naylor’s method of manufacturing 2D material from a conductive oxide seed material it would be obvious to the ordinary artisan that the conductive oxide would necessarily be around dielectric 710 and under 2D material 720 of Fig 7I).
Regarding claim 14, Diaz in view of Naylor teaches claim 14 wherein the 2D material is an N-type material or a P- type material ([0039]).
Regarding claim 18, Diaz teaches, in Figs 7H-7I, a transistor structure, comprising:
a source metal (740a,740b, [0084]);
a drain metal (740a,740b, [0084]);
a two-dimensional (2D) channel material (720, [0075]) around a portion of a seed layer that extends between the source metal and the drain metal;
a dielectric (731,[0080]) around a portion of the 2D channel material; and
a gate metal (732, [0080]) around a portion of the dielectric and isolated from the source metal and the drain metal by a dielectric material (735, [0081-0083], not included in Fig.7I but present in cross-sectional view 7H), the 2D channel material (720) interposed between the gate metal (732) and seed layer.
However, Diaz does not explicitly teach that the layer is a seed layer nanosheet or that the dielectric (731) is explicitly a high-k dielectric. Although Diaz does teach use of high-K dielectric in other embodiments.
Naylor teaches, in Fig 3A, a seed layer nanosheet (metal oxide, [0045-0047]) for a 2D channel material together with a high-k dielectric (315, [0064]) to “reduce electrical leakage to/from one or more of the transistor terminals stemming from either surface states of the channel semiconductor material or compositional changes within the channel semiconductor material” ([0025]).
It would have been obvious to a person having ordinary skill in the art at the time of filing to use the seed layer nanosheet and high-k dielectric of Naylor in the device of Diaz, because Naylor teaches it reduces electrical leakage to/from one or more of the transistor terminals. Furthermore, an alternative method of creating a 2D material is known and within the purview of an artisan.
With regard to claim 19, Diaz in view of Naylor teaches, wherein the source metal and the drain metal are in contact with a portion of the high-k dielectric (See Figure 7I).
With regard to claim 20, Diaz in view of Naylor teaches, wherein the source metal and the drain metal are ink contact with the 2D channel material (See Figure 7I).
Regarding claim 22, Diaz in view of Naylor discloses a transistor structure of claim 18, further comprising a dielectric layer interposed between the 2D channel material and each of the source metal and the drain metal as detailed above.
Regarding claim 23, Diaz in view of Naylor discloses the transistor structure of claim 22, wherein the dielectric layer is also interposed between the gate metal and each of the source metal and the drain metal as detailed above.
Regarding claim 24, Diaz in view of Naylor discloses the transistor structure of claim 18, wherein the seed layer nanosheet directly contacts a sidewall of the source metal and a sidewall of the drain metal as detailed above.
Claims 15 and 16 is rejected under 35 U.S.C 103 as being unpatentable over Diaz et al. (US 2016/0093745 in view of Naylor et al. (US 2021/0083122) as applied to claim 10 above, and further in view of Frougier et al. (US 10388732).
Regarding claim 15, Diaz in view of Naylor teach wherein the dielectric is a first dielectric, the 2D material is a first 2D material, the conductive oxide is a first conductive oxide, and the active gate is a first active gate, the device most of the limitation of this claim, as set forth above with regard to claim 10.
However, Diaz in view of Naylor do not explicitly teach
a second dielectric extending from a third source/drain contact to a fourth source drain contact;
a second conductive oxide material on a portion of the second dielectric;
a second 2D material around the second dielectric and extending from the third source/drain contact to the fourth source drain contact; and
a second active gate around the second 2D material.
Frougier teaches, in Figs 9c and 11,
a second dielectric (50, col.7, lines 8-12) extending from a third source/drain (52, col. 7, lines 14-29 and 45-51) contact to a fourth source drain contact (52, col. 7, lines 14-29 and 45-51);
a second conductive oxide material ([0045-0047] of Naylor) on a portion of the second dielectric;
a second 2D material (44b, col. 6, lines 10-31 and 50-58) around the second dielectric and extending from the third source/drain contact to the fourth source drain contact; and
a second active gate (37 and 39, col. 5, lines 16-23) around the second 2D material (see annotated Figure 11 of Frougier reproduced above) to develop “non-planar field effect transistors that may permit additional increases in packing density in an integrated circuit,” (col. 1, lines 22-25).
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It would have been obvious to a person having ordinary skill in the art at the time of filing to combine the device Diaz in view of Naylor by adding additional layers as is shown in the structure of Frougier, because such an addition is within the purview of the artisan and helps develop non-planar field effect transistors to increase the packing density in an integrated circuit.
Regarding claim 16, Diaz in view of Naylor and further in view of Frougier teach (combined structure represented by Fig. 11), wherein:
the first dielectric, conductive oxide material, 2D material, active gate, first source/drain contact, and second source drain contact form a first transistor structure (not numbered but clearly shown in annotated figure 11 above),
the second dielectric, second conductive oxide material, second 2D material, second active gate, third source/drain contact, and fourth source drain contact form a second transistor structure (not numbered but clearly shown in annotated figure 11), and
the second transistor structure is disposed above the first transistor structure and separated by a third dielectric (Frougier, Fig 11, 30, col.4, lines 29-26).
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[AltContent: textbox (Frougier )][AltContent: textbox (Cheng )]Claim 17 is rejected under 35 U.S.C 103 as being unpatentable over Diaz et al. (US 2016/0093745 in view of Naylor et al. (US 2021/0083122) and Frougier et al. (US 10388732), as applied to claim 15 above, and further in view of Cheng et al. (US 2022/0140098).
Regarding claim 17, the combined device of Diaz, Naylor, and Frougier teach most of the limitations of this claim, as set forth above with regard to claim 15.
Here taking an alternate interpretation of the 1st and 2nd transistor structures of Frougier reproduced in Fig 11 above.
However, the combined device of Diaz, Naylor, and Frougier do not explicitly teach wherein the 2D material is an N-type material, and the second 2D material is a P-type material.
Cheng teaches, in Fig 16B, a “p-type nano-FET and the n-type nano-FET,” ([0045]) wherein the 2D material is an N-type material ([0015]), and the second 2D material is a P-type material ([0015]) to “solve the fermi level pinning problem, and hence the performance of both p-type nano-FET and n-type nano-FET,” ([0048]).
It would have been obvious to a person having ordinary skill in the art at the time of filing to take the combined the device of Diaz, Naylor, and Frougier and add the N-type and P-type 2D material of Cheng to solve the fermi level pinning problem.
Claims 21 is rejected under 35 U.S.C 103 as being unpatentable over Diaz et al. (US 2016/0093745 in view of Naylor et al. (US 2021/0083122) as applied to claim 18 above, and further in view of Frougier et al. (US 10388732).
Regarding claim 21, Diaz in view of Naylor wherein the high-k dielectric is a first high-k dielectric as described above, but the transistor structure does not explicitly disclose a second high-k dielectric, wherein the gate metal (732) is interposed between the first high-k dielectric (731 as modified by Naylor) and the second high-k dielectric.
Frougier et al. teaches, in Figs 9c and 11, a second dielectric (50, col.7, lines 8-12) extending from a third source/drain (52, col. 7, lines 14-29 and 45-51) contact to a fourth source drain contact (52, col. 7, lines 14-29 and 45-51).
It would have been obvious to a person having ordinary skill in the art at the time of filing to take the combined the device of Diaz in view of Naylor with Frougier to teach a second high-k dielectric, because an additional high-k would increase the effective electric field and within the purview of one having ordinary skill in the art.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893