DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the specification for the claim limitations of "the ferroelectric layer comprises a plurality of crystalline domains intrinsically created by and corresponding to the two adjacent surfaces of the gate electrode", as recited in claim 1 (note: paragraph [0025] discloses that “In an embodiment, the ferroelectric layer 130 covers and laterally encloses the gate electrode 120 … the ferroelectric layer 130/131 is deposited over protruding edges and/or denting edges (defined by the side surfaces of the gate electrode 120) of the gate electrode 120, which intrinsically creates a plurality of crystalline domains (e.g., crystalline (ferroelectric) domains 132, 134, 136) …. In some embodiments, the crystalline domains (e.g., crystalline domains 132, 134, 136) may correspond to side surfaces S1, S2, S3 of the gate electrode 120).
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitations of "… a plurality of crystalline domains intrinsically created by and corresponding to the two adjacent surfaces of the gate electrode", as recited in claim 1, are unclear as to what is meant by “corresponding to”; and as to how a plurality of crystalline domains (material regions) correspond to “two adjacent surfaces” (geometric features).
The claimed limitation of "a plurality of crystalline domains", as recited in claim 2, is unclear as to whether said limitation is the same as or different from "a plurality of crystalline domains", as recited in claim 1.
The claimed limitation of "an upper side surface of the gate electrode", as recited in claim 4, is unclear as to whether said limitation is the same as or different from "two adjacent surfaces of the gate electrode", as recited in claim 1.
The claimed limitation of "a lateral side surface of the gate electrode", as recited in claim 4, is unclear as to whether said limitation is the same as or different from "two adjacent surfaces of the gate electrode", as recited in claim 1.
The claimed limitation of "a uniform thickness", as recited in claims 4, 23 and 24, is unclear as to whether said limitation is the same as or different from "a uniform thickness", as recited in claim 1 and 21, respectively.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 7 and 21-24, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Sharma et al. (2020/0388685) in view of Lee et al. (2021/0313439).
Sharma et al. show in Figs. 2, 3 (source/drain electrodes 250 extending through a dielectric material 340 portion only), 16H and related text
As for claims 1 and 2, a ferroelectric memory device, comprising:
a substrate 205;
a gate electrode 220 disposed over the substrate, wherein a full height of the gate electrode is greater than a full width of the gate electrode;
a gate dielectric layer 315 at least covering two adjacent surfaces of the gate electrode, wherein the gate dielectric layer covers the two adjacent surfaces of the gate electrode with a uniform thickness;
a pair of source/drain electrodes 250 disposed on the substrate and disposed on two opposite sides of the gate electrode, respectively; and
wherein the gate dielectric layer covers and laterally enclosed the gate electrode.
As for claim 21, a ferroelectric memory device, comprising:
a substrate205;
a gate electrode 220 disposed over the substrate, wherein a full height of the gate electrode is greater than a full width of the gate electrode;
a gate dielectric layer 315 at least covering two adjacent side surfaces of the gate electrode with a uniform thickness;
a channel layer 210 covering the gate dielectric layer with a uniform thickness in a cross-sectional view;
a dielectric structure 340 covering the substrate and in physical contact with an upper surface of the channel layer; and
a pair of source/drain electrodes extending through the dielectric structure over the substrate and disposed on two opposite sides of the gate electrode, respectively.
Sharma et al. do not disclose the gate dielectric layer is a ferroelectric layer (claims 1 and 21), the ferroelectric layer comprising a plurality of crystalline domains intrinsically created by and corresponding to the two adjacent surfaces of the gate electrode (claim 1); and the ferroelectric layer comprising a plurality of crystalline domains corresponding to at least the two adjacent surfaces of the gate electrode (claim 2).
Lee et al. teach in Fig. 2 and related text:
As for claims 1 and 21, a ferroelectric layer 201 at least covering two adjacent surfaces of the gate electrode 101 ([0068]); the ferroelectric layer comprising a plurality of crystalline domains intrinsically created by and corresponding to the two adjacent surfaces of the gate electrode ([0060], [0064]).
As for claim 2, the ferroelectric layer comprising a plurality of crystalline domains corresponding to at least the two adjacent surfaces of the gate electrode ([0060], [0064]).
Sharma et al. and Lee et al. are analogous art because they are directed to a field effect transistor and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sharma et al. with the specified feature(s) of Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use ferroelectric layer as a gate dielectric layer, and the ferroelectric layer comprising a plurality of crystalline domains intrinsically created by and corresponding to at least the two adjacent surfaces of the gate electrode, as taught by Lee et al., in Sharma et al.’s device, in order to reduce parasitic capacitance, enhance carrier mobility, improve electrostatic control and better scalability of the device.
As for claim 3, the combined device shows a channel layer 210 covering the ferroelectric layer and is between the ferroelectric layer and the pair of source/drain electrodes with a uniform thickness (Sharma: Figs. 1 and 16H).
As for claim 4, the combined device shows the ferroelectric layer covers an upper side surface of the gate electrode, a lateral side surface of the gate electrode and an upper surface of the substrate with a uniform thickness (Sharma: Fig. 16H).
As for claim 5, the combined device shows a channel layer completely covering the ferroelectric layer in a cross-sectional view, wherein the ferroelectric layer covers the upper side surface and the lateral side surface of the gate electrode (Sharma: Fig. 16H).
As for claim 7, the combined device shows a channel layer covering a region between the pair of source/drain electrodes with a uniform thickness (Sharma: Figs. 2 and 16H).
As for claim 22, the combined device shows the channel layer is disposed between the ferroelectric layer and the pair of source/drain electrodes (Sharma: Figs. 2 and 16H).
As for claim 23, the combined device shows the channel layer covers a region between the pair of source/drain electrodes with a uniform thickness (Sharma: Fig. 16H).
As for claim 24, Sharma et al. and Lee et al. disclosed substantially the entire claimed invention, as applied to claim 21 above, except the ferroelectric layer has a uniform thickness in a range from 1 nm to 15 nm.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the ferroelectric layer having a uniform thickness in a range from 1 nm to 15 nm, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
Response to Arguments
Applicant's arguments filed January 7, 2026 have been fully considered but they are not persuasive.
Applicant argues that “the now-pending claim 1 stands novel and non-obvious over the cited references and are allowable” because 1) “applicant respectfully submits that the cited references fail to read on each and every feature of the now-pending claim 1 for at least the reason set forth below. For example, both Sharma and Van Duran fails to teach any ferroelectric layer covering the gate electrode. It is the gate dielectric 315 of Sharma that covers the gate electrode 220. Similarly, it is the gate dielectric 506 that covers the gate electrode 504. On the other hand, Lee teaches the ferroelectric layer 201 but the ferroelectric layer 201 does not cover any two adjacent surfaces of the gate electrode 100 with a uniform thickness, and the full height of the gate electrode 100 is not greater than a full width of the gate electrode 100. Therefore, it would not be obvious to one of ordinary skills in the art to have the motivations to incorporate the ferroelectric layer 201 of Lee with the structures of Sharma and Van Duran” and 2) Moreover, according to para. [0025] of the application, the configuration and the motivation of the ferroelectric layer covering two adjacent surfaces of the gate electrode is to create a plurality of crystalline domains without having to adjust any doping type. None of the cited reference has mentioned such purposes, and the gate dielectric 315 of Sharma definitely cannot achieve such result, so it would certainly not obvious to one of ordinary skills in the art to obtain each and every feature set forth in the now-pending claim 1 based on the disclosure of cited reference.
The examiner respectfully disagrees because:
1) Lee was not cited to teach an artisan the entire structure of the claimed invention. Lee was merely cited to teach an artisan “a ferroelectric layer at least covering two adjacent surfaces of the gate electrode”; and
2) It is noted that the features upon which applicant relies (i.e., “without having to adjust any doping type”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Furthermore, Lee discloses that the ferroelectric layer is a conformal polycrystalline; and it is well known in the art that a conformal polycrystalline ferroelectric film deposited over a high aspect ratio feature intrinsically builds crystalline domains corresponding to respective two adjacent surfaces of the structure due to surface-dependent growth and crystallization conditions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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