DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17, 19, 25, 26 and 28 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 17 and 28, the limitation ”wherein the base is floating or is connected to the emitter through an electrical connection external to the transistor,” recited in claim 17 and similarly in claim 28, does not appear to have support in the originally filed disclosure. Specifically, there is no disclosure as to how the base is connected to the emitter.
Note the dependent claims do not cure the deficiencies of the claims on which they depend.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17, 19, 25, 26 and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 17 and 28, the limitation ”wherein the base is floating or is connected to the emitter through an electrical connection external to the transistor,” is unclear as to what is required by “through an electrical connection external to the transistor.” Specifically, there is no description of the connection between the base and the emitter, and therefore it is unclear as to the proper scope of “electrical connection,” and “external to the transistor.”
Note the dependent claims necessarily inherit the indefiniteness of the claims on which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under pre-AIA 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under pre-AIA 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of pre-AIA 35 U.S.C. 103(c) and potential pre-AIA 35 U.S.C. 102(e), (f) or (g) prior art under pre-AIA 35 U.S.C. 103(a).
Claims 1, 4-7, 10-11 and 27 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tseng (US 2007/0045743; herein “Tseng”) in view of Schneider et al. (US 2006/0226488; herein “Schneider”) and Chiozzi (US 6,020,623; herein “Chiozzi”).
Regarding claim 1, Tseng discloses in Fig. 5 and related text a semiconductor device comprising:
a substrate (500);
a transistor in the substrate, comprising:
a collector comprising an n-type region (512, see [0022] and [0023]);
a base comprising a first p-type region (510, see [0022] and [0023]); and
an emitter comprising an N well (502/514, see [0022] and [0023]);
a first p well (504, see [0023]) in the substrate and under the first p-type region;
a first isolation region in the substrate between the n-type region and the first p-type region (e.g. at least a region of the FOX between 512 and 510), wherein the first P well (504) physically contacts and extends along a sidewall of the first isolation region and a first portion of a bottommost surface of the first isolation region (see Fig. 5);
a substrate p-type region (substrate 500 and 506, see [0022]), wherein the first P well (504) and the N well (502) extend into the substrate p-type region, wherein the substrate p-type region physically contacts and extends along a lower surface of the n-type region (512);
a second isolation region in the substrate between the n-type region and the N well (e.g. at least a region of the FOX between 512 and 514).
Tseng does not disclose
a second P well, wherein the first P well and the N well extend into the second P well, wherein the second P well physically contacts and extends along a lower surface of the n-type region;
a PN junction connected in series with the transistor, wherein the PN junction comprises the N well and a second p-type region over the N well.
In the same field of endeavor, Schneider teaches in Fig. 12a and related text
a P well (see [0051]; see also 44 in Fig. 12a) in the substrate instead of a P type substrate.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Tseng by having a P well in the substrate, as taught by Schneider, in order to allow for use of an N type substrate or allow for appropriate doping of the P well for NPN bipolar transistors (see Schneider [0051]). Further, Schneider shows that P wells is an equivalent structure to a P type substrate known in the art. Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute the P well of Schneider for the P type substrate of Tseng. The limitation “a second P well in the substrate, wherein the first P well and the N well extend into the second P well, wherein the second P well physically contacts and extends along a lower surface of the n-type region” is therefore taught by the first P well and the N well extending into the substrate p-type region and the substrate p-type region physically contacting and extending along a lower surface of the n-type region, as shown by Tseng, and employing the P well instead of the P substrate, as shown by Schneider. Note that the claimed second P well is a combination of the 506 of Tseng and the P well replacing the substrate p-type region 500 of Tseng, as taught by Schneider.
In the same field of endeavor, Chiozzi teaches in Fig. 2 (the embodiment of opposite polarities from those shown, see col. 3 line 4-6) and related text
a PN junction (275, see col. 3 line 56) connected in series with the transistor, wherein the PN junction comprises the N well and a second p-type region over the N well (245 over emitter 240/227, see col. 3 lines 21, 34, 39, 55-62).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Tseng and Schneider by having a PN junction connected in series with the transistor, wherein the PN junction comprises the N well and a second p-type region over the N well, as taught by Chiozzi, in order to achieve a Zener diode for, e.g. voltage limiting or reference (see Chiozzi col. 1 lines 11-17), which has low series resistance and good reliability (see Chiozzi col. 2 lines 18-22).
Regarding claim 4, Tseng further discloses wherein the n-type region (512), the first p-type region (510), the N well (502/514), the first isolation region (at least a region of FOX between 510 and 512), and the second isolation region (at least a region of FOX between 512 and 514) have a coplanar upper surface (note that one can choose a “region” of each FOX such it reads on the claimed limitation; note that the broadest reasonable “region” is interpreted as a continuous part of a surface, space or body).
Regarding claim 5, Tseng further discloses wherein the first isolation region (at least a region of FOX between 510 and 512) extends continuously from the first p-type region (510) to the n-type region (512), and wherein the second isolation region (at least a region of FOX between 512 and 514) extends continuously from the n-type region (512) to the N well (502/514).
Regarding claim 6, Tseng further discloses wherein the first isolation region and the second isolation region extend deeper into the substrate than the n-type region and the first p-type region, wherein the N well extends deeper into the substrate than the first isolation region and the second isolation region (note that one can choose portions of 512 and 510 to read on the “regions” such that the claimed limitation is met; note that the broadest reasonable “region” is interpreted as a continuous part of a surface, space or body).
Regarding claim 7, the combined device shows wherein the first P well (Tseng: 504) contacts and extends along a lower surface of the first p-type region (Tseng: 510), wherein the second P well (Schneider: 44; Tseng: substrate p-type region 500 and 506) contacts and extends along a second portion of the bottommost surface of the first isolation region.
Regarding claim 10, the combined device shows the N well (Tseng: 502/514) physically contacts and extends along a sidewall of the second isolation region and a first portion of a bottommost surface of the second isolation region (at least a region of FOX between 512 and 514), wherein the second P well (Schneider: 44; Tseng: substrate p-type region 500 and 506) physically contacts and extends along a second portion of the bottommost surface of the second isolation region.
Regarding claim 11, the combined device shows wherein there is a depletion region at the lower surface of the n-type region (see Tseng Fig. 5).
Regarding claim 27, the combined device shows wherein the PN junction is coupled between the emitter and electrical ground.
Additionally, note that is it is the Office' s position that the limitation is directed to a method of using the device and that because the combined device has all of the structural limitations of the claimed invention the device is capable of being operated in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.II and 2112.01.
Claim 2 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tseng, Schneider, and Chiozzi, as applied to claim 1 above, and further in view of Claverie (US 6,144,066; herein “Claverie”).
Regarding claim 2, Tseng as modified does not disclose
wherein the second p-type region is a p-type metal contact;
wherein a lower surface of the p-type metal contact facing the substrate contacts and extends along an upper surface of the N well.
in the same field of endeavor, Claverie teaches in Fig. 6 and related text a PN junction (Schottky diode between 33 and 31, see col. 5 line 8-12)
wherein the second p-type region (33) is a p-type metal contact (metallization layer 33, forms Schottky diode with n-type 30/31, thus is p-type);
wherein a lower surface of the p-type metal contact facing the substrate contacts and extends along an upper surface of the N well (30/31).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Tseng by having the second p-type region is a p-type metal contact and a lower surface of the p-type metal contact facing the substrate contacts and extends along an upper surface of the N well, as taught by Claverie, in order to simplify manufacturing methods by eliminating one masking and doping step (see col. 5 lines 16-17). Furthermore, Claverie shows that a p-type metal contact is an equivalent structure known in the art to the implanted p-type region. Therefore, because these two were art-recognized equivalents at the time the invention was made, one of ordinary skill in the art would have found it obvious to substitute the metal contact of Claverie for the p-type well of Schneider and Chiozzi.
Claims 12-13, 21, 23-24, and 29 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Tseng in view of Schneider, Chiozzi and Claverie.
Regarding claims 12 and 13, Tseng in view of Schneider, Chiozzi and Claverie substantially teaches the claimed invention in the same manner and for the same reasons as applied to claims 1 and 2 above.
Note that “the second P well is a single p-type well” is taught because the combined device shows a second p-type which is, e.g., “distinct from other things,” or “something forming one individual unit” (see Collins English Dictionary) or “consisting of only one in number,” (see Merriam-Webster Dictionary.
Regarding claim 21, the combined device shows the N well (Tseng: 502/514) physically contacts and extends along a first portion of a bottommost surface of the second isolation region (Tseng: FOX between 512 and 514), wherein the second P well (Schneider: 44; Tseng: substrate p-type region 500 and 506) physically contacts and extends along a second portion of the bottommost surface of the first isolation region and a second portion of the bottommost surface of the second isolation region.
Regarding claim 23, Tseng further discloses wherein the bottommost surface of the first isolation region and the bottommost surface of the second isolation region extend deeper into the substrate than a bottommost surface of the n-type region and a bottommost surface of the p-type region (note that one can choose portions of 512 and 510 to read on the “regions” such that the claimed limitation is met; note that the broadest reasonable “region” is interpreted as a continuous part of a surface, space or body).
Regarding claim 24, Tseng further discloses wherein a bottommost surface of the N well (502/514) extends deeper into the substrate than the bottommost surface of the first isolation region and the bottommost surface of the second isolation region (FOX regions).
Regarding claim 29, the combined device shows wherein an anode of the diode is coupled to electrical ground, and a cathode of the diode is coupled to the emitter (see Chiozzi).
Additionally, note that is it is the Office' s position that the limitation “an anode of the diode is coupled to electrical ground” is directed to a method of using the device and that because the combined device has all of the structural limitations of the claimed invention the device is capable of being operated in the manner claimed by the applicant. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114.II and 2112.01.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-3, 12, 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-3, 10 and 18 of U.S. Patent No. 11,282,830 in view of Tseng.
Regarding claim 1, the claims of the instant application are substantially taught by claim 1 of ‘830. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘830 recite additional features and more specific limitations than those of the instant application. Any additional limitations are taught by Tseng in the same manner as outlined above.
Regarding claims 2 and 3, the claims of the instant application are further substantially taught by claims 2 and 3 of ‘830.
Regarding claims 12, the claims of the instant application are substantially taught by claim 1 of ‘830. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘830 recite additional features and more specific limitations than those of the instant application.
Regarding claims 13, the claims of the instant application are further substantially taught by claims 2 and 3 of ‘830.
Regarding claim 12, the claims of the instant application are substantially taught by claims 10 and 18 of ‘830. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of ‘830 recite additional features and more specific limitations than those of the instant application.
Regarding claims 13, the claims of the instant application are further substantially taught by claim 12 of ‘830.
Response to Arguments
Applicant's arguments filed 4/2/2026 have been fully considered but are not persuasive.
Applicant argues (page 9) that the combined references do not teach or suggest the claimed invention because the Office Action’s assertions are “based on a single sentence of Chiozzi” reciting “[d]ual considerations are, however, applicable if the N type regions are replaced by corresponding P type regions and vice versa,” which applicant contends is unclear.
The examiner disagrees. Specifically, the teachings of Chiozzi are not based on this single sentence. Rather, Chiozzi is relied upon to teach a PN junction (275) connected in series with the transistor, explicitly shown in Fig. 2. Further, the portion of Chiozzi cited by applicant is relied upon for the explicit teaching that the structure of Fig. 2 could have opposite doping types (i.e. “the N type regions are replaced by corresponding P type regions and vice versa”). Aside from possibly the term “[d]ual considerations,” on which the examiner does not specifically rely, nothing about this teaching is unclear.
Applicant argues (pages 9-10) that the examiners “asserted dual circuit…contains errors.” Applicant further provides two circuit diagrams which applicant argues representative of the teachings of Chiozzi and that the rejections “implicitly relied on a dual circuit shown in,” the first figure (Fig. A), and argues that various aspects of the Office action as they relate to these figures are incorrect.
In response, the examiner disagrees. It is first noted that the rejection does not rely upon or address any aspect of biasing the device, implicitly or otherwise. Nor does the rejection rely upon a “dual circuit,” which is not found anywhere in the previous Office action. It is unclear what applicant intends by “dual circuit,” and its repeated appears to be an attempt at employing the term “dual consideration” in such a fashion as to make the teaching of Chiozzi cited above appear unclear or confusing.
The rejection of claims, rather, is based on the fact that the combined references teach all of the structural limitations of the claim, which is all the prior art needs to teach for the given product claims (see MPEP 2114.II and 2112.01). The biasing of the device is a matter directed to a method of using the device and is not germane to the patentability of the product claims.
Additionally, applicant’s attempts to invalidate the combination of references amount to an attempt to bodily incorporate Chiozzi into Tseng. However, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In the instant case, as explicitly taught by Chiozzi, Zener diodes are known to be able to be used in semiconductor devices as voltage limiters and/or references (see col. 4 lines 11-17) and the structure of Chiozzi provides such a Zener diode in series with an emitter of a bipolar transistor for low series resistance and good reliability (see Chiozzi col. 2 lines 18-22).
It is also noted that neither of applicant’s figures are correct for the relied upon embodiment, nor is the cited portion of Chiozzi relating to biasing of the device. Applicant has repeated relied upon a circuit diagram which represent the structure and polarities of Fig. 2 despite the explicit recitation in the Office action that the rejection is based upon the embodiment where the polarities are reversed. Further, the portion of Chiozzi which relies upon to argue that the improper combination of Chiozzi and Tseng is only for the embodiment which is not relied upon in the rejection. Rather, the circuit diagram of the embodiment relied upon in the reject is shown below.
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The disclosure of Chiozzi is silent as to the biasing of this embodiment. One of ordinary skill, however, would readily recognize, at the very least, that if one were to supply Isupply at pad 260 for this embodiment, as applicant contends is taught by Chiozzi, the diode would be impotent as the current would merely flow through the diode at all times. As applicant’s arguments do not address the embodiment relied upon, the arguments are understood to be moot.
Applicant argues (page 10-12) that Tseng does not teach or suggest the biasing can be reversed.
In response, the examiner again notes that the rejection of claims is based on the fact that the combined references teach all of the structural limitations of the claim, which is all the prior art needs to teach for the given product claims (see MPEP 2114.II and 2112.01). The biasing of the device is a matter directed to a method of using the device and is not germane to the patentability of the product claims.
Applicant argues (pages 12-14) that Tsend and Chiozzi would not be combined because of “fundamental contradiction in purpose, operational incompatibility, and contrary operating principles” and the combination “renders Tseng unsatisfactory for its intended purpose.” Specifically, Applicant argues that Tseng provides an ESD circuit which ”needs to be able to discharge a large ESD current (e.g., up to a few amps) in an extremely short period of time (e.g., a few nanoseconds),” and “needs to handle a high ESD voltages (e.g., up to hundreds of volts or even thousands of volts)” whereas Chiozzi is a “voltage reference circuit” which “[t]ypically…are designed to maintain stability and accuracy of a reference voltage (e.g., a few volts) with slow variations and a low, steady electrical current (e.g., microamps to milliamps),” teaches a component which “may not be able to withstand the harsh conditions…of an ESD event.”
In response, the examiner disagrees. Specifically, it is noted that arguments by applicant cannot take the place of evidence (see MPEP 716.01(c)). Applicant’s arguments amount to a mere assertion that Zener diodes are unsuitable for use in ESD circuits and the Zener diode of Chiozzi is applicable to “voltage reference” circuits only. Zener diodes, however, are well-known to be used in ESD circuits. This is supported by myriad references which show an ESD circuit employing a Zener diode. Some examples are as follows:
US 5343053 – see Fig. 5 and related text;
US 20090278168 – see Fig. 1C and related text;
US 20070073807 – see Fig. 4 and related text;
US 20050224836 – see Fig. 6 and related text;
US 6768176 – see Fig. 4 and related text;
US 6459139 – see Fig. 2 and related text;
US 6501632 – see Fig. 3 and related text;
US 20090315113 – see Figs. 5-6 and related text;
US 20080224179 – see Fig. 4C and related text.
Additionally, Applicant’s argument that the Zener diode of Chiozzi is applicable to a “voltage reference circuit” only are a mischaracterization. The reference recites: “[d]evices with preset reverse conduction thresholds, such as Zener diodes, are used in many different applications [sic] as voltage limiters or references. They effect a limitation of the maximum voltage which can be applied between two nodes of a circuit or maintain a node at a preset voltage value with respect to a reference voltage,” [emphasis added]. It is clear from the reference that the use of Zener diodes is not limited to these applications and that these applications are separate functions. “Voltage limiting” is a function of and related to ESD. The Zener diode in an ESD device would function by allowing low voltage surges, i.e. surges which do not present a risk to a circuit to be protected, to continue passing through the circuit, but prohibit higher voltage surges from passing through the circuit, instead allowing the surge to pass through the ESD/protection circuit. It is the position of the Office that Applicant’s attempts to dismiss the teaching of “voltage limiting” as a function which can simply be lumped in with “voltage reference” and Applicant’s assertion that “voltage limiting” has been incorrectly interpretated by the examiner are merely attempts to disregard a portion of the reference in favor of the portions which support Applicant’s position.
Lastly, it is noted that even if the speed of the ESD function is degraded by addition of a Zener diode, the court has held that ‘[a] given course of action often has simultaneous advantages and disadvantages, and this does not necessarily obviate motivation to combine.” (see MPEP 2143.01.V). An alleged disadvantage does not render the device inoperable or unsatisfactory for its intended purposed.
Applicant argues (pages 14-15) that Tseng and Chiozzi would not be combined because “the voltage reference circuit of Chiozzi, in contrast, is turned ON all the time and produces a fixed reference voltage at pad 260.”
In response, the examiner disagrees. Specifically, as addressed in detail above, Applicant is basing the arguments regarding biasing on an embodiment which is not relied upon in the rejection. Accordingly, the argument is moot.
Applicant argues (pages 15-16) that the combination of Tseng and Chiozzi is improper because “the rejection is based on modifying Tseng with the dual circuit of Chiozzi, and applying the biasing scheme of Chiozzi for the modified circuit,” which is in error.
In response, the examiner disagrees. As discussed in detail above, the rejection does not rely upon or address any aspect of biasing the device or a “dual circuit.” The rejection of claims is based on the combined structural limitations of the claim and the biasing of the device is a matter directed to a method of using the device and is not germane to the patentability of the product claims. Additionally, applicant’s arguments regarding the biasing of the device are based upon an embodiment which has not been relied upon and are therefore moot.
Applicant argues (pages 16-17) that the combination of Tseng and Chiozzi is does not provide ESD protection because Chiozzi does not have ESD protection capability and because the biasing of Tseng is incompatible with the “dual circuit of Chiozzi.”
In response, the examiner disagrees. Specifically, it is first noted that it is noted that the features upon which applicant relies (i.e., providing ESD protection) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Additionally, it is noted that one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Lastly, applicant’s arguments regarding the biasing of the device are based upon an embodiment which has not been relied upon and are therefore moot.
Applicant argues (page 17) that the combined art does not teach or suggest “the second P well is a single p-type well.”
In response, the examiner disagrees. Specifically, it is noted that, in accordance with MPEP 2111, USPTO personnel are to give claims their broadest reasonable interpretation in light of the supporting disclosure. In re Morris, 127 F.3d 1048, 1054-55, 44 USPQ2d 1023, 1027-28 (Fed. Cir. 1997).Therefore the claim limitation “single” has been given its broadest reasonable interpretation. The limitation is taught because the combined device shows a second p-type which is, e.g., “distinct from other things,” or “something forming one individual unit” (see Collins English Dictionary) or “consisting of only one in number,” (see Merriam-Webster Dictionary). The fact that the well might have been formed in two steps or may have portions of different doping concentration does not compromise this.
Applicant’s remaining arguments have been considered but are moot in view of the new grounds of rejection presented above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lauren R Bell whose telephone number is (571)272-7199. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAUREN R BELL/Primary Examiner, Art Unit 2896
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