DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 21, 2025 has been entered.
Response to Arguments
RE: the rejection of the previous claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered, however, further search and consideration prompted the new grounds of rejection presented herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 18-19, 21-26, 29-31, 39-40is/are rejected under 35 U.S.C. 103 as being unpatentable over US20200105772A1 (“Chen”) in view of US20020106816A1 (“Okuno”) further in view of US20210098595A1 (“Lee”) further in view of US20230098622A1 (“Koo”).
RE: Claim 18, Chen discloses A method for forming an integrated chip (IC in FIG. 2, [0026]; the method in FIGs. 3-13 is used to form the IC in FIG. 2, [0034]-[0035]), the method comprising:
forming a transistor device (304 in FIG. 2) along a substrate (308);
depositing a first electrode layer (802/604 in FIG. 8 becomes 104 in FIG. 13, FIG. 2) comprising a first conductive material over the transistor device (802 and 604 may be the same material, [0040]; 604 is a conductive body, [0038], 802 is a conductive body, [0040]);
depositing a first ferroelectric layer (804 in FIG. 8) comprising a first ferroelectric material (804 is a ferroelectric layer, [0040]);
depositing a second electrode layer (806) comprising a second conductive material (806 is an electrode layer comprising conductive material, [0040]);
depositing a hard mask layer (hard mask 808, [0040]; mask 808 in FIG. 8 becomes mask 116 in FIG. 9, [0043]) on the second electrode layer;
etching the hard mask layer and the second electrode layer with a first etching process (FIG. 9 shows the hard mask 808 and the second electrode 806 are etched, [0042]);
depositing a spacer layer (1002 in FIG. 10) directly on a sidewall of the second electrode layer; and
etching the first electrode layer, the first ferroelectric layer, , and the spacer layer with a second etching process (FIG. 11 shows 802, 804, 1002 are etched with a second etching process).
Chen does not explicitly disclose:
the first electrode layer having a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall;
depositing a first barrier layer comprising a first barrier material, different from the first conductive material, on the first electrode layer;
depositing the first ferroelectric layer comprising the first ferroelectric material, on the first barrier layer, the first ferroelectric material different from the first barrier material, wherein a bandgap energy of the first ferroelectric layer is less than a bandgap energy of the first barrier layer;
depositing a second barrier layer comprising a second barrier material, different from the first ferroelectric material, on the first ferroelectric layer, wherein a bandgap energy of the second barrier layer is greater than the bandgap energy of the first ferroelectric layer;
depositing a second ferroelectric layer comprising a second ferroelectric material, different from the first barrier material and the second barrier material, on the second barrier layer, wherein a bandgap energy of the second ferroelectric layer is less than the bandgap energy of the second barrier layer;
depositing a third barrier layer comprising a third barrier material, different from the first ferroelectric material and the second ferroelectric material, on the second ferroelectric layer, wherein a bandgap energy of the third barrier layer is greater than the bandgap energy of the second ferroelectric layer;
depositing the second electrode layer comprising the second conductive material, on the third barrier layer, the second conductive material different from the third barrier material;
depositing the hard mask layer between the first and second sidewalls of the first electrode layer;
depositing a spacer layer directly on an upper surface of the third barrier layer; and
etching the first barrier layer, the second barrier layer, the second ferroelectric layer, the third barrier layer, with a second etching process.
In the same field of endeavor, Okuno discloses a concaved capacitor, [0035] with a recess 14 a in the second interlayer insulating film 14, [0037].
Okuno further discloses a first lower platinum film 15 a is formed by sputtering on the second interlayer insulating film 14 and the walls and the bottom of the recess 14, [0038], FIG. 1C, 2A.
Okuno further discloses that 15A serves as a lower electrode and 18A is the upper electrode, [0064].
Okuno further discloses since the lower conducting film included in the conducting film to be formed into the lower electrode is formed by the sputtering, the conducting film to be formed into the lower electrode is improved in its morphology, which improves the quality of the capacitor dielectric film formed on the conducting film, [0016].
In FIG. 4A, the resist 19, serving as a mask, is between sidewalls of the lower electrode 15A, sidewalls of the upper electrode 18A, and sidewalls of the capacitor dielectric film 17A, [0064].
In FIG. 4B, the layers 15A, 17A, 18A of the capacitor in FIG. 4B each have a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen by forming a recess in the conductive body layer 604, 802 in FIG. 8 as taught by Okuno in order to increase the effective area of the capacitor, thereby increasing its capacitance.
As a result, the layers 808, 806, 804 in Chen FIG. 8 would be deposited in the recess of 640, 802 as shown in FIG. 4A of Okuno.
In the same field of endeavor, Lee discloses in FIG. 1 a ferroelectric thin-film structure 200, [0052], including at least one first atomic layer 210, at least one second atomic layer 220, and a third atomic layer 230, [0054].
Lee discloses The first dielectric material 211 may include, for example, an oxide of at least one of aluminum (Al), [0056].
Lee discloses The second dielectric material 221 may include, for example, an oxide of at least one of hafnium (Hf), [0058].
Lee further discloses the third atomic layer 230 including the first dielectric material 211 and the dopant 231 that has a greater bandgap than that of the first dielectric material 211, is provided on the first atomic layer 210 including the first dielectric material 211 and the second atomic layer 220 including the second dielectric material 221, wherein each of the first dielectric material 211 and the second dielectric material 221 are based on an oxide, and the dopant 231 included in the third atomic layer 230 may improve ferroelectric and electrical properties, [0065].
Lee further discloses in FIG. 12 a capacitor 1300, [0124], with a layer 1340 between a top electrode 1320 and a lower electrode 1310, [0125]. The layer 1340 is the ferroelectric thin- film structure 200, [0126].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute depositing the ferroelectric layer 804 on the conductive body 802 with depositing the ferroelectric thin- film structure 200 as taught by Lee as both are ferroelectric structures used for capacitors and the results of the substitution would have been predictable, see MPEP 2143, and further it would result in improved ferroelectric properties of the structure.
In the same field of endeavor, Koo discloses that the ferroelectric layer 120 may include hafnium oxide, [0049] and The first barrier insulation layer 201 may include, for example, aluminum oxide, [0072] and the first barrier insulation layer 201 may have a band gap energy that is greater than that of the ferroelectric layer 120, [0071].
Accordingly, as Koo teaches that the first barrier insulation layer 201 has a greater band gap energy than that of the ferroelectric layer 120, the ferroelectric layer 120 includes hafnium oxide and the first barrier insulation layer includes aluminum oxide, it is considered inherent that aluminum oxide in 210, 211 would have a greater bandgap energy than that of hafnium oxide in 220, 221. As Lee teaches the third atomic layer 230 including the first dielectric material 211 and the dopant 231 that has a greater bandgap than that of the first dielectric material 211, [0065], 230 would have a bandgap larger than that of 210, 211 and therefore 220, 221.
Alternatively, it would have been obvious to modify 210, 211 and 230 to have a larger bandgap than that of the hafnium oxide of 220, 221 as taught by Koo in order to reduce the leakage current of the ferroelectric structure as taught by Koo in [0090].
Chen as modified by Okuno, Lee, Koo would therefore disclose:
the first electrode layer having a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall (Chen’s 604, 802 would include a recess as shown for 15A in FIG. 4A of Okuno; Accordingly, 604, 802 would include a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall);
depositing a first barrier layer (From Lee: second 210 from the bottom in FIG. 1) comprising a first barrier material (As modified, 210 includes dielectric material 211 which is aluminum oxide; Koo identifies aluminum oxide as barrier material, [0072]), different from the first conductive material, on the first electrode layer;
depositing a first ferroelectric layer (second 220 from the bottom in FIG. 1 of Lee) comprising a first ferroelectric material (As modified, 220 includes dielectric material 221 which is hafnium oxide; Lee discloses 200 is ferroelectric, [0054]; Koo identifies hafnium oxide as ferroelectric material, [0049]; Accordingly, hafnium oxide in 200 would be ferroelectric), different from the first barrier material, on the first barrier layer, wherein a bandgap energy of the first ferroelectric layer is less than a bandgap energy of the first barrier layer (As modified the bandgap of 220 is less than the bandgap of 210);
depositing a second barrier layer (third 210 from bottom in FIG. 1 of Lee) comprising a second barrier material, different from the first ferroelectric material, on the first ferroelectric layer, wherein a bandgap energy of the second barrier layer is greater than the bandgap energy of the first ferroelectric layer (As modified the bandgap of 220 is less than the bandgap of 210);
depositing a second ferroelectric layer (third 220 from bottom in FIG. 1 of Lee) comprising a second ferroelectric material, different from the first barrier material and the second barrier material, on the second barrier layer, wherein a bandgap energy of the second ferroelectric layer is less than the bandgap energy of the second barrier layer (As modified the bandgap of 220 is less than the bandgap of 210);
depositing a third barrier layer (230 from FIG. 1 of Lee) comprising a third barrier material, different from the first ferroelectric material and the second ferroelectric material, on the second ferroelectric layer, wherein a bandgap energy of the third barrier layer is greater than the bandgap energy of the second ferroelectric layer (As modified, 230 has a larger bandgap than 220);
depositing a second electrode layer (From Chen FIG. 8: 806) comprising a second conductive material, different from the third barrier material, on the third barrier layer;
depositing a hard mask layer (From Chen: 808, [0040]) on the second electrode layer and between the first and second sidewalls of the first electrode layer (Chen’s 808 would have the configuration of the mask 19 in Okuno’s FIG. 4A which is on the second electrode layer 18A and between the first and second sidewalls of the lower electrode layer 15A; Accordingly, Chen’s 808 would be on the second electrode layer 806 and between the first and second sidewalls of the first lower electrode layer 802, 604);
etching the hard mask layer and the second electrode layer with a first etching process (Chen FIG. 9 shows the hard mask 808 and the second electrode 806 are etched to form hard mask 116 and second electrode 114, [0042]-[0043]);
depositing a spacer layer (Chen FIG. 10: 1002 is directly deposited on an upper surface of Chen’s ferroelectric 804 and sidewall of Chen’s upper electrode 114; As modified, 1002 would be deposited directly on an upper surface of the uppermost layer of Lee’s 200 which is Lee’s 230) directly on an upper surface of the third barrier layer and a sidewall of the second electrode layer; and
etching the first electrode layer, the first barrier layer, the first ferroelectric layer, the second barrier layer, the second ferroelectric layer, the third barrier layer, and the spacer layer with a second etching process (Chen FIG. 11 shows 802, 804, 1002 are etched with a second etching process; As modified, 804 would be substituted with Lee’s 200 which includes the layers of 210, 220, 230 corresponding to the first barrier layer, the first ferroelectric layer, the second barrier layer, the second ferroelectric layer, the third barrier layer; therefore these layers would be etched in the second etching process).
RE: Claim 19, Chen in view of Okuno, Lee, Koo discloses The method of claim 18, wherein the etching of the second electrode layer stops on the third barrier layer (In Chen FIGs. 8-9 show etching stopping on a sidewall of 804; As modified, Chen’s 804 would be substituted with Lee’s 200 and therefore etching would stop on a sidewall of Lee’s 230), and wherein the spacer layer is deposited directly on an upper surface and a sidewall of the hard mask layer (Chen FIG. 10 shows 1002 deposited directly on an upper surface and sidewall of hard mask 116 which is formed from Chen’s 808, [0043]).
RE: Claim 21, Chen in view of Okuno, Lee, Koo discloses The method of claim 18, further comprising:
forming a first metal interconnect (106be in Chen FIGs. 2, 3; note for compactness, lower portion of IC in FIG. 2 is omitted in FIGs. 3-13, [0035]; Accordingly, the process of FIG. 3 is performed with the lower portion of IC in FIG. 2 though this is not shown for compactness) over and coupled to the transistor device;
depositing a lower layer (124 in Chen FIG. 4) over the first metal interconnect;
etching the lower layer to form an opening in the lower layer to uncover the first metal interconnect (Chen FIG. 5 shows 124 was etched to form an opening 502 to uncover 106be, [0037]); and
depositing a diffusion barrier layer (Chen FIG. 6: 602) on an upper surface of the lower layer, on an upper surface of the first metal interconnect, and along sidewalls of the lower layer (Chen FIG. 6 shows 602 was deposited on an upper surface of the 124, on an upper surface of 106be, and along sidewalls of the 124; 602 is a conductive barrier material such as tantalum nitride or titanium nitride, [0038]),
wherein the first electrode layer is deposited on a first upper surface of the diffusion barrier layer, on a second upper surface of the diffusion barrier layer, and along sidewalls of the diffusion barrier layer (Chen FIG. 6 shows 604 deposited on a first upper surface of the 602, on a second upper surface of 602, and along sidewalls of 602), and
wherein the first barrier layer is deposited on a first upper surface of the first electrode layer, on a second upper surface of the first electrode layer, and along sidewalls of the first electrode layer (As modified, Chen’s 804 would be substituted with Lee’s ferroelectric film 200; Lee’s ferroelectric 200 would have the configuration of the capacitor dielectric film 17A in Okuno FIG. 4A which is deposited on a first upper surface of the first electrode layer 15A, on a second upper surface of the first electrode layer 15A, and along sidewalls of the first electrode layer 15A).
RE: Claim 22, Chen in view of Okuno, Lee, Koo discloses The method of claim 19, wherein the spacer layer is deposited directly on a sidewall of the hard mask layer (Chen FIG. 10 shows 1002 deposited directly on sidewall of 116), and wherein the spacer layer remains directly on the sidewall of the hard mask layer, the sidewall of the second electrode layer, and the upper surface of the third barrier layer after the etching of the spacer layer (FIGs. 12-13 shows 1002 remains directly on sidewall of 116, on sidewall of 114 and upper surface of ferroelectric structure 112 which would correspond to the upper surface of Lee’s 200 which is Lee’s 230).
RE: Claim 23, Chen in view of Okuno, Lee, Koo discloses The method of claim 19, further comprising:
depositing an etch stop layer (Chen FIG. 12: 128) directly on the hard mask layer, the spacer layer, the third barrier layer, the second ferroelectric layer, the second barrier layer, the first ferroelectric layer, the first barrier layer, and the first electrode layer (Chen FIG. 12 shows 128 deposited directly on 116, 118, the sidewall of ferroelectric 112, and 104; 128 serves as an etch stop, [0023]; 1002 becomes 118 after etching, [0045]; Chen’s ferroelectric 112 would be substituted with Lee’s 200; therefore, 128 would be formed directly on the side of each layer of Lee’s 200);
depositing a buffer layer (Chen FIG. 12: 130) over the etch stop layer;
depositing a second dielectric layer (Chen FIG. 12: 126) over the buffer layer; and
forming a second metal interconnect (Chen FIG. 13: 120te, 106te; 120te and 106te are the same material, [0024]; 120te are vias, 106te are metal wires, [0047]; vias and metal wires are copper, aluminum, [0047]) over the buffer layer and extending through the second dielectric layer, the buffer layer, the etch stop layer, and the hard mask layer to the second electrode layer.
RE: Claim 24, Chen in view of Okuno, Lee, Koo discloses The method of claim 18, wherein a thickness of the first ferroelectric layer and a thickness of the second ferroelectric layer are greater than a thickness of the first barrier layer, greater than a thickness of the second barrier layer, and greater than a thickness of the third barrier layer (Koo discloses The ferroelectric layer 120 may have a thickness of, for example, 1 nanometer (nm) to 4 nanometers (nm), [0050] and Each of the first dielectric layer 131 and the second dielectric layer 132 may have a thickness of, for example, 5 angstroms (Å) to 20 angstroms (Å), [0051] and The thickness of the first barrier insulation layer 201 may be equal to or less than the thickness of the first dielectric layer 131, [0072]. Accordingly, before the effective filing date of the claimed invention, there was a need to select thicknesses for each layer in Lee’s 200; It would have been obvious to make the thickness of each ferroelectric layer 220 from Lee have a thickness of 4nm as this would have been obvious to try since 4nm is one solution for the thickness of a ferroelectric layer identified by Koo and this would have had a reasonable expectation of success, see MPEP 2143; It would have been further obvious to make the thickness of each 210, 230 equal to 5 Angstroms as 5 Angstroms is one solution for a thickness of a barrier layer material and this would have had a reasonable expectation of success, see MPEP 2143; As 5 Angstroms is equal to 0.5nm, the thickness of each 220 would be greater than a thickness of each 210, 230; Alternatively or additionally, it would have been obvious to one of ordinary skill in the art at the time the invention was made to make each 220 have a larger thickness than that of each 210, 230, since it has been held by the courts that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device, see MPEP 2144.04).
RE: Claim 39, Chen in view of Okuno, Lee, Koo discloses The method of claim 18, wherein the first barrier layer, the first ferroelectric layer, the second barrier layer, the second ferroelectric layer, the third barrier layer, and the second electrode layer are deposited between the first and second sidewalls of the first electrode layer (As modified, Chen’s 804 would be substituted with Lee’s ferroelectric film 200; Lee’s ferroelectric 200 would have the configuration of the capacitor dielectric 17A in Okuno FIG. 4A; In Okuno, the top electrode 18A, the capacitor dielectric 17A, and the mask 19 are deposited between first and second sidewalls of the lower electrode 15A; Accordingly, each layer of Lee’s ferroelectric 200 would be deposited between the first and second sidewalls of Chen’s lower electrode 604, 802 in FIG. 8).
RE: Claim 25, Chen discloses A method for forming an integrated chip (IC in FIG. 2, [0026]; the method in FIGs. 3-13 is used to form the IC in FIG. 2, [0034]-[0035]), the method comprising:
depositing a first electrode layer (802/604 in FIG. 8 becomes 104 in FIG. 13, FIG. 2) over a substrate (308 in FIG. 2 or 106be in FIG. 8);
depositing a first ferroelectric layer (804 in FIG. 8);
depositing a second electrode layer (806);
depositing a hard mask layer (hard mask 808, [0040]; mask 808 in FIG. 8 becomes mask 116 in FIG. 9, [0043]) on a first upper surface of the second electrode layer; and
etching the second electrode layer and the hard mask layer (FIG. 9 shows the hard mask 808 and the second electrode 806 are etched, [0042]).
Chen does not explicitly disclose:
depositing a first barrier layer over the first electrode layer;
depositing the first ferroelectric layer over the first barrier layer, wherein a bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer;
depositing a second barrier layer over the first ferroelectric layer;
depositing a second ferroelectric layer over the second barrier layer;
depositing a third barrier layer directly on the second ferroelectric layer;
depositing the second electrode layer directly on a first upper surface, a second upper surface, and a third upper surface of the third barrier layer;
depositing the hard mask layer on a first upper surface and a second upper surface of the second electrode layer, between the first and second upper surfaces of the second electrode layer, and between the first and second upper surfaces of the third barrier layer.
In the same field of endeavor, Okuno discloses a concaved capacitor, [0035] with a recess 14 a in the second interlayer insulating film 14, [0037].
Okuno further discloses a first lower platinum film 15 a is formed by sputtering on the second interlayer insulating film 14 and the walls and the bottom of the recess 14, [0038], FIG. 1C, 2A.
Okuno further discloses that 15A serves as a lower electrode and 18A is the upper electrode, [0064].
Okuno further discloses since the lower conducting film included in the conducting film to be formed into the lower electrode is formed by the sputtering, the conducting film to be formed into the lower electrode is improved in its morphology, which improves the quality of the capacitor dielectric film formed on the conducting film, [0016].
In FIG. 4A, the resist 19, serving as a mask, is between sidewalls of the lower electrode 15A, sidewalls of the upper electrode 18A, and sidewalls of the capacitor dielectric film 17A, [0064].
In FIG. 4B, the layers 15A, 17A, 18A of the capacitor in FIG. 4B each have a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen by forming a recess in the conductive body layer 604, 802 in FIG. 8 as taught by Okuno in order to increase the effective area of the capacitor, thereby increasing its capacitance.
As a result, the layers 808, 806, 804 in Chen FIG. 8 would be deposited in the recess of 640, 802 as shown in FIG. 4A of Okuno.
In the same field of endeavor, Lee discloses in FIG. 1 a ferroelectric thin-film structure 200, [0052], including at least one first atomic layer 210, at least one second atomic layer 220, and a third atomic layer 230, [0054].
Lee discloses The first dielectric material 211 may include, for example, an oxide of at least one of aluminum (Al), [0056].
Lee discloses The second dielectric material 221 may include, for example, an oxide of at least one of hafnium (Hf), [0058].
Lee further discloses the third atomic layer 230 including the first dielectric material 211 and the dopant 231 that has a greater bandgap than that of the first dielectric material 211, is provided on the first atomic layer 210 including the first dielectric material 211 and the second atomic layer 220 including the second dielectric material 221, wherein each of the first dielectric material 211 and the second dielectric material 221 are based on an oxide, and the dopant 231 included in the third atomic layer 230 may improve ferroelectric and electrical properties, [0065].
Lee further discloses in FIG. 12 a capacitor 1300, [0124], with a layer 1340 between a top electrode 1320 and a lower electrode 1310, [0125]. The layer 1340 is the ferroelectric thin- film structure 200, [0126].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute depositing the ferroelectric layer 804 on the conductive body 802 with depositing the ferroelectric thin- film structure 200 as taught by Lee as both are ferroelectric structures used for capacitors and the results of the substitution would have been predictable, see MPEP 2143, and further it would result in improved ferroelectric properties of the structure.
In the same field of endeavor, Koo discloses that the ferroelectric layer 120 may include hafnium oxide, [0049] and The first barrier insulation layer 201 may include, for example, aluminum oxide, [0072] and the first barrier insulation layer 201 may have a band gap energy that is greater than that of the ferroelectric layer 120, [0071].
Accordingly, as Koo teaches that the first barrier insulation layer 201 has a greater band gap energy than that of the ferroelectric layer 120, the ferroelectric layer 120 includes hafnium oxide and the first barrier insulation layer includes aluminum oxide, it is considered inherent that aluminum oxide in 210, 211 would have a greater bandgap energy than that of hafnium oxide in 220, 221. As Lee teaches the third atomic layer 230 including the first dielectric material 211 and the dopant 231 that has a greater bandgap than that of the first dielectric material 211, [0065], 230 would have a bandgap larger than that of 210, 211 and therefore 220, 221.
Alternatively, it would have been obvious to modify 210, 211 and 230 to have a larger bandgap than that of the hafnium oxide of 220, 221 as taught by Koo in order to reduce the leakage current of the ferroelectric structure as taught by Koo in [0090].
Chen as modified by Okuno, Lee, Koo would therefore disclose:
depositing a first barrier layer (From Lee: second 210 from the bottom in FIG. 1; As modified, 210 includes dielectric material 211 which is aluminum oxide; Koo identifies aluminum oxide as barrier material, [0072]) over the first electrode layer;
depositing the first ferroelectric layer (second 220 from the bottom in FIG. 1 of Lee; As modified, 220 includes dielectric material 221 which is hafnium oxide; Lee discloses 200 is ferroelectric, [0054]; Koo identifies hafnium oxide as ferroelectric material, [0049]; Accordingly, hafnium oxide in 200 would be ferroelectric) over the first barrier layer, wherein a bandgap energy of the first barrier layer is greater than a bandgap energy of the first ferroelectric layer (As modified the bandgap of 220 is less than the bandgap of 210);
depositing a second barrier layer (third 210 from bottom in FIG. 1 of Lee) over the first ferroelectric layer;
depositing a second ferroelectric layer (third 220 from bottom in FIG. 1 of Lee) over the second barrier layer;
depositing a third barrier layer (230 from FIG. 1 of Lee) directly on the second ferroelectric layer;
depositing the second electrode layer directly on a first upper surface, a second upper surface, and a third upper surface of the third barrier layer (As modified, Chen’s 804 would be substituted with Lee’s ferroelectric film 200; Chen’s top electrode 806 and Lee’s ferroelectric 200 would have the configuration of Okuno’s top electrode 18A and dielectric film 17A in FIG. 4A; Accordingly, as Okuno’s top electrode 18A is deposited directly on a first upper surface, a second upper surface, and a third upper surface of the dielectric 17A in FIG. 4A Okuno, Chen’s top electrode 806 in FIG. 8 would deposited on a first upper surface, a second upper surface, and a third upper surface of the third barrier layer in Lee’s 230 from FIG. 1; Lee’s 230 is the uppermost layer in Lee’s 200);
depositing the hard mask layer on a first upper surface and a second upper surface of the second electrode layer, between the first and second upper surfaces of the second electrode layer, and between the first and second upper surfaces of the third barrier layer (As modified, Chen’s hard mask 808 would have the configuration of Okuno’s mask 19 in FIG. 4A, Chen’s second electrode 806 would have the configuration of Okuno’s top electrode 18A in FIG. 4A, Lee’s layer 230 would have the configuration of Okuno’s dielectric 17A in FIG. 4A: In Okuno, the mask 19 is shown deposited on a first upper surface and a second upper surface of the second electrode layer 18A, between the first and second upper surfaces of the second electrode layer 18A, and between the first and second uppermost surfaces of the dielectric 17A; Accordingly as modified, Chen’s hard mask 808 would be deposited on a first upper surface and a second upper surface of the Chen’s top electrode 806, between the first and second upper surfaces of Chen’s 806, and between the first and second upper surfaces of Lee’s 230).
RE: Claim 26, Chen in view of Okuno, Lee, Koo discloses The method of Claim 25,
wherein a bandgap energy of the second barrier layer is greater than the bandgap energy of the first ferroelectric layer (As modified the bandgap of 220 is less than the bandgap of 210), wherein a bandgap energy of the second barrier layer is greater than the bandgap energy of the second ferroelectric layer (As modified the bandgap of 220 is less than the bandgap of 210), and wherein a bandgap energy of the third barrier layer is greater than the bandgap energy of the second ferroelectric layer (As modified, 230 has a larger bandgap than 220).
RE: Claim 29, Chen in view of Okuno, Lee, Koo discloses The method of claim 25, further comprising:
wherein a sidewall of the hard mask layer and a sidewall of the second electrode layer are directly over an upper surface of the first ferroelectric layer, an upper surface of the first barrier layer, and an upper surface of the first electrode layer (As modified, Chen’s 804 would be substituted with Lee’s ferroelectric film 200; In FIGs. 10-11 Chen, a sidewall of hard mask layer 116 and a sidewall of the second electrode layer 114 are directly over an upper surface of the ferroelectric 804/112; Accordingly, a sidewall of hard mask layer 116 and a sidewall of the second electrode layer 114 would be directly over an upper surface of each layer of Lee’s 200; Note Chen’s hard mask 808 becomes 116 in FIG. 9; Chen’s top electrode 806 becomes 114 in FIG. 9;), and wherein an upper surface of the third barrier layer extends laterally from a bottom of the sidewall of the second electrode layer to a top of a sidewall of the third barrier layer (Lee’s 230 is the uppermost layer in Lee’s 200; Accordingly, Chen’s upper electrode 114 would be directly on Lee’s 230 and Lee’s 230 would therefore extend laterally from a bottom of the sidewall of Chen’s 114 to a top of a sidewall of Lee’s 230).
RE: Claim 30, Chen in view of Okuno, Lee, Koo discloses The method of claim 25, wherein the first barrier layer is deposited on a first upper surface of the first electrode layer, on a second upper surface of the first electrode layer, on a third upper surface of the first electrode layer, and along a pair of sidewalls of the first electrode layer (As modified, Chen’s 804 would be substituted with Lee’s ferroelectric film 200; Lee’s ferroelectric 200 would have the configuration of the capacitor dielectric film 17A in Okuno FIG. 4A, and therefore each layer of Lee’s 200 would have a first upper surface, a second upper surface, a third upper surface, and a pair of sidewalls, and further each layer of Lee’s 200 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of a layer underneath the each layer; In FIG. 4a Okuno, the dielectric 17A is deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of the lower electrode 15A; Accordingly, Lee’s second 210 from the bottom in Lee’s FIG. 1 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of Chen’s lower electrode 802/604), and
wherein the first ferroelectric layer is deposited on a first upper surface of the first barrier layer, on a second upper surface of the first barrier layer, on a third upper surface of the first barrier layer, and along a pair of sidewalls of the first barrier layer (As modified, Lee’s second 220 from the bottom in Lee’s FIG. 1 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of Lee’s second 210 from the bottom in Lee’s FIG. 1),
wherein the second barrier layer is deposited on a first upper surface of the first ferroelectric layer, on a second upper surface of the first ferroelectric layer, on a third upper surface of the first ferroelectric layer, and along a pair of sidewalls of the first ferroelectric layer (As modified, Lee’s third 210 from the bottom in Lee’s FIG. 1 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of Lee’s second 220 from the bottom in Lee’s FIG. 1),
wherein the second ferroelectric layer is deposited on a first upper surface of the second barrier layer, on a second upper surface of the second barrier layer, on a third upper surface of the second barrier layer, and along a pair of sidewalls of the second barrier layer (As modified, Lee’s third 220 from the bottom in Lee’s FIG. 1 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of Lee’s third 210 from the bottom in Lee’s FIG. 1), and
wherein the third barrier layer is deposited on a first upper surface of the second ferroelectric layer, on a second upper surface of the second ferroelectric layer, on a third upper surface of the second ferroelectric layer, and along a pair of sidewalls of the second ferroelectric layer (As modified, Lee’s 230 in Lee’s FIG. 1 would be deposited on a first upper surface, on a second upper surface, on a third upper surface, and along a pair of sidewalls of Lee’s third 220 from the bottom in Lee’s FIG. 1).
RE: Claim 31, Chen in view of Okuno, Lee, Koo discloses The method of claim 25, wherein the first barrier layer, the second barrier layer, and the third barrier layer are amorphous (Koo teaches the first barrier insulation layer 201 may have an amorphous structure, [0072]; Accordingly, before the effective filing date of the claimed invention, there was a need to determine if each barrier layer 210, 230 would be amorphous. It would have been obvious to one of ordinary skill in the art to deposit each barrier layer, i.e., Lee’s 210, 230 as an amorphous structure as this would have been obvious to try since an amorphous structure is one solution for the structure of a dielectric barrier layer in a capacitor identified by Koo and this would have had a reasonable expectation of success, see MPEP 2143).
RE: Claim 40, Chen in view of Okuno, Lee, Koo discloses The method of claim 25, further comprising:
etching the third barrier layer, the second ferroelectric layer, the second barrier layer, the first ferroelectric layer, the first barrier layer, and the first electrode layer after etching the second electrode layer and the hard mask layer (Chen FIG. 11 shows 802, 804, 1002 are etched with a second etching process after Chen’s hard mask 808 and top electrode 806 were etched in FIG. 9 in a first etching process; As modified, 804 would be substituted with Lee’s 200 which includes the layers of 210, 220, 230 corresponding to the first barrier layer, the first ferroelectric layer, the second barrier layer, the second ferroelectric layer, the third barrier layer; therefore these layers would be etched in the second etching process after the first etching process shown in Chen FIGs. 8-9).
Claims 41-42 is/are rejected under 35 U.S.C. 103 as being unpatentable over Okuno, in view of Lee, further in view of Koo as applied to claim 25, further in view of US 20170365656 A1 (“Zelner”).
RE: Claim 41, Chen in view of Okuno, Lee, Koo discloses The method of claim 25, wherein the first barrier layer comprises a first amorphous material, wherein the second barrier layer comprises a second amorphous material, and wherein the third barrier layer comprises a third amorphous material (Koo teaches the first barrier insulation layer 201 may have an amorphous structure, [0072]; The first barrier insulation layer 201 may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more thereof, [0072]. Accordingly, before the effective filing date of the claimed invention, there was a need to determine if each barrier layer 210, 230 would be amorphous. It would have been obvious to one of ordinary skill in the art to deposit each barrier layer, i.e., Lee’s 210, 230 as an amorphous structure as this would have been obvious to try since an amorphous structure is one solution for the structure of a dielectric barrier layer in a capacitor identified by Koo and this would have had a reasonable expectation of success, see MPEP 2143).
Chen in view of Okuno, Lee, Koo does not explicitly disclose:
the second amorphous material is different than the first amorphous material
the third amorphous material is different than the first amorphous material and the second amorphous material.
In the same field of endeavor, Zelner discloses in FIG. 1 a ferroelectric capacitor 100, [0020].
Zelner further discloses the second dielectric layers 113 can be a group of stacked dielectric layers that are formed from the same material or that are formed (in whole or in part) from different materials, [0023].
Zelner further discloses the composition of the second dielectric layers 113 can be the same or different than the composition of the first dielectric layer 112, [0024].
Accordingly, before the effective filing date of the claimed invention, there was a need to determine if Lee’s dielectric layers 210 would be the same or different.
It would have been obvious to make Lee’s dielectric layers 210 formed from different materials as taught by Zelner as this would have been obvious to try since different dielectric materials is one solution for dielectric layers in a capacitor identified by Zelner and this would have had a reasonable expectation of success, see MPEP 2143.
Further, Koo discloses in FIG. 12: an inner barrier layer 206 may form a potential barrier between the first sub ferroelectric layer 120 a and the second sub ferroelectric layer 120 b within the ferroelectric layer 1200. The band gap energy of the inner barrier layer 206 may be greater than the band gap energy of each of the first and second sub ferroelectric layers 120 a and 120 b. Accordingly, the inner barrier layer 206 may reduce the leakage current of the ferroelectric layer 1200 and increase the breakdown voltage of the ferroelectric layer 1200. The inner barrier layer 206 may include, for example, aluminum oxide, yttrium oxide, magnesium oxide, or a combination of two or more thereof, [0090].
It would have been obvious to substitute the aluminum oxide material of Lee’s second layer 210 from the bottom in Lee’s FIG. 1 (corresponding to the claimed first barrier layer) with magnesium oxide as aluminum oxide, magnesium oxide are each insulating/dielectric materials used in ferroelectric capacitors and positioned between ferroelectric layers and the results of the substitution would have been predictable, see MPEP 2143.
As a result:
the second amorphous material is different than the first amorphous material (Lee’s second 210 from the bottom in Lee’s FIG. 1 would be magnesium oxide, Lee’s third 210 from the bottom in Lee’s FIG. 1 would be aluminum oxide)
the third amorphous material is different than the first amorphous material and the second amorphous material (Lee’s 230 includes dielectric material 211 and a dopant 231; Lee discloses dielectric material 211 is aluminum oxide, [0062]; dopant 231 includes yttrium oxide; Accordingly, Lee’s 230 would be aluminum oxide doped with yttrium oxide which is different from Lee’s layers 210).
RE: Claim 42, Chen in view of Okuno, Lee, Koo, Zelner discloses The method of claim 41, wherein the first ferroelectric layer comprises a first ferroelectric material, and wherein the second ferroelectric layer comprises a second ferroelectric material different than the first ferroelectric material (Koo discloses The ferroelectric layer 1200 may include a first sub ferroelectric layer 120 a, an inner barrier layer 206 disposed on the first sub ferroelectric layer 120 a, and a second sub ferroelectric layer 120 b disposed on the inner barrier layer 206. The first sub ferroelectric layer 120 a and the second sub ferroelectric layer 120 b may be made of the same material, or may be made of different materials. The first sub ferroelectric layer 120 a and the second sub ferroelectric layer 120 b may be made of the same material as the ferroelectric layer 120, [0089].
Accordingly, before the effective filing date of the claimed invention, there was a need to determine if Lee’s ferroelectric layers 220 would be the same or different.
It would have been obvious to one of ordinary skill in the art to make the Lee’s ferroelectric layers 220 out of different materials as this would have been obvious to try since different ferroelectric materials is one solution for first and second ferroelectric materials in a capacitor identified by Koo and this would have had a reasonable expectation of success, see MPEP 2143.
Koo further discloses ferroelectric layer 120 may include hafnium oxide, hafnium zirconium oxide, or a combination thereof. In another embodiment, the ferroelectric layer 120 may include hafnium oxide doped with a dopant, hafnium zirconium oxide doped with a dopant, or a combination thereof. The dopant may stabilize the ferroelectric property of the ferroelectric layer 120. The dopant may include, for example, carbon (C), silicon (Si), [0049].
It would have been further to include a first dopant of carbon in Lee’s second 220, and a second dopant of silicon in Lee’s third 220 as taught by Koo in order to stabilize the ferroelectric property of these layers; As a result, the materials in these layers would be different).
Claims 33-36, 38 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Okuno, further in view of Lee, further in view of Koo, further in view of US20010052607A1 (“Kato”).
RE: Claim 33, Chen discloses A method for forming an integrated chip (IC in FIG. 2, [0026]; the method in FIGs. 3-13 is used to form the IC in FIG. 2, [0034]-[0035]), the method comprising:
depositing a first electrode layer (802/604 in FIG. 8 becomes 104 in FIG. 13, FIG. 2; 802 and 604 may be the same material, [0040]; 604 is a conductive body, [0038], 802 is a conductive body, [0040]) comprising a first conductive material over a substrate (308 in FIG. 2);
depositing a first ferroelectric layer (804 in FIG. 8) comprising a first ferroelectric material over the first electrode layer (804 is a ferroelectric layer, [0040]);
depositing a second electrode layer (806) comprising a second conductive material (806 is an electrode layer comprising conductive material, [0040]);
depositing a hard mask layer (hard mask 808, [0040]; mask 808 in FIG. 8 becomes mask 116 in FIG. 9, [0043]) on the second electrode layer;
etching the hard mask layer and the second electrode layer with a first etching process (FIG. 9 shows the hard mask 808 and the second electrode 806 are etched in a first etching process, [0042]); and
etching the first ferroelectric layer, and the first electrode layer with a second etching process, separate from the first etching process (FIG. 11 shows 802, 804 are etched with a second etching process separate from the first etching process).
Chen does not explicitly disclose:
depositing a first barrier layer comprising a first barrier material, different than the first ferroelectric material and the first conductive material, over the first ferroelectric layer, wherein a conduction band edge energy of the first barrier material is greater than a conduction band edge energy of the first ferroelectric material, and wherein a valence band edge energy of the first barrier material is less than a valence band edge energy of the first ferroelectric material;
depositing the second electrode layer comprising a second conductive material over the first barrier layer;
depositing the hard mask layer on a first upper surface of the second electrode layer, a second upper surface of the second electrode layer, and between a pair of sidewalls of the second electrode layer;
etching the first barrier layer with the second etching process, separate from the first etching process, wherein an upper surface of the first barrier layer extends laterally from a bottom of an outer sidewall of the second electrode layer to a top of an outer sidewall of the first barrier layer.
In the same field of endeavor, Okuno discloses a concaved capacitor, [0035] with a recess 14 a in the second interlayer insulating film 14, [0037].
Okuno further discloses a first lower platinum film 15 a is formed by sputtering on the second interlayer insulating film 14 and the walls and the bottom of the recess 14, [0038], FIG. 1C, 2A.
Okuno further discloses that 15A serves as a lower electrode and 18A is the upper electrode, [0064].
Okuno further discloses since the lower conducting film included in the conducting film to be formed into the lower electrode is formed by the sputtering, the conducting film to be formed into the lower electrode is improved in its morphology, which improves the quality of the capacitor dielectric film formed on the conducting film, [0016].
In FIG. 4A, the resist 19, serving as a mask, is between sidewalls of the lower electrode 15A, sidewalls of the upper electrode 18A, and sidewalls of the capacitor dielectric film 17A, [0064].
In FIG. 4B, the layers 15A, 17A, 18A of the capacitor in FIG. 4B each have a first upper surface, a second upper surface, a third upper surface below and between the first and second upper surfaces, a first sidewall extending from the first upper surface to the third upper surface, and a second sidewall extending from the second upper surface to the third upper surface and facing the first sidewall.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen by forming a recess in the conductive body layer 604, 802 in FIG. 8 as taught by Okuno in order to increase the effective area of the capacitor, thereby increasing its capacitance.
As a result, the layers 808, 806, 804 in Chen FIG. 8 would be deposited in the recess of 640, 802 as shown in FIG. 4A of Okuno.
In the same field of endeavor, Lee discloses in FIG. 6 a ferroelectric thin-film structure 400, [0090], including at least one first atomic layer 410, at least one second atomic layer 420, and a third atomic layer 430, [0054].
Lee discloses The first dielectric material 411 may include, for example, an oxide of at least one of aluminum (Al), [0093].
Lee discloses The second dielectric material 421 may include, for example, an oxide of at least one of hafnium (Hf), [0093].
Lee further discloses in FIG. 12 a capacitor 1300, [0124], with a layer 1340 between a top electrode 1320 and a lower electrode 1310, [0125]. The layer 1340 is the ferroelectric thin- film structure 400, [0126].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute depositing the ferroelectric layer 804 on the conductive body 802 with depositing the ferroelectric thin- film structure 400 as taught by Lee as both are ferroelectric structures used for capacitors and the results of the substitution would have been predictable, see MPEP 2143, and further it would result in improved ferroelectric properties of the structure.
In the same field of endeavor, Koo discloses that the ferroelectric layer 120 may include hafnium oxide, [0049] and The first barrier insulation layer 201 may include, for example, aluminum oxide, [0072] and the first barrier insulation layer 201 may have a band gap energy that is greater than that of the ferroelectric layer 120, [0071].
Koo further discloses the first barrier insulation layer 201 may reduce the leakage current generated at an interface between the ferroelectric layer 120, [0071].
Accordingly, as Koo teaches that the first barrier insulation layer 201 has a greater band gap energy than that of the ferroelectric layer 120, the ferroelectric layer 120 includes hafnium oxide and the first barrier insulation layer includes aluminum oxide, it is considered inherent that aluminum oxide in 410, 411 would have a greater bandgap energy than that of hafnium oxide in 420, 421, and therefore a conduction band edge energy of aluminum oxide in 410, 411 would be greater than a conduction band edge energy of hafnium oxide in 420, 421, and wherein a valence band edge energy of aluminum oxide in 410, 411 would be less than a valence band edge energy of hafnium oxide in 420, 421.Alternatively, in the same field of endeavor, Kato discloses that silicon oxide film 14 serves as a dielectric film, [0032] and Since the ferroelectric film 15 and the silicon oxide film 14 are in direct contact with each other, charge present on their interface is polarization charge, [0037].
Kato further discloses in FIG. 2A that the conduction band 23 energy of silicon oxide film 14 is larger than conduction band 22 energy of ferroelectric film 15; FIG. 2A also shows valence band energy (band energy below band 23) of the silicon oxide film 14 is lower than valence band energy (band energy below band 22) of ferroelectric film 15, [0036].
Kato further discloses in FIG. 5B that the conduction band 33 energy of silicon oxide film 5 is larger than conduction band 32 energy of ferroelectric film 6; FIG. 5B also shows valence band energy (band energy below band 33) of the silicon oxide film 5 is lower than valence band energy (band energy below band 32) of ferroelectric film 6, [0008].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute each layer 410 with a layer of silicon oxide and substitute each layer 420 with the ferroelectric film 6 or 15 of Kato to widen the bandgap energy of the layer 410 to result in each 410 having a conduction band edge energy greater than a conduction band edge energy of each 420, and wherein a valence band edge energy of each 410 is less than a valence band edge energy of each 420 as taught by Kato in order to ensure that 410 forms an adequate potential barrier to reduce leakage current.
As a result, Chen in view of Lee, Koo discloses:
depositing a first ferroelectric layer (From Lee FIG. 6, uppermost 420, i.e., third 420 from bottom) comprising a first ferroelectric material over the first electrode layer (As modified, Lee’s third 420 would be deposited over Chen’s 802/604);
depositing a first barrier layer (From Lee FIG. 6: uppermost 410) comprising a first barrier material, different than the first ferroelectric material and the first conductive material, over the first ferroelectric layer, wherein a conduction band edge energy of the first barrier material is greater than a conduction band edge energy of the first ferroelectric material, and wherein a valence band edge energy of the first barrier material is less than a valence band edge energy of the first ferroelectric material (As modified each 410 has a conduction band edge energy greater than a conduction band edge energy of each 420, and a valence band edge energy of each 410 is less than a valence band edge energy of each 420);
depositing a second electrode layer (Chen’s 806 would be deposited over Lee’s 400 and therefore over the uppermost 410 from Lee’s 400) comprising a second conductive material over the first barrier layer;
depositing a hard mask layer (From Chen: 808, [0040]) on a first upper surface of the second electrode layer, a second upper surface of the second electrode layer, and between a pair of sidewalls of the second electrode layer (Chen’s 808 would have the configuration of the mask 19 in Okuno’s FIG. 4A which is on a first upper surface of the second electrode layer 18A, a second upper surface of the second electrode layer 18A, and between a pair of sidewalls of the second electrode layer 18A; Accordingly, Chen’s 808 would be on a first upper surface, a second upper surface, and between a pair of sidewalls of Chen’s 806);
etching the hard mask layer and the second electrode layer with a first etching process (Chen FIG. 9 shows the hard mask 808 and the second electrode 806 are etched in a first etching process, [0042]); and
etching the first barrier layer, the first ferroelectric layer, and the first electrode layer with a second etching process, separate from the first etching process (FIG. 11 shows 802, 804 are etched with a second etching process separate from the first etching process; As modified, Chen’s 804 is substituted with Lee’s 400 which includes Lee’s 410, 420 from Lee FIG. 6 and therefore these layers would be etched in the second etching process), wherein an upper surface of the first barrier layer extends laterally from a bottom of an outer sidewall of the second electrode layer to a top of an outer sidewall of the first barrier layer (Lee’s uppermost 410 is the uppermost layer in Lee’s 400; Accordingly, Chen’s upper electrode 114 would be directly on Lee’s uppermost 410 and Lee’s uppermost 410 would therefore extend laterally from a bottom of an outer sidewall of Chen’s 114 to a top of a sidewall of Lee’s uppermost 410 in FIG. 9; Chen’s 806 becomes 114 in FIG. 9).
RE: Claim 34, Chen in view of Okuno, Lee, Koo, Kato discloses The method of claim 33, further comprising:
depositing a second ferroelectric layer (From Lee FIG. 6: second 420 from bottom) comprising a second ferroelectric material, different than the first barrier material, over the first electrode layer (As modified, each 410, 420 would be deposited over Chen’s 802/604; As modified each 410 has a conduction band edge energy greater than a conduction band edge energy of each 420, and a valence band edge energy of each 410 is less than a valence band edge energy of each 420; therefore the material of each 410 is different from the material of each 420), wherein the first ferroelectric layer is deposited over the second ferroelectric layer (In FIG. 6 Lee shows the uppermost 420 deposited over the second 420 from the bottom), wherein the second ferroelectric layer is etched with the second etching process (Chen FIG. 11 shows the second etching process etches Chen’s 804 which as modified is substituted with Lee’s 400; Accordingly, each layer of Lee’s 400 would be etched in the second etching process of Chen; Therefore the second 420 from the bottom in Lee’s FIG. 6 would be etched in the second etching process of Chen).
RE: Claim 35, Chen in view of Okuno, Lee, Koo, Kato discloses The method of claim 34, further comprising:
depositing a second barrier layer (From Lee FIG. 6: second 410 from bottom) comprising a second barrier material, different than the second ferroelectric material, over the second ferroelectric layer, wherein the first ferroelectric layer is deposited over the second barrier layer (Lee’s uppermost 420 is deposited over the second 410 from the bottom in Lee’s FIG. 6), wherein the second barrier layer is etched with the second etching process (Chen FIG. 11 shows the second etching process etches Chen’s 804 which as modified is substituted with Lee’s 400; Accordingly, the second 410 from the bottom in Lee’s FIG. 6 would be etched in the second etching process of Chen), wherein a conduction band edge energy of the second barrier material is greater than the conduction band edge energy of the second ferroelectric material, and wherein a valence band edge energy of the second barrier material is less than the valence band edge energy of the second ferroelectric material (As modified each 410 has a conduction band edge energy greater than a conduction band edge energy of each 420, and wherein a valence band edge energy of each 410 is less than a valence band edge energy of each 420).
RE: Claim 36, Chen in view of Okuno, Lee, Koo, Kato discloses The method of claim 35, further comprising:
depositing a third barrier layer (From Lee FIG. 6: lowermost 410) comprising a third barrier material, different than the first ferroelectric material, over the first electrode layer (As modified, each 410 would be deposited over Chen’s 802/604), wherein the second ferroelectric layer is deposited over the third barrier layer (In Lee FIG. 6, second 420 from the bottom is deposited over the lowermost 410), wherein the third barrier layer is etched with the second etching process (Chen FIG. 11 shows the second etching process etches Chen’s 804 which as modified is substituted with Lee’s 400; Accordingly, each layer of Lee’s 400 would be etched in the second etching process of Chen; Therefore the lowermost 410 would be etched with the second etching process), wherein a conduction band edge energy of the third barrier material is greater than the conduction band edge energy of the second ferroelectric material, and wherein a valence band edge energy of the third barrier material is less than the valence band edge energy of the second ferroelectric material (As modified each 410 has a conduction band edge energy greater than a conduction band edge energy of each 420, and wherein a valence band edge energy of each 410 is less than a valence band edge energy of each 420).
RE: Claim 38, Chen in view of Okuno, Lee, Koo, Kato discloses The method of claim 33, further comprising:
forming a transistor (From Chen FIG. 2: 304) along the substrate;
forming a first conductive interconnect (106be, [0016]) over and coupled to the transistor, wherein the first electrode layer is deposited on the first conductive interconnect (FIG. 2 shows 104 is deposited on 106be; FIG. 8 shows 802, 604 deposited on 106be, [0040]; 802, 604 becomes 104 in FIG. 13); and
forming a second conductive interconnect (120te, 106te in FIG. 13, [0047]) on the second electrode layer.
Conclusion
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899