DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao et al. (US 10,770,414).
Liao discloses a package structure (300), comprising:
a wiring substrate (2319A/2319B external connectors; col. 15, lines 41-59);
an interposer disposed on and electrically connected to the wiring substrate (package structure is mounted to package components through external connectors; interposer-like stacked package architecture is disclosed, Col. 15, lines 29-36, 41-59, and Col. 16, lines 21-32), the interposer comprising:
a semiconductor substrate comprising through vias (Conductive vias/through-vias through the package substrate are disclosed; Col. 9, lines 18-45, Col. 16, lines 21-32, Col. 18, lines 35-60); and
an embedded dielectric waveguide and conductive wirings, disposed over the semiconductor substrate (First and second dielectric waveguides and conductive features formed in stacked layers over the package substrate; from Col. 11, line 7 to Col. 13, line 45, Col. 16, lines 52 to Col. 17, line 31),
wherein one of the conductive wirings connects the embedded dielectric waveguide to the through vias (Conductive vias 809 connect to RDLs and electrodes that couple to the waveguides, Col. 10, line 48 to Col. 11, line 6, Col. 13, lines 24-48, Col. 14, lines 42-67, Col. 15, lines 6-; and
a semiconductor die stacked on and electrically connected to the interposer (Transmitter die 1011A and receiver die 1011B are mounted to the package structure, Col. 9, line 46 to Col. 10, line 16, Col. 15, lines 29-36).
Regarding claim 2, Liao discloses the package structure of claim 1, wherein the interposer comprises:
dielectric layers stacked on the semiconductor substrate (Polymer/ILD layers 1113, 1815, 1916, 2015, 2116 stacked in the package, Col. 12, line 11 to Col. 13, line 45, Col. 14, line 4 to Col. 15, line 28);
wherein the conductive wirings are disposed on and electrically connected to the semiconductor substrate (Conductive vias/RDL features/electrodes formed in the stacked layers and connected through the package; Col. 10, line 48 to Col. 11, line 6, Col. 12, lines 30-43, Col. 13, line 24-45, Col. 14, lines 42-67, Col. 15, lines 29-59),
wherein the conductive wirings and the embedded dielectric waveguide are embedded in the dielectric layers (Waveguides and conductive features are formed within/patterned in polymer/ILD layers; Col. 11, line 53 to Col. 13, line 45, Col. 14, line 24 to Col. 15, line 28).
Regarding claim 3, Liao discloses the package structure of claim 2, wherein the conductive wirings comprise a transmitter coupling structure and a receiver coupling structure (Transmitter electrodes and receiver electrodes are explicitly disclosed, Col. 3, line 36 to Col. 5, line 63, Col. 12, line 30 to Col. 13, line 45, Col. 14, line 42 to Col. 15, line 35),
the transmitter coupling structure is coupled to a transmission end portion of the embedded dielectric waveguide (Col. 3, line 53 to Col. 4, line 8, Col. 12, lines 30-56, Col. 16, lines 52-58, Col. 17, line 62 to Col. 18, line 19), and
the receiver coupling structure is coupled to a receiver end of the embedded dielectric waveguide (Col. 3, line 63 to Col. 4, line 25, Col. 14, lines 42-67, Col. 17, lines 47-61).
Regarding claim 4, Liao the package structure of claim 3,
wherein the transmitter coupling structure comprises a pair of transmitter electrodes coupled to the transmission end portion of the embedded dielectric waveguide (Col. 4, lines 39-59, Col. 5, lines 18-38, Col. 12, lines 30-43, Col. 13, lines 24- 45, Col. 14, lines 42-67), and
the receiver coupling structure comprises a pair of receiver electrodes coupled to the receiver end of the embedded dielectric waveguide (Col. 4, line 60 to Col. 5, line 11, Col. 5, lines 39-57, Col. 12, lines 30-43, Col. 13, lines 24-45, Col. 14, lines 42-67, Col. 17, lines 47-61).
Regarding claim 5, Liao the package structure of claim 4,
wherein the pair of transmitter electrodes comprise a first transmitter electrode and a second transmitter electrode,
the first transmitter electrode and the second transmitter electrode are disposed at opposite surfaces of the transmission end portion of the embedded dielectric waveguide (Col. 4, lines 39-59, Col. 5, lines 18-38, Col. 12, lines 30-43, Col. 13, lines 24- 45, Col. 14, lines 42-67), and
wherein the pair of receiver electrodes comprise a first receiver electrode and a second receiver electrode, the first receiver electrode and the second receiver electrode are disposed at opposite surfaces of the receiver end of the embedded dielectric waveguide (Col. 4, lines 39-59, Col. 5, lines 18-38, Col. 12, lines 30-43, Col. 13, lines 24- 45, Col. 14, lines 42-67).
Regarding claim 6, Liao the package structure of claim 5, wherein the semiconductor die comprises a transmitter circuit and a receiver circuit (Transmitter die 1011A / receiver die 1011B may include those circuits; Col. 9, lines 46-57),
the transmitter circuit is electrically connected to the first transmitter electrode (Col. 12, lines 44-56),
the second transmitter electrode is electrically grounded (Col. 13, lines 24-45),
the receiver circuit is electrically connected to the first receiver electrode (Col. 12, lines 44-56), and
the second receiver electrode is electrically grounded (Col. 13, lines 24-45).
Regarding claim 7, Liao the package structure of claim 1 further comprising:
first conductive terminals disposed between the interposer and the semiconductor die (Conductive pillars/vias and UBMs connecting dies to the package, Col. 15, lines 29-35),
wherein the interposer is electrically connected to the semiconductor die through the first conductive terminals (Col. 15, lines 29-35); and
second conductive terminals disposed between the interposer and the wiring substrate (External connectors 2319A/2319B / UBMs 2218 to package components, Col. 15, lines 29-59),
wherein the interposer is electrically connected the wiring substrate through the second conductive terminals (Col. 15, lines 36-59).
Regarding claim 8, Liao the package structure of claim 7 further comprising:
an underfill disposed between the interposer and the semiconductor die (Molding compound/underfill around dies, Col. 9, line 58 to Col. 9, line 16),
wherein the first conductive terminals are laterally encapsulated by the underfill (Col. 9, line 62 to Col. 9, line 16); and
an insulating encapsulant disposed on the interposer (Molding compound / insulating encapsulant, Col. 9, line 58 to Col. 9, line 16),
wherein the insulating encapsulant laterally encapsulates the semiconductor die and the underfill (Col. 9, line 58 to Col. 9, line 16).
Regarding claim 9, Liao the package structure of claim 1, wherein the semiconductor die comprises a transmitter circuit and a receiver circuit (Col. 9, lines 46-57),
the transmitter circuit is electrically connected to a transmission end portion of the embedded dielectric waveguide (Col. 12, lines 44-56), and
the receiver circuit is electrically connected to a receiver end of the embedded dielectric waveguide (Col. 12, lines 44-56; Col. 14, lines 42-67).
Regarding claim 10, Liao discloses a package structure, comprising:
a photonic interposer comprising:
a semiconductor substrate comprising through vias (Conductive via/through-via package substrate architecture, Col. 9, lines 18-45); and
conductive wirings, a first embedded dielectric waveguide and a second embedded dielectric waveguide (N waveguides and N metal layers; first/second dielectric waveguides in FIG. 1A / FIG. 2; Col. 6, lines 20-67),
wherein one of the conductive wirings is in contact with one of the through vias in the semiconductor substrate and the first embedded dielectric waveguide (Conductive vias connect to RDL features; electrodes couple to waveguides; Col. 12, lines 30-59);
a wiring substrate electrically connected to the photonic interposer (Package connected to substrate / external connectors; Col. 15, lines 29-59); and
a semiconductor die electrically connected to the photonic interposer (Transmitter/receiver die mounted to package; Col. 15, lines 29-35),
the wiring substrate and the semiconductor die being disposed at opposite side of the photonic interposer (Package stack arrangement implies opposite-side mounting/connectivity; Col. 15, lines 29-59),
wherein the second embedded dielectric waveguide is disposed between the first embedded dielectric waveguide and the semiconductor die (reference discloses stacked waveguides disposed one over another, and in the package embodiment the second waveguide is formed above the first waveguide; Col. 17, lines 19-46), and
electromagnetic signals propagated in the second embedded dielectric waveguide have higher transmission frequency than electromagnetic signals propagated in the first embedded dielectric waveguide (reference expressly discloses that the electromagnetic signals propagated by the first and second dielectric waveguides may be different in frequency, and in one embodiment the upper waveguide transmits at a higher frequency; Col. 6, lines 40-54).
Regarding claim 11, Liao discloses the package structure of claim 10, wherein the photonic interposer comprises (embedded waveguide):
dielectric layers stacked on the semiconductor substrate (multiple stacked polymer/ILD layers, including layers 1113, 1815, 1916, 2015, 2116, formed over the package substrate/base structure),
wherein the conductive wirings, the first embedded dielectric waveguide and the second embedded dielectric waveguide are embedded in the dielectric layers (Conductive features/electrodes/vias are formed in patterned polymer/ILD layers; First dielectric waveguide 110 is formed within patterned polymer/ILD layers; Second dielectric waveguide 120 is also formed within stacked polymer/ILD layers).
Regarding claim 12, Liao discloses the package structure of claim 10 further comprising an insulating encapsulant laterally encapsulating the semiconductor die (molding compound / encapsulant surrounding the dies, receiver die, and filling gaps; Col. 9. Lines 58-67),
wherein sidewalls of the insulating encapsulant are substantially aligned with sidewalls of the photonic interposer (encapsulant and planarization).
Regarding claim 13, Liao discloses the package structure of claim 10, wherein the semiconductor die comprises a transmitter circuit and a receiver circuit (transmitter die 1011A and receiver die 1011B, and also describes transmitter/receiver circuits in the waveguide), and the conductive wirings comprise:
a first transmitter electrode electrically connected to the transmitter circuit (Transmitter electrodes 143/146 are connected to the transmitter die/circuit through conductive features);
a second transmitter electrode electrically grounded (Transmitter electrodes 144/147 are coupled to ground);
a first receiver electrode electrically connected to the receiver circuit (Receiver electrodes 153/156 are connected to the receiver die/circuit through conductive features); and
a second receiver electrode electrically grounded (Receiver electrodes 154/157 are coupled to ground).
Regarding claim 14, Liao discloses the package structure of claim 13, wherein
the first transmitter electrode and the second transmitter electrode are disposed at opposite surfaces of a transmission end portion of the first embedded dielectric waveguide (Col. 4, lines 39-59; Col. 5, lines 18-38),
the first receiver electrode and the second receiver electrode are disposed at opposite surfaces of a receiver end of the first embedded dielectric waveguide (Col. 5, lines 39-57).
Regarding claim 15, Liao discloses a package structure, comprising:a photonic interposer comprising;
a semiconductor substrate (package substrate/base structure with conductive via architecture; Col. 9, lines 18-45); and
conductive wirings and embedded dielectric waveguides coupled to portions of the conductive wirings (first/second dielectric waveguides 110, 120 and associated conductive electrodes/features),
wherein one of the conductive wirings is extending along a top surface of the semiconductor substrate and in contact with one of the embedded dielectric waveguides (conductive/electrode features formed in stacked layers and coupled to waveguide end portions);
a wiring substrate electrically connected to the photonic interposer (package/substrate connection through external connectors; Col. 15, lines 37-64); and
a semiconductor die electrically connected to the photonic interposer, the wiring substrate and the semiconductor die being disposed at opposite side of the photonic interposer (transmitter die 1011A and receiver die 1011B mounted to the package structure, with external connectors on the opposite side),
wherein the embedded dielectric waveguides are different in transmission frequency (different-frequency waveguides expressly disclosed).
Regarding claim 16, Liao discloses the package structure of claim 15, wherein the photonic interposer comprises:
the semiconductor substrate comprising through vias (conductive vias / through-via type package interconnects); and
dielectric layers stacked on the semiconductor substrate, wherein the conductive wirings and the embedded dielectric waveguides are embedded in the dielectric layers (stacked polymer/ILD layers with embedded conductive features and waveguides).
Regarding claim 17, Liao discloses the package structure of claim 15 further comprising:
an insulating encapsulant laterally encapsulating the semiconductor die (molding compound / encapsulant surrounding the dies),
wherein sidewalls of the insulating encapsulant are substantially aligned with sidewalls of the photonic interposer (encapsulation geometry and planarization shown, though the exact sidewall-alignment phrasing is not expressly stated).
Regarding claim 18, Liao discloses the package structure of claim 15, wherein the semiconductor die comprises a transmitter circuit and a receiver circuit (transmitter/receiver die and circuit functionality), and the portions of the conductive wirings comprise:
a first transmitter electrode electrically connected to the transmitter circuit (transmitter electrodes 143/146 coupled to transmitter circuitry);
a second transmitter electrode electrically grounded (ground-coupled transmitter electrodes);
a first receiver electrode electrically connected to the receiver circuit (receiver electrodes 153/156 coupled to receiver circuitry); anda second receiver electrode electrically grounded (ground-coupled receiver electrodes 154/157).
Regarding claim 19, Liao discloses the package structure of claim 18, wherein
the first transmitter electrode and the second transmitter electrode are disposed at opposite surfaces of the one of the embedded dielectric waveguides (transmitter electrodes on opposite sides of the first dielectric waveguide at the transmission end portion),
the first receiver electrode and the second receiver electrode are disposed at opposite surfaces of the one of the embedded dielectric waveguides (receiver electrodes on opposite sides of the first dielectric waveguide at the receiver end portion).
Regarding claim 20, Liao discloses the package structure of claim 18, wherein
the first transmitter electrode and the first receiver electrode are disposed on a first surface of the one of the embedded dielectric waveguides (upper-side electrode arrangement along the waveguide),
the second transmitter electrode and the second receiver electrode are disposed on a second surface of the one of the embedded dielectric waveguides (lower-side electrode arrangement along the waveguide).
Response to Arguments
Applicant's arguments filed April 17, 2025 have been fully considered but they are not persuasive.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUE A PURVIS whose telephone number is (571)272-1236. The examiner can normally be reached M-F 0830 to 1630.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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