DETAILED ACTION
This action is responsive to the amendment received November 18, 2025. The amendment has been entered.
Claim Rejections - 35 USC § 112
The prior §112 rejection is withdrawn in view of the amended claims removing the term “”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 10, and 11 are rejected under 35 U.S.C. 103 as being unpatentable over LaRoche (US 2019/0237552) in view of Chang (US 2011/0095426) and Gagnon (US 4,916,506).
Claims 1-12 are product-by-process claims. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed diced into a die need not be formed by the process of dicing, the die may be formed by any process and/or simply provided. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
(Re Claim 1) LaRoche teaches a semiconductor with backside through silicon vias (TSVs), comprising (see Figs. 1A-2U and supporting text):
a semiconductor substrate with a front side and a back side, wherein said semiconductor substrate is diced into a die (substrate 32 or 32+34, dicing is a product-by-process limitation, the completed device is understood to be a semiconductor die);
multiple pads on said front side, wherein said die is provided with corresponding said pads (multiple pads, e.g. see Fig. 2D: 42x);
multiple backside TSVs extending from said back side to said front side (see Fig. 2U, TSVs at 301 &302), wherein a number of said pads connect with said backside TSVs (see Fig. 2U connections as shown), and the other said pads do not connect with said backside TSVs (pads at 423 & 425 are not connected to TSVs);
and a metal coating covering said back side and surfaces of said backside TSVs and connecting with said number of pads that connect with said backside TSVs (Fig. 2U: back metal 28/303 connected to ground, ¶88), wherein said number of pads grounded through said backside TSVs and said metal coating are defined as being in "1" logic state and said the other pads that aren't grounded through said backside TSVs and said metal coating are defined as being in "0" logic state (some pads are connected to ground, others are not, and are therefore defined as claimed).
LaRoche is silent regarding a package structure, wherein said die is encapsulated in said package structure, and said pads are electrically connected to pins of said package structure through bonding wires, and said die ID information of said die is provided through said pads in a form of said "1" logic state and said "0" logic state, implemented through determining if said pads are connected with said metal coating or not.
A PHOSITA would recognize that semiconductor devices are normally packaged to provide protection and electrical connections with external circuits. A PHOSITA would be motivated to look to related packaging art to teach suitable packaging options for LaRoche’s device. Related art from Chang teaches dies having pads and wire bonds for connections with external package terminals (Fig. 3: die with pad 133 and wire bond 144, see Fig. 4: die encapsulated, wire bonds 104 connect to external pins 180 of package). Related art from Gagnon also teaches a packaged semiconductor die 12 is encapsulated in 18, having pads 22 connected to wire bonds 24 connected to pins 16 of the package. Furthermore, regarding a “die”, while LaRoche does not use the term die, it is obvious LaRoche’s completed device is in the form of a die as that is common practice in the art, i.e. it is well known and obvious to batch process a wafer and then singulate into a plurality of dies/chips when packaging, for completeness noting Chen and Gagnon show and recite die(s), not full semiconductor wafers, are packaged. In light of the prior art teaching conventional semiconductor packaging configurations wherein the die is encapsulated in a package structure with die pads electrically connected to pins of the package structure through bonding wires, a PHOSITA would find it obvious to package LaRoche’s device according to Chang and Gagnon, such that each pad is connected to a wire bond and each wire bond is connected to a pin of the package and the die is encapsulated in an encapsulant, because this is a well-known, conventional semiconductor package structure that provides electrical connections between the die and external pins while the encapsulation provides protection. LaRoche’s die packaged according to Chang and Gagnon will then provide die ID information of said die is provided through said pads in a form of said "1" logic state and said "0" logic state, implemented through determining if said pads are connected with said metal coating or not (this limitation provides no additional structure, the claimed information is still present since some of the pads are connected to ground and others are not).
(Re Claim 10) wherein said semiconductor substrate is a GaN-on-Si substrate (32 is Si, 34 is GaN).
(Re Claim 11) wherein said metal coating is plating1 gold (¶88: gold).
Claims 1-3 and 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al. (US 2020/0395475) in view of Chang (US 2011/0095426) and Gagnon (US 4,916,506).
Claims 1-12 are product-by-process claims. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed diced into a die need not be formed by the process of dicing, the die may be formed by any process and/or simply provided. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
(Re Claim 1) Bothe teaches a semiconductor with backside through silicon vias (TSVs), comprising (see Figs. 2A-2C and 4A-4I and supporting text):
a semiconductor substrate with a front side and a back side, wherein said semiconductor substrate is diced into a die (“diced” is a product-by-process limitation, the completed device is understood to be a semiconductor die, substrate 322 or 322+324, ¶¶83-88);
multiple pads on said front side, wherein die is provided with corresponding said pads (310, 365, also see die photos in Figs. 11C and 16 showing pads);
multiple backside TSVs (325) extending from said back side to said front side, wherein a number of said pads connect with said backside TSVs (e.g. 365), and the other said pads do not connect with said backside TSVs (310 not connected to TSV); and a metal coating covering said back side and surfaces of said backside TSVs and connecting with said number of pads that connect with said backside TSVs, wherein said number of pads grounded through said backside TSVs and said metal coating are defined as being in "1" logic state and said the other pads that aren't grounded through said backside TSVs and said metal coating are defined as being in "0" logic state (backmetal 335 is connected to ground, ¶93, some pads are connected to ground, others are not, and are therefore defined as claimed),
Bothe is silent regarding a package structure, wherein said die is encapsulated in said package structure, and said pads are electrically connected to pins of said package structure through bonding wires, and said die ID information of said die is provided through said pads in a form of said "1" logic state and said "0" logic state, implemented through determining if said pads are connected with said metal coating or not.
A PHOSITA would recognize that semiconductor devices are normally packaged to provide protection and electrical connections with external circuits. A PHOSITA would be motivated to look to related packaging art to teach suitable packaging options for Bothe’s device. Related art from Chang teaches dies having pads and wire bonds for connections with external package terminals (Fig. 3: die with pad 133 and wire bond 144, see Fig. 4: die encapsulated, wire bonds 104 connect to external pins 180 of package). Related art from Gagnon also teaches a packaged semiconductor die 12 is encapsulated in 18, having pads 22 connected to wire bonds 24 connected to pins 16 of the package. Furthermore, regarding a “die”, while Bothe does not use the term die, it is obvious Bothe’s completed device is in the form of a die as that is common practice in the art, i.e. it is well known and obvious to batch process a wafer and then singulate into a plurality of dies/chips when packaging, for completeness noting Chen and Gagnon show and recite die(s), not full semiconductor wafers, are packaged. In light of the prior art teaching conventional semiconductor packaging configurations wherein the die is encapsulated in a package structure with die pads electrically connected to pins of the package structure through bonding wires, a PHOSITA would find it obvious to package Bothe’s device according to Chang and Gagnon, such that each pad is connected to a wire bond and each wire bond is connected to a pin of the package and the die is encapsulated in an encapsulant, because this is a well-known, conventional semiconductor package structure that provides electrical connections between the die and external pins while the encapsulation provides protection. Bothe’s die packaged according to Chang and Gagnon will then provide die ID information of said die is provided through said pads in a form of said "1" logic state and said "0" logic state, implemented through determining if said pads are connected with said metal coating or not (this limitation provides no additional structure, the claimed information is still present since some of the pads are connected to ground and others are not).
(Re Claim 2) further comprising multiple transistors on said semiconductor substrate, wherein a source of said transistor connects with one said backside TSV (sources at 315 ¶¶89-103, plural transistors ¶¶85,97,103).
(Re Claim 3) wherein said transistor is high electron mobility transistor (HEMTs: see ¶¶82-103).
(Re Claim 8) wherein a gate of said transistor is T-shaped gate made of Au or Ni/Au alloy (T-shaped gate ¶100, further noting US 8,120,064 is incorporated by reference and discloses forming the gate from gold, col 6 lines 18-21).
(Re Claim 9) comprising a passivation layer covering on said transistors, and a material of said passivation layer is silicon nitride (410/350, ¶¶118,120).
(Re Claim 10) wherein said semiconductor substrate is a GaN-on-Si substrate (322 silicon, 324 GaN, ¶¶85,88).
(Re Claim 11) wherein said metal coating is plating2 gold (¶129).
Claims 4, 7, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al. (US 2020/0395475), Chang (US 2011/0095426) and Gagnon (US 4,916,506), as applied above, and further in view of Lee et al. (US 2017/0330940).
(Re Claim 4) wherein said source and a drain of said transistors are ohmic contact metal made of Ni/Au alloy or Ti/Al/Ni/Au alloy.
(Re Claim 12) further comprising an ohmic contact metal layer formed between said pads and said semiconductor substrate, wherein a material of said ohmic contact metal layer is Ni/Au alloy or Ti/Al/Ni/Au alloy.
Bothe discloses using ohmic contacts (¶92), and discloses Au, Ti, Al, and Ni individually, but not in combination. Related art from Lee discloses forming the ohmic contacts using Ti/Al/Ni/Au by alloying (¶47) to advantageously form a reduced resistance S/D contact. A PHOSITA would find it obvious to look to related art from Lee to teach improved S/D ohmic contacts for use in Bothe’s HEMT.
(Re Clam 7) further comprising an air bridge field plate formed above said transistors, wherein two ends of said air bridge field plate connect respectively to two of said sources.
Bothe is silent regarding an air bridge field plate formed above said transistors, wherein two ends of said air bridge field plate connect respectively to two of said sources. Related art from Lee discloses connecting the sources together with an air bridge (¶65,74,75). A PHOSITA would recognize using an air bridge connection in Bothe’s HEMT, as taught by Lee, increases the breakdown voltage while reducing parasitic capacitance which improves device performance, and therefore would be an obvious modification.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al. (US 2020/0395475), Chang (US 2011/0095426), Gagnon (US 4,916,506), and Lee et al. (US 2017/0330940) as applied above, and further in view of Alcorn et al. (US 2021/0375856).
Claim 5 further comprising a liner covering on parts of surfaces of said source and said drain, and a material of said liner is aluminum nitride.
Bothe is silent regarding the material of the liner 355 covering the source and drain. A PHOSITA would be motivated to look to related art to teach suitable materials where Bother is silent, in order to make and use Bothe’s HEMT. Related art from Alcorn teaches layers 355 and/or 360 may be AlN (¶71). Selecting a known material from the prior art based on its known properties for a known application in an analogous HEMT device would be obvious to a PHOSITA.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Bothe et al. (US 2020/0395475), Chang (US 2011/0095426) and Gagnon (US 4,916,506), and Lee et al. (US 2017/0330940) as applied above, and further in view of Jang et al. (US 2018/0313785).
(Re Claim 6) further comprising bonding pads formed on said sources and said drains, and a material of said bonding pad and said pad is Ti/Au alloy.
Bothe and Lee are silent regarding bonding pads/ pads comprising Ti/Au alloy. Related art from Jang discloses forming a layer of Ti/Au over the ohmic contacts for connecting the HEMT, i.e. bonding pads (¶47). A PHOSITA would find to obvious to look to related art to teach alternative bonding pads which may offer improvements over the materials taught by Bothe. Jang’s Ti/Au provides excellent adhesion, good corrosion resistance and is compatible with gold wire bonding.
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection necessitated by amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/Primary Examiner, Art Unit 2898
1 See MPEP §2113(I), “plating” is given no patentable weight, the gold may be formed by any process.
2 See note 1 above.