DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 28 January 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed 28 January 2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. § 103 using Kakkad in view of Huang, Orihashi, and Cheng have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made using Kakkad in view of Orihashi, and Miykura.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 7-12, 16-18, 22, 29-31 are rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), and Miyakura (US 2018/0040475 A1 ).
Regarding claim 1, Kakkad teaches a method (title, abstract) of processing a substrate (4; see Fig. 2), comprising:
(a) forming (¶ [0021], Fig. 6: depositing step 60) a first film (1; see Fig. 1; also layer 6 in Fig. 2 and ¶ [0034]) in an amorphous state on the substrate (4; see Fig. 2) by supplying a first process gas to the substrate (¶ [0024]: using Silane SiH4 as precursor gas in a PECVD deposition method);
(b) forming (¶ [0021], Fig. 6: forming doped layer step 61) a second film ( 2; see Fig. 1; see also layer 7 in Fig. 2 and ¶ [0035]) in an amorphous state (Fig. 1, ¶ [0021]: doped a-Si film 2), which has a crystallization temperature lower than a crystallization temperature of the first film (¶ [0021]: doped film 2 crystallizes at a lower thermal budget than undoped layer; ¶ [0024]: reduction of thermal budgets of doped a-Si material using diborane gas as dopant of the film 2), on the first film by supplying a second process gas (¶ [0024]: diborane gas) to the substrate ;
(c) crystallizing the first film and the second film formed on the substrate by heating the first film and the second film (¶ [0021], Fig. 6: Step annealing step 62); and
(d) removing at least the second film by exposing a surface of the substrate to an etching agent after crystallizing the first film and the second film (¶ [0031]: etched away partially or entirely; ¶ [0032]: wet etching or dry etching of Si02 formed after annealing and optional oxidization step).
However, Kakkad does not teach a method of processing a substrate comprising:
forming a seed layer by performing a cycle, which includes supplying a seed gas to the substrate and supplying a reducing gas to the substrate, a predetermined number of times.
Orihashi, in the same field of invention, teaches a method of processing a substrate (200; see Figs. 1-2 and 6A-6C; ¶ [0024], ¶ [0027], ¶ [0061]; abstract) comprising:
forming a seed layer (200f; ¶ [0082]) by performing a cycle (1st cycle in Fig. 4 and ¶ [0049]; or, alternatively, "1 cycle" in Fig. 5), which includes supplying a seed gas ( DCS; Figs. 4 & 5, ¶ [0063]-[0068]; DCS is a seed gas since it is a processing gas used to form a seed layer on the wafer as taught in ¶ [0049]; also DCS is cited in ¶ [0090] of the instant application as a seed gas ) to the substrate (200; see Figs. 6A & 6B) and supplying a reducing gas ( H2; see Figs. 4 & 5; ¶ [0050], ¶ [0069]: H2 used to remove residual Cl in the DCS gas to avoid hindrance of seed formation; this is analogous to the use of H2 gas in ¶ [0099] of the instant application; hence Orihashi teaches the use of H2 as a reducing gas; also, Figs. 4 & 5 teach supplying DCS and H2 in each cycle of the P-doped seed layer step) to the substrate, a predetermined number of times (Fig. 4 shows seed layer formation performed up to the nth cycle; ¶ [0049]: predetermined number of times).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Orihashi into the method of Kakkad by adding a step of forming a seed layer on a substrate, with the said step consisting of performing a predetermined number of cycles and with each cycle consisting of supplying a seed gas and a reducing gas. The ordinary artisan would have been motivated to modify Kakkad in the manner set forth above for at least the purpose using the seed layer to form the first film (200g, see Orihashi Fig. 6E and ¶ [0114]) on the seed layer while reducing or eliminating pinholes in the first film (¶ [0083]), which prevents the first film from being etching in a wet etching process performed after the first film is formed (Orihashi ¶ [0194]), and therefore, improving the quality of the first film formed on the substrate (Orihashi ¶ [0203]).
Orihashi further teaches supplying the reducing gas either simultaneously with the seed gas (¶ [0050]) or asynchronously with the seed gas (Fig. 5, modifications 2-8; ¶ [0151]). Hence, the pressures of the seed gas and the reducing gas can be independently controlled (¶ [0062]).
However, Kakkad et al. do not teach the method comprising of supplying the seed gas at a first pressure and supplying the reducing gas at a second pressure higher than the first pressure.
Miyakura, in the same field of invention, teaches a method at least comprising of supplying the seed gas (¶ [0053] ) at a first pressure (¶ [0056], [0058]: 1 to 1000 Pa) and supplying the reducing gas (¶ [0076]: hydrogen used for purging ) at a second pressure (¶ [0078]: 500 to 2000 Pa) higher than the first pressure.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Miyakura into the method of Kakkad et at to supply the second gas at a pressure higher than that of the seed gas. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the reducing gas as a purge gas to effectively clean the entire surface of the wafer (Miyakura ¶ [0076]), with the ordinary artisan noting that Orihashi also teaches using the reducing gas in the same manner (see Orihashi ¶ [0069]). Furthermore, using scientific principles, the ordinary artisan will find it obvious that increasing the pressure of the reducing gas would effectively optimize and/or increase the rate of cleaning. See also Le Chatelier's principle, NPL: “Effect of Pressure on Gas-Phase Equilibria,” and MPEP § 2144.02.
Regarding claim 3, the limitations of claim 1, wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1),
wherein in (b), the second film is a film (2) doped with the dopant (¶ [0011], 0034: n-type or p-type dopants), and
wherein in (c), a part of the dopant in the second film is diffused into the first film (Kakkad ¶ [0025], [0030]: teaches that no significant, emphasis added, doping found on undoped film at the crystallization thermal budget with appropriate doping concentration of Boron of 1021 cm3. Through this passage, Kakkad teaches that traces of doping elements are present due to diffusion during the annealing process), and
wherein in (d), a portion of the first film into which the dopant in the second film is diffused is also removed (Kakkad ¶ [0035]: In this TFT gate design example, Kakkad teaches an island formation in where it requires the removal of layers 7, analogous to the second film, and a portion of layer 6, analogous to the first film, after a crystallization step, in order to form a completely undoped layer in the island. Hence, Kakkad removed a portion of the first film contaminated by the dopants).
Regarding claim 4, the limitations of claim 3, wherein in (d), a surface of the first film, which does not contain the dopant, is exposed (Kakkad ¶ [0031]: doped layer entirely etched; Fig. 2, ¶ [0036]: no doped layer 7 remain on the channel).
Regarding claim 7, the limitations of claim 1, wherein in (c), the crystallization of the second film is started earlier than the crystallization of the first film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method).
Regarding claim 8, the limitations of claim 1, wherein in (c), the crystallization of the second film is completed earlier than the crystallization of the first film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method.).
Regarding claim 9, the limitations of claim 7, wherein in (c), the first film is crystallized starting from crystal grains of the second film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method.).
Regarding claim 10, the limitations of claim 7, wherein in (c), the first film takes on a crystal state of the second film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method).
Regarding claim 11, the limitations of claim 1, wherein in (c), a temperature of the substrate is set to 550 degrees C or higher and 650 degrees C or lower (Kakkad ¶ [0027]-[0028]: at or lower than 600C).
Regarding claim 12, the limitations of claim 3 wherein in (a), the first film is formed thicker (Kakkad ¶ [0034], Fig. 2: undoped a-Si film 6 made thick enough to such that after etching step to form the island, the undoped crystallized portion of film 6 is retained) by a depth or more of diffusion of the dopant (Kakkad ¶ [0025], ¶ [0030]: teaches that no significant, emphasis added, doping found on undoped film at the crystallization thermal budget with appropriate doping concentration of Boron of 1021 cm3; through this passage, Kakkad teaches that traces of doping elements are present due to diffusion during the annealing process) from the second film (Kakkad Fig. 2: layer 7) into the first film in (c) than a film thickness of the first film (Kakkad Fig. 2 shows the thickness before and after etching) obtained after performing (d) (Kakkad ¶ [0034]-[0035]).
Regarding claim 16, the limitations of claim 1, wherein the first film is an amorphous silicon film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1; Fig. 1: film 1), and
wherein the second film is an amorphous silicon film doped with a dopant (Kakkad ¶ [0021]: doped a-Si film 2: Fig. 1: film 2; ¶ [0024]: diborane gas).
Regarding claim 17, the limitations of claim 1, wherein an oxide film (5, Kakkad Fig. 2) is formed on the surface of the substrate, and
wherein in (a), the first film (Kakkad ¶ [0035], Fig. 2, undoped a-silicon layer 6) is formed on the oxide film (5; Kakkad ¶ [0034] and Fig. 2 show gate insulator layer 5 below undoped a-si layer 6).
Regarding claim 18, a method of manufacturing a semiconductor device comprising the method of Claim 1 (Kakkad ¶ [0043]-[0045] and Figs. 3A-3B shows a thin film transistor, TFT, made using the method described in ¶ [0021]-[0032]).
Regarding claim 22, the method of Claim 1, wherein the act of supplying the seed gas and the act of supplying the reducing gas are performed alternately (Orihashi Fig. 5, Modification 9; ¶ [0168] : "Modification 9 shown in FIG. 5, in the seed step, the H.sub.2 gas may be continuously supplied. As such, in the seed step, under a state where the step of supplying the H.sub.2 gas is performed, the step of supplying the DCS gas and the step of supplying the DS gas may be alternately performed", emphasis added).
Regarding claim 29, the method of claim 1, wherein the first pressure is in a range of 277 to 1,200 Pa (Miyakura ¶ [0056], [0058]: 1 to 1000 Pa), and the second pressure is in a range of 1,333 to 13,322 Pa (¶ [0078]: 500 to 2000 Pa).
Regarding claim 30, the method of claim 29, wherein the first pressure is in a range of 667 to 1,200 Pa (Miyakura ¶ [0056], [0058]: 1 to 1000 Pa).
Regarding claim 31, the method of claim 29, wherein the seed layer is formed at a temperature of 350 to 450 degrees C (Orihashi ¶ [0101], ¶ [0063]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1), Orihashi (US 2017/0263441 A1), and Miyakura (US 2018/0040475 A1 ) as applied to claim 1 above, and further in view of Huang (US 6,265,267 B1).
Regarding claim 6, Kakkad et al. teach the limitations of claim 1, wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1),
wherein in (b), the second film is a film doped with a dopant (¶ [0011], 0034: n-type or p-type dopants).
However, Kakkad et al. do not teach the method further comprising: (e) oxidizing at least one portion, where the dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before performing (d).
Huang, in the same field of invention, teaches a method comprising:
(e) oxidizing (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portion of 222b; see Huang Fig. 3C; Column 5, Line 41), where the dopant is present (Huang Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film ( 218; see Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad et al. in view of Huang teaches the crystallizing step; see Kakkad: ¶ [0021], Fig. 6: Step annealing step 62) and before performing (d) (Column 5, Lines 61-32: 226 is removed by wet-etching; also see Kakkad: ¶ [0031]: etched away partially or entirely; ¶ [0032]: wet etching or dry etching of SiO2 formed after annealing and optional oxidization step).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et at to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer (222a) transforms it to be a “more loosely packed” layer compared to the undoped first film (218) (see Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures as embodied in Huang Fig. 3D.
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), and Miyakura (US 2018/0040475 A1 ) as applied to claim 1 above, and further in view of Yabuhara (US 2008/0237686 A1)
Regarding claim 14, Kakkad et al. teach the limitations of claim 1. However, Kakkad et al. do not teach a method of processing a substrate wherein a thickness of the second film is made equal to or thicker than a thickness of the first film.
Yabuhara, in the same field of invention, teaches a method of manufacturing a semiconductor device that requires a Phosphorus-doped amorphous second silicon film (80; see Fig. 4A and ¶ [0033]) formed on top of an undoped amorphous silicon first film (70; ¶ [0033]) and then subjected to annealing to form a polycrystalline film (600; see Fig. 4B ¶ 0035) and wherein a thickness (T8; see Fig. 4A) of the second film is made equal to or thicker (Fig. 4A shows T8 is thicker than T7) than a thickness (T7) of the first film.
A person of ordinary skill in the art, prior to the effective date of the invention, will find it obvious to combine the teachings Yabuhara into the method of Kakkad et al., wherein the thickness of the second film is made equal to or thicker than that of the first film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of designing a semiconductor devices such as thin-film-transistors, short-channel devices (Kakkad: ¶ [0033]-[0054]), or non-volatile semiconductor memory devices having gate electrodes made of polycrystalline silicon (Yabuhara: ¶ [0005]) such that the grain size of the polycrystalline silicon is made larger by increasing the thickness of the second film deposited prior to the annealing step (Yabuhara: Fig. 1; ¶ [0012], [0016]-[0017]). Having a larger grain size will then result in reducing electrical interference between adjacent floating gate electrodes and variations of threshold and/or operating voltages can be restrained (Yabuhara ¶ [0041]). Hence, increasing the thickness of the second film leads to device performance optimization and smaller over-all device size (Yabuhara ¶ [0041]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), and Miyakura (US 2018/0040475 A1 ) as applied to claim 1 above, and further in view of Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1).
Regarding claim 23, Kakkad et al. teach the method of Claim 1,
wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1), and
wherein in (b), the second film is a film doped with the dopant (¶ [0011], 0034: n-type or p-type dopants).
However, Kakkad et al. do not teach the method further comprising:
(e) modifying at least one portion, wherein a dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before performing (d), in such a manner that a non-doped portion of the first film is not modified;
Huang, in the same field of invention, teaches a method comprising:
(e) modifying (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portion of 222b; see Fig. 3C; Column 5, Line 41), where a dopant is present (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad teaches the crystallizing step in Kakkad et al. in view of Huang) and before performing (d) (the removing at least the second film 222b through wet-etching; see Column 5, Lines 61-63), in such a manner that a non-doped portion (portions of 218 below 222b) of the first film 218 is not modified (Column 6, Lines 1-4: "to remove the poly-oxide layer 222b without removing the gate oxide layers 218, 226 formed in the thermal process"),
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et al. to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step of Kakkad, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer 222a transforms it to be a "more loosely packed" layer compared to the undoped first film 218. (Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures such as embodied in Huang Fig. 3D.
However, Kakkad et al. do not teach the method wherein in (e), the at least one portion is modified by supplying a modifying gas including a mixture of O-containing gas and H-containing gas.
Horita, In the same field of invention, teaches a method wherein in (e), the at least one portion is modified by supplying a modifying gas (¶ [0072]: oxidizing gas supplied to wafer 200) including a mixture of O-containing gas and H-containing gas (¶ [0073]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Horita into the method of Kakkad in et al. to supply the modifying gas to include a mixture of O-containing gas and H-containing gas in order during the modifying process of step (e). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of enhancing the oxidizing power of the modifying gas (Horita ¶ [0073]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), and Miyakura (US 2018/0040475 A1 ) as applied to claim 1 above, and further in view of Wang (US 2021/0118687 A1).
Regarding claim 24, Kakkad et al. teach the method of Claim 1, but do not teach: wherein the etching agent includes a fluorine-based gas.
Wang, in the same field of invention, teaches a method wherein the etching agent includes a fluorine-based gas (¶ [0025]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wang into the method of Kakkad et al. to remove the second film wherein the etching agent includes a fluorine-based gas. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of substituting the wet etching process of Kakkad (see ¶ [0032]) with the process of Wang in order to have a better etch selectivity rate to each away an oxide layer (140, see Wang Fig. 1) against other film layers on the substrate (Wang: abstract).
Claims 32 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) and Miyakura (US 2018/0040475 A1 ) as applied to claim 31, and further in view of Cheng (US 2019/0019724 A1).
Regarding claim 32, Kakkad et al. teach the method of claim 31, but do not teach: the first film is formed at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa, and the second film is formed at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa in (b).
Cheng, in the same field of invention, teaches a method of forming a first film (¶ [0023]: amorphous silicon film) and a second film (¶ [0024]: doped amorphous silicon film) wherein the forming of the first film at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa (¶ [0025]: 150 to 500 C and 100 mTorr to 350 Torr, which is 13 Pa to 46,662 Pa) and the forming of the second film at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa (¶ [0025]: 150 to 500 C and 100 mTorr to 350 Torr, which is 13 Pa to 46,662 Pa).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the method of Kakkad et al. to form the first film at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa and to form the second film at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa, when doing step (b). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of substituting the PECVD deposition process of Kakkad that deposits the undoped amorphous first film and the doped amorphous second film with a suitable deposition process such as CVD, PECVD, ALD, PEALD (Cheng ¶ [0022]), which generally require subjecting the substrate to several precursor gases (Cheng ¶ [0023], ¶ [0024]) in a chamber (310, Fig. 3, ¶ [0033]) at the abovementioned temperature and pressure conditions.
Regarding claim 33, the method of Claim 1, wherein the seed layer, the first film and the second film are crystallized at a temperature of 550 to 650 degrees C (Kakkad ¶ [0024]-[0028]: 600 C to 650 C ) and at a pressure of 1 to 101,325 Pa (Kakkad ¶ [0008] and claim 14: annealing for crystallization is at 650 C and 1 atm, which is 101,325 Pa).
Claim 34 are rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), Miyakura (US 2018/0040475 A1 ), and Cheng (US 2019/0019724 A1) as applied to claim 33 above, and further in view of Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1).
Regarding claim 34, Kakkad et al. teach the method of claim 33. However, Kakkad et al. do not teach the method comprising:
(e) modifying at least one portion, where a dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before (d), in such a manner that a non-doped portion of the first film is not modified,
wherein the first film is not doped with the dopant and the second film is doped with the dopant.
Huang, in the same field of invention, teaches a method comprising:
(e) modifying (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portions of 222b; see Fig. 3C; Column 5, Line 41), where a dopant is present (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad teaches the crystallizing step in Kakkad et al. in view of Huang) and before performing (d) (the removing at least the second film 222b through wet-etching; see Column 5, Lines 61-63), in such a manner that a non-doped portion (portions of 218 below 222b) of the first film 218 is not modified (Column 6, Lines 1-4: "to remove the poly-oxide layer 222b without removing the gate oxide layers 218, 226 formed in the thermal process"),
wherein the first film is not doped with the dopant (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film is doped with the dopant (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et al. to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step of Kakkad, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer 222a transforms it to be a "more loosely packed" layer compared to the undoped first film 218. (Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures such as embodied in Huang Fig. 3D.
However, Kakkad et al. do not teach the method wherein the at least one portion is modified at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa in (e).
Horita, in the same field of invention, teaches a method wherein the at least one portion is modified at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa (¶ [0055], ¶ [0062]: 600 to 900 C; ¶ [0069]: 133 to 1000 Pa; see also Fig. 4).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Horita into the method of Kakkad et al. to modify the at least one portion of the substrate at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa while performing step (e). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of shortening the time required for the modifying process to oxidize the amorphous film (Horita ¶ [0087]), for increasing the etching rate of the oxidized amorphous film (Horita, Fig. 8, ¶ [0105] and Fig. 10, ¶ [0114]) and for improving the quality of the film forming process (Horita ¶ [0048]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), Miyakura (US 2018/0040475 A1 ), Cheng (US 2019/0019724 A1), Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1) as applied to claim 34 above, and further in view of Wang (US 2021/0118687 A1).
Regarding claim 35, Kakkad et al. teach the method of Claim 34, but do not teach: wherein at least the second film is removed at a temperature of room temperature to 1,000 degrees C and at a pressure of 133 to 50,000 Pa in (d).
Wang, in the same field of invention, teaches a method wherein at least the second film is removed at a temperature of room temperature to 1,000 degrees C and at a pressure of 133 to 50,000 Pa (¶ [0025]: 0 to 200 C and 0.1 to 20 Torr, which is 13 Pa to 2666 Pa).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wang into the method of Kakkad et al. to remove at least the second film at a temperature of room temperature to 1000 C and at a pressure of 133 to 50000 Pa when performing step (d). The ordinary artisan would have been motivated to modify Kakkad in view of Huang, Orihashi, and Cheng in the manner set forth above for at least the purpose of substituting the wet etching process of Kakkad (see ¶ [0032]) with the etching process of Wang in order to have a better etch selectivity rate to each away an oxide layer (140, see Wang Fig. 1) against other film layers on the substrate (Wang: abstract).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-4, 6-12, 14, 16-18, 22-24, and 29-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 19 of U.S. Patent No. 11,587,788 in view of Kakkad (US 2007/0004185 A1) and Orihashi (US 2017/0263441 A1).
Claim 1 of the instant application, and by extension, its dependent claims 3-4, 6-12, 14, 16-18, 22-24, and 29-25, recite a subset of the limitations of claim 1 of the reference patent, particularly:
forming a seed layer by performing a cycle (“(a) forming a silicon seed layer on a substrate by performing a cycle a predetermined number of times”), which includes supplying a seed gas to a substrate (“(a1) supplying a first gas containing halogen and silicon to the substrate”) at a first pressure and supplying a reducing gas to the substrate (“(a2) supplying a second gas containing hydrogen to the substrate”) at a second pressure higher than the first pressure (“wherein a pressure of a space in which the substrate is located in (a2) is set higher than a pressure of the space in which the substrate is located in (a1)”), a predetermined number of times (see limitation (a) in the reference claim).
The reference patent further claims manufacturing a semiconductor device using the method of claim 1 (see claim 19 of the reference patent). From the disclosure, this means using the seed layer formed in claim 1 to form an amorphous silicon layer (see Fig. 4 and 6 and Col. 13, Ln. 40)
However, the reference patent does not teach:
(a) forming a first film in an amorphous state, on the seed layer by supplying a first process gas to the substrate;
(b) forming a second film in an amorphous state, which has a crystallization temperature lower than a crystallization temperature of the first film, on the first film by supplying a second process gas to the substrate;
(c) crystallizing the first film and the second film formed on the substrate by heating the first film and the second film; and
(d) removing at least the second film by exposing a surface of the substrate to an etching agent after crystallizing the first film and the second film.
Kakkad, in the same field of invention, teaches a method comprising:
(a) forming (¶ [0021], Fig. 6: depositing step 60) a first film (1; see Fig. 1; also layer 6 in Fig. 2 and ¶ [0034]) in an amorphous state on the seed layer (Kakkad shows 6 deposited on substrate 4; see Fig. 2; the reference patent in view of Kakkad teaches forming 6 on the seed layer) by supplying a first process gas to the substrate (¶ [0024]: using Silane SiH4 as precursor gas in a PECVD deposition method);
(b) forming (¶ [0021], Fig. 6: forming doped layer step 61) a second film ( 2; see Fig. 1; see also layer 7 in Fig. 2 and ¶ [0035]) in an amorphous state (Fig. 1, ¶ [0021]: doped a-Si film 2), which has a crystallization temperature lower than a crystallization temperature of the first film (¶ [0021]: doped film 2 crystallizes at a lower thermal budget than undoped layer; ¶ [0024]: reduction of thermal budgets of doped a-Si material using diborane gas as dopant of the film 2), on the first film by supplying a second process gas (¶ [0024]: diborane gas) to the substrate ;
(c) crystallizing the first film and the second film formed on the substrate by heating the first film and the second film (¶ [0021], Fig. 6: Step annealing step 62); and
(d) removing at least the second film by exposing a surface of the substrate to an etching agent after crystallizing the first film and the second film (¶ [0031]: etched away partially or entirely; ¶ [0032]: wet etching or dry etching of Si02 formed after annealing and optional oxidization step).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Kakkad into the method of the reference patent to form an amorphous first film on the seed layer, forming an amorphous second film on the first film, with the second film having a crystallization temperature lower than a crystallization temperature of the first film, crystallizing both films through heat, and removing the second film through etching. The ordinary artisan would have been motivated to modify the reference patent in the manner set forth above for at least the purpose of manufacturing a semiconductor device (thin-film transistor, see ¶ [0005] ) with reduced thermal budget required for crystallization (Kakkad ¶ [0014] ), which reduces the manufacturing time without a reduction of the crystal grain size (Kakkad ¶ [0012]-[0013] , ¶ [0023] ). The ordinary artisan will also find it obvious to etch the second film in order to form source, drain, and channel regions of the thin-film transistor (Kakkad ¶ [0031] ).
Conclusion
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/JOHN M PARKER/ Examiner, Art Unit 2899