DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 02 June 2026, with respect to the rejection of claim 1 under 35 U.S.C. § 103 using Kakkad in view of Huang, Orihashi, and Miyakura and under the nonstatutory double patenting have been fully considered and are persuasive in part. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground of rejection under 35 U.S.C. § 103 is made using Kakkad in view of Orihashi due to the amendments in claim 1.
Specifically, the examiner finds that Orihashi teaches DS to be a seed gas supplied at a first pressure to form a nuclei on the substrate and H2 to be a reducing gas supplied at a second pressure higher than the first pressure, with the H2 reacting with the nuclei in order to form the seed layer.
The applicant argues that Orihashi uses H2 not as a reducing gas but rather as an auxiliary gas used for removing chlorine and, hence, declared that Orihashi does not teach “reducing gas reacts with the nuclei to form the seed layer.” The examiner respectfully disagrees. Clearly, Orihashi’s use of H2 gas mirrors that of the applicant as described in paragraphs [0096]-[0097] of the instant application. The instant application discloses the use of H2 gas to desorb (plain meaning: remove) the chlorine that is found on the nucleus formed on the substrate in order to remove said chlorine from the seed layer. Likewise, Orihashi, in paragraph [0078] teaches “H2 gas supplied together with the DCS gas can contribute to effectively remove the residual Cl which is a factor that inhibits formation of a seed by the DS gas in the next step 2.”
In summary, this application is not placed in a condition for an allowance.
Claim Objections
Claim 1 is objected to because of the following informalities: the use of “nuclei” instead of “nucleus,” as used in the specification to denote the element formed by the seed gas on the substrate prior to subjecting said nucleus to the reducing gas. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-4, 7-12, 16-18, 22, 29, 31 and 36 are rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1).
Regarding claim 1, Kakkad teaches a method (title, abstract) of processing a substrate (4; see Fig. 2), comprising:
(a) forming (¶ [0021], Fig. 6: depositing step 60) a first film (1; see Fig. 1; also layer 6 in Fig. 2 and ¶ [0034]) in an amorphous state on the substrate (4; see Fig. 2) by supplying a first process gas to the substrate (¶ [0024]: using Silane SiH4 as precursor gas in a PECVD deposition method);
(b) forming (¶ [0021], Fig. 6: forming doped layer step 61) a second film ( 2; see Fig. 1; see also layer 7 in Fig. 2 and ¶ [0035]) in an amorphous state (Fig. 1, ¶ [0021]: doped a-Si film 2), which has a crystallization temperature lower than a crystallization temperature of the first film (¶ [0021]: doped film 2 crystallizes at a lower thermal budget than undoped layer; ¶ [0024]: reduction of thermal budgets of doped a-Si material using diborane gas as dopant of the film 2), on the first film by supplying a second process gas (¶ [0024]: diborane gas) to the substrate ;
(c) crystallizing the first film and the second film formed on the substrate by heating the first film and the second film (¶ [0021], Fig. 6: Step annealing step 62); and
(d) removing at least the second film by exposing a surface of the substrate to an etching agent after crystallizing the first film and the second film (¶ [0031]: etched away partially or entirely; ¶ [0032]: wet etching or dry etching of Si02 formed after annealing and optional oxidization step).
However, Kakkad does not teach a method of processing the substrate comprising:
forming a seed layer by performing a cycle two or more times, the cycle including: supplying a seed gas to the substrate at a first pressure to form nuclei on a surface of the substrate; and supplying a reducing gas to the nuclei on the surface of the substrate at a second pressure higher than the first pressure so that the reducing gas reacts with the nuclei to form the seed layer.
Orihashi, in the same field of invention, teaches a method of processing a substrate (200; see Figs. 6A-6D, ¶ [0064]) comprising:
forming a seed layer (200f; ¶ [0083]) by performing a cycle (a cycle of Modification 5 in Fig. 5) two or more times (Fig. 4 shows seed layer formation performed up to the nth cycle; ¶ [0049]: predetermined number of times; also see ¶ [0080] ), the cycle including:
supplying a seed gas ( DS ) to the substrate (200; ¶ [0073] ) at a first pressure (¶ [0091], [0097],: P2 set to 250 Pa to 350 Pa ) to form nuclei (200c; Fig. 6C and ¶ [0074] ) on a surface (top surface) of the substrate (200) and
supplying a reducing gas ( H2; see Modification 5 in Fig. 5; ¶ [0069]: H2 reduces any residual Cl; hence H2 is a reducing gas) to the nuclei on the surface of the substrate (Modification 5 teaches introducing H2 after supplying DS; ¶ [0074]: the nuclei is formed after supplying DS) at a second pressure (¶ [0094]: P1 set to 400 Pa to 1000 Pa; alternatively, ¶ [0096]: P1 exceeds 1000 Pa; note: ¶ [0069] describes supplying H2 under Step 1 and ¶ [0091] discloses P1 to be the pressure for step 1 ) higher than the first pressure (¶ [0091]) so that the reducing gas reacts (removes residual Cl) with the nuclei to form the seed layer (¶ [0078]: “the action of the H2 gas supplied together with the DCS gas can contribute to effectively remove the residual Cl which is a factor that inhibits formation of a seed by the DS gas in the next step 2”; note: since Modification 5 in Fig. 5 teaches supplying H2 after DS, then Orihashi teaches this limitation ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Orihashi into the method of Kakkad by adding a step of forming a seed layer on a substrate, with the said step consisting of performing a cycle two or more times, the cycle including: supplying a seed gas to the substrate at a first pressure to form nuclei on a surface of the substrate and supplying a reducing gas at a second pressure higher than the first pressure to react with the nuclei to form the seed layer on the substrate. The ordinary artisan would have been motivated to modify Kakkad in the manner set forth above for at least the purpose using the seed layer to form the first film (200g, see Orihashi Fig. 6E and ¶ [0114]) on the seed layer, while reducing or eliminating pinholes in the first film (¶ [0083]), which prevents the first film from being etching in a wet etching process performed after the first film is formed (Orihashi ¶ [0194]), and therefore, improving the quality of the first film formed on the substrate (Orihashi ¶ [0203]). Furthermore, the ordinary skilled artisan would be motivated to use the reducing gas as means to clean any uneven structure that may be formed by the nuclei on the substrate (¶ [0078]: using a combination of DCS and H2 gas to desorb residual Cl that may inhibit seed formation) and to use the higher pressure when introducing the reducing step in order to enhance its treatment effect (¶ [0091]-[0092] ).
Regarding claim 3, the limitations of claim 1, wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1),
wherein in (b), the second film is a film (2) doped with the dopant (¶ [0011], 0034: n-type or p-type dopants), and
wherein in (c), a part of the dopant in the second film is diffused into the first film (Kakkad ¶ [0025], [0030]: teaches that no significant, emphasis added, doping found on undoped film at the crystallization thermal budget with appropriate doping concentration of Boron of 1021 cm3. Through this passage, Kakkad teaches that traces of doping elements are present due to diffusion during the annealing process), and
wherein in (d), a portion of the first film into which the dopant in the second film is diffused is also removed (Kakkad ¶ [0035]: In this TFT gate design example, Kakkad teaches an island formation in where it requires the removal of layers 7, analogous to the second film, and a portion of layer 6, analogous to the first film, after a crystallization step, in order to form a completely undoped layer in the island. Hence, Kakkad removed a portion of the first film contaminated by the dopants).
Regarding claim 4, the limitations of claim 3, wherein in (d), a surface of the first film, which does not contain the dopant, is exposed (Kakkad ¶ [0031]: doped layer entirely etched; Fig. 2, ¶ [0036]: no doped layer 7 remain on the channel).
Regarding claim 7, the limitations of claim 1, wherein in (c), the crystallization of the second film is started earlier than the crystallization of the first film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method).
Regarding claim 8, the limitations of claim 1, wherein in (c), the crystallization of the second film is completed earlier than the crystallization of the first film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method.).
Regarding claim 9, the limitations of claim 7, wherein in (c), the first film is crystallized starting from crystal grains of the second film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method.).
Regarding claim 10, the limitations of claim 7, wherein in (c), the first film takes on a crystal state of the second film (Kakkad ¶ [0049]: explains that doped regions crystallize at reduced thermal budget and grains grow laterally from the doped regions into the undoped region in Kakkad's short channel device application of the method).
Regarding claim 11, the limitations of claim 1, wherein in (c), a temperature of the substrate is set to 550 degrees C or higher and 650 degrees C or lower (Kakkad ¶ [0027]-[0028]: at or lower than 600C).
Regarding claim 12, the limitations of claim 3 wherein in (a), the first film is formed thicker (Kakkad ¶ [0034], Fig. 2: undoped a-Si film 6 made thick enough to such that after etching step to form the island, the undoped crystallized portion of film 6 is retained) by a depth or more of diffusion of the dopant (Kakkad ¶ [0025], ¶ [0030]: teaches that no significant, emphasis added, doping found on undoped film at the crystallization thermal budget with appropriate doping concentration of Boron of 1021 cm3; through this passage, Kakkad teaches that traces of doping elements are present due to diffusion during the annealing process) from the second film (Kakkad Fig. 2: layer 7) into the first film in (c) than a film thickness of the first film (Kakkad Fig. 2 shows the thickness before and after etching) obtained after performing (d) (Kakkad ¶ [0034]-[0035]).
Regarding claim 16, the limitations of claim 1, wherein the first film is an amorphous silicon film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1; Fig. 1: film 1), and
wherein the second film is an amorphous silicon film doped with a dopant (Kakkad ¶ [0021]: doped a-Si film 2: Fig. 1: film 2; ¶ [0024]: diborane gas).
Regarding claim 17, the limitations of claim 1, wherein an oxide film (5, Kakkad Fig. 2) is formed on the surface of the substrate, and
wherein in (a), the first film (Kakkad ¶ [0035], Fig. 2, undoped a-silicon layer 6) is formed on the oxide film (5; Kakkad ¶ [0034] and Fig. 2 show gate insulator layer 5 below undoped a-si layer 6).
Regarding claim 18, a method of manufacturing a semiconductor device comprising the method of Claim 1 (Kakkad ¶ [0043]-[0045] and Figs. 3A-3B shows a thin film transistor, TFT, made using the method described in ¶ [0021]-[0032]).
Regarding claim 22, the method of Claim 1, wherein the act of supplying the seed gas and the act of supplying the reducing gas are performed alternately (Orihashi Fig. 5, Modification 9; ¶ [0168] : "Modification 9 shown in FIG. 5, in the seed step, the H.sub.2 gas may be continuously supplied. As such, in the seed step, under a state where the step of supplying the H.sub.2 gas is performed, the step of supplying the DCS gas and the step of supplying the DS gas may be alternately performed", emphasis added).
Regarding claim 29, the method of claim 1, wherein the first pressure is in a range of 277 to 1,200 Pa (Orihashi ¶ [0097]: 250 Pa to 350 Pa), and the second pressure is in a range of 1,333 to 13,322 Pa (Orihashi ¶ [0096]: P1 exceeds 1000 Pa).
Regarding claim 31, the method of claim 29, wherein the seed layer is formed at a temperature of 350 to 450 degrees C (Orihashi ¶ [0101], ¶ [0063]).
Regarding claim 36, the method of claim1, wherein the reducing gas is a deuterium gas or a monosilane gas (Orihash ¶ [0108] : deuterium gas and/or MS gas).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) as applied to claim 1 above, and further in view of Huang (US 6,265,267 B1).
Regarding claim 6, Kakkad et al. teach the limitations of claim 1, wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1),
wherein in (b), the second film is a film doped with a dopant (¶ [0011], 0034: n-type or p-type dopants).
However, Kakkad et al. do not teach the method further comprising: (e) oxidizing at least one portion, where the dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before performing (d).
Huang, in the same field of invention, teaches a method comprising:
(e) oxidizing (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portion of 222b; see Huang Fig. 3C; Column 5, Line 41), where the dopant is present (Huang Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film ( 218; see Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad et al. in view of Huang teaches the crystallizing step; see Kakkad: ¶ [0021], Fig. 6: Step annealing step 62) and before performing (d) (Column 5, Lines 61-32: 226 is removed by wet-etching; also see Kakkad: ¶ [0031]: etched away partially or entirely; ¶ [0032]: wet etching or dry etching of SiO2 formed after annealing and optional oxidization step).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et at to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer (222a) transforms it to be a “more loosely packed” layer compared to the undoped first film (218) (see Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures as embodied in Huang Fig. 3D.
Claims 14 are rejected under 35 U.S.C. 103 as being unpatentable over Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) as applied to claim 1 above, and further in view of Yabuhara (US 2008/0237686 A1)
Regarding claim 14, Kakkad et al. teach the limitations of claim 1. However, Kakkad et al. do not teach a method of processing a substrate wherein a thickness of the second film is made equal to or thicker than a thickness of the first film.
Yabuhara, in the same field of invention, teaches a method of manufacturing a semiconductor device that requires a Phosphorus-doped amorphous second silicon film (80; see Fig. 4A and ¶ [0033]) formed on top of an undoped amorphous silicon first film (70; ¶ [0033]) and then subjected to annealing to form a polycrystalline film (600; see Fig. 4B ¶ 0035) and wherein a thickness (T8; see Fig. 4A) of the second film is made equal to or thicker (Fig. 4A shows T8 is thicker than T7) than a thickness (T7) of the first film.
A person of ordinary skill in the art, prior to the effective date of the invention, will find it obvious to combine the teachings Yabuhara into the method of Kakkad et al., wherein the thickness of the second film is made equal to or thicker than that of the first film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of designing a semiconductor devices such as thin-film-transistors, short-channel devices (Kakkad: ¶ [0033]-[0054]), or non-volatile semiconductor memory devices having gate electrodes made of polycrystalline silicon (Yabuhara: ¶ [0005]) such that the grain size of the polycrystalline silicon is made larger by increasing the thickness of the second film deposited prior to the annealing step (Yabuhara: Fig. 1; ¶ [0012], [0016]-[0017]). Having a larger grain size will then result in reducing electrical interference between adjacent floating gate electrodes and variations of threshold and/or operating voltages can be restrained (Yabuhara ¶ [0041]). Hence, increasing the thickness of the second film leads to device performance optimization and smaller over-all device size (Yabuhara ¶ [0041]).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) as applied to claim 1 above, and further in view of Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1).
Regarding claim 23, Kakkad et al. teach the method of Claim 1,
wherein in (a), the first film is a film not doped with a dopant (Kakkad ¶ [0021]: undoped a-Si film 1), and
wherein in (b), the second film is a film doped with the dopant (¶ [0011], 0034: n-type or p-type dopants).
However, Kakkad et al. do not teach the method further comprising:
(e) modifying at least one portion, wherein a dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before performing (d), in such a manner that a non-doped portion of the first film is not modified;
Huang, in the same field of invention, teaches a method comprising:
(e) modifying (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portion of 222b; see Fig. 3C; Column 5, Line 41), where a dopant is present (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad teaches the crystallizing step in Kakkad et al. in view of Huang) and before performing (d) (the removing at least the second film 222b through wet-etching; see Column 5, Lines 61-63), in such a manner that a non-doped portion (portions of 218 below 222b) of the first film 218 is not modified (Column 6, Lines 1-4: "to remove the poly-oxide layer 222b without removing the gate oxide layers 218, 226 formed in the thermal process"),
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et al. to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step of Kakkad, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer 222a transforms it to be a "more loosely packed" layer compared to the undoped first film 218. (Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures such as embodied in Huang Fig. 3D.
However, Kakkad et al. do not teach the method wherein in (e), the at least one portion is modified by supplying a modifying gas including a mixture of O-containing gas and H-containing gas.
Horita, In the same field of invention, teaches a method wherein in (e), the at least one portion is modified by supplying a modifying gas (¶ [0072]: oxidizing gas supplied to wafer 200) including a mixture of O-containing gas and H-containing gas (¶ [0073]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Horita into the method of Kakkad in et al. to supply the modifying gas to include a mixture of O-containing gas and H-containing gas in order during the modifying process of step (e). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of enhancing the oxidizing power of the modifying gas (Horita ¶ [0073]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) as applied to claim 1 above, and further in view of Wang (US 2021/0118687 A1).
Regarding claim 24, Kakkad et al. teach the method of Claim 1, but do not teach: wherein the etching agent includes a fluorine-based gas.
Wang, in the same field of invention, teaches a method wherein the etching agent includes a fluorine-based gas (¶ [0025]).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wang into the method of Kakkad et al. to remove the second film wherein the etching agent includes a fluorine-based gas. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of substituting the wet etching process of Kakkad (see ¶ [0032]) with the process of Wang in order to have a better etch selectivity rate to each away an oxide layer (140, see Wang Fig. 1) against other film layers on the substrate (Wang: abstract).
Claims 32 and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) as applied to claim 31, and further in view of Cheng (US 2019/0019724 A1).
Regarding claim 32, Kakkad et al. teach the method of claim 31, but do not teach: the first film is formed at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa, and the second film is formed at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa in (b).
Cheng, in the same field of invention, teaches a method of forming a first film (¶ [0023]: amorphous silicon film) and a second film (¶ [0024]: doped amorphous silicon film) wherein the forming of the first film at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa (¶ [0025]: 150 to 500 C and 100 mTorr to 350 Torr, which is 13 Pa to 46,662 Pa) and the forming of the second film at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa (¶ [0025]: 150 to 500 C and 100 mTorr to 350 Torr, which is 13 Pa to 46,662 Pa).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Cheng into the method of Kakkad et al. to form the first film at a temperature of 450 to 550 degrees C and at a pressure of 30 to 400 Pa and to form the second film at a temperature of 450 to 500 degrees C and at a pressure of 30 to 400 Pa, when doing step (b). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of substituting the PECVD deposition process of Kakkad that deposits the undoped amorphous first film and the doped amorphous second film with a suitable deposition process such as CVD, PECVD, ALD, PEALD (Cheng ¶ [0022]), which generally require subjecting the substrate to several precursor gases (Cheng ¶ [0023], ¶ [0024]) in a chamber (310, Fig. 3, ¶ [0033]) at the abovementioned temperature and pressure conditions.
Regarding claim 33, the method of Claim 1, wherein the seed layer, the first film and the second film are crystallized at a temperature of 550 to 650 degrees C (Kakkad ¶ [0024]-[0028]: 600 C to 650 C ) and at a pressure of 1 to 101,325 Pa (Kakkad ¶ [0008] and claim 14: annealing for crystallization is at 650 C and 1 atm, which is 101,325 Pa).
Claim 34 are rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1) and Cheng (US 2019/0019724 A1) as applied to claim 33 above, and further in view of Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1).
Regarding claim 34, Kakkad et al. teach the method of claim 33. However, Kakkad et al. do not teach the method comprising:
(e) modifying at least one portion, where a dopant is present, in at least one selected from the group of the first film and the second film after performing (c) and before (d), in such a manner that a non-doped portion of the first film is not modified,
wherein the first film is not doped with the dopant and the second film is doped with the dopant.
Huang, in the same field of invention, teaches a method comprising:
(e) modifying (Column 5, Line 41: thermally oxidize doped polysilicon layer 222a into 222b) at least one portion (portions of 222b; see Fig. 3C; Column 5, Line 41), where a dopant is present (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD), in at least one selected from the group of the first film (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film (222b) after performing (c) (Kakkad teaches the crystallizing step in Kakkad et al. in view of Huang) and before performing (d) (the removing at least the second film 222b through wet-etching; see Column 5, Lines 61-63), in such a manner that a non-doped portion (portions of 218 below 222b) of the first film 218 is not modified (Column 6, Lines 1-4: "to remove the poly-oxide layer 222b without removing the gate oxide layers 218, 226 formed in the thermal process"),
wherein the first film is not doped with the dopant (218; Column 4, Line 30-34 discloses 218 is made of undoped oxidized silicon) and the second film is doped with the dopant (Column 5, Lines 24-27: polysilicon layer 222a is the formed… ions are being doped in-situ by CVD).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Huang into the method of Kakkad et al. to insert a thermal oxidizing step to modify the doped second film but not the undoped first film after crystallizing the first and second films and before etching the second film. The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of using the oxidizing process to improve the etch selectivity of the doped second film, prior to the etching step of Kakkad, while keeping the selectivity of the undoped first film the same, noting that Huang teaches that thermally oxidizing the doped polysilicon layer 222a transforms it to be a "more loosely packed" layer compared to the undoped first film 218. (Huang Column 5, Lines 61-67; Column 6, Lines 1-11). This teaching enables the skilled artisan to form desired transistor structures such as embodied in Huang Fig. 3D.
However, Kakkad et al. do not teach the method wherein the at least one portion is modified at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa in (e).
Horita, in the same field of invention, teaches a method wherein the at least one portion is modified at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa (¶ [0055], ¶ [0062]: 600 to 900 C; ¶ [0069]: 133 to 1000 Pa; see also Fig. 4).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Horita into the method of Kakkad et al. to modify the at least one portion of the substrate at a temperature of 500 to 800 degrees C and at a pressure of 1 to 101,325 Pa while performing step (e). The ordinary artisan would have been motivated to modify Kakkad et al. in the manner set forth above for at least the purpose of shortening the time required for the modifying process to oxidize the amorphous film (Horita ¶ [0087]), for increasing the etching rate of the oxidized amorphous film (Horita, Fig. 8, ¶ [0105] and Fig. 10, ¶ [0114]) and for improving the quality of the film forming process (Horita ¶ [0048]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable by Kakkad (US 2007/0004185 A1) in view of Orihashi (US 2017/0263441 A1), Cheng (US 2019/0019724 A1), Huang (US 6,265,267 B1) and Horita (US 2019/0214250 A1) as applied to claim 34 above, and further in view of Wang (US 2021/0118687 A1).
Regarding claim 35, Kakkad et al. teach the method of Claim 34, but do not teach: wherein at least the second film is removed at a temperature of room temperature to 1,000 degrees C and at a pressure of 133 to 50,000 Pa in (d).
Wang, in the same field of invention, teaches a method wherein at least the second film is removed at a temperature of room temperature to 1,000 degrees C and at a pressure of 133 to 50,000 Pa (¶ [0025]: 0 to 200 C and 0.1 to 20 Torr, which is 13 Pa to 2666 Pa).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wang into the method of Kakkad et al. to remove at least the second film at a temperature of room temperature to 1000 C and at a pressure of 133 to 50000 Pa when performing step (d). The ordinary artisan would have been motivated to modify Kakkad in view of Huang, Orihashi, and Cheng in the manner set forth above for at least the purpose of substituting the wet etching process of Kakkad (see ¶ [0032]) with the etching process of Wang in order to have a better etch selectivity rate to each away an oxide layer (140, see Wang Fig. 1) against other film layers on the substrate (Wang: abstract).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached on (571) 272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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