DETAILED ACTION
This Office action is in response to the filing of this application on 23 February 2022. Claims 1-20 are pending in the application
Related U.S. Application Data
This application is a continuation-in-part of U.S. patent application Ser. No. 16/537,564, filed on Aug. 10, 2019, now U.S. Pat, No. 12,362,219; which is a continuation-in-part of U.S. patent application Ser. No. 15/460,230, filed on Mar. 16, 2017, now U.S. Pat. No. 10,497,713; which is a continuation-in-part of U.S. patent application Ser. No. 14/821,683, filed on Aug. 7, 2015, now U.S. Pat. No. 9,613,844; which is a continuation-in-part of U.S. patent application Ser. No. 13/492,395, filed on Jun. 8, 2012, now U.S. Pat. No. 9,136,153; which is a continuation of U.S. patent application Ser. No. 13/273,712, filed Oct. 14, 2011, now U.S. Pat. No. 8,273,610; which is a continuation-in-part of U.S. patent application Ser. No. 13/016,313, filed on Jan. 28, 2011, now U.S. Pat. No. 8,362,482; which is a continuation-in-part of U.S. patent application Ser. No. 12/970,602, filed on Dec. 16, 2010, now U.S. Pat. No. 9,711,407; which is a continuation-in-part of U.S. patent application Ser. No. 12/949,617, filed on Nov. 18, 2010, now U.S. Pat. No. 8,754,533, which is a continuation-in-part of U.S. patent application 12/900,379, filed on October 07, 2010, now U.S. Patent 8,395,191.
This application is also a continuation-in-part of U.S. patent application Ser. No. 17/542,492, filed on Dec. 5, 2021, now U.S. Patent 11,482,440; which is a continuation-in-part of U.S. patent application Ser. No. 17/233,503, filed on Apr. 18, 2021, now U.S. Pat. No. 11,217,472; which is a continuation-in-part of U.S. patent application Ser. No.16/537,564, filed on Aug. 10, 2019, now abandoned.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Terminal Disclaimer
The terminal disclaimer filed on 24 February 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of any patent granted on Application Serial No. 17/693,282 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 7, 11, 12, and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation "said second transistor channel" in line 2. There is insufficient antecedent basis for this limitation in the claim, since claim 1, from which claim 6 depends, recites “second transistors channel”.
Claim 7 recites the limitation "said second transistor channel" in line 9. There is insufficient antecedent basis for this limitation in the claim, since claim 1, from which claim 7 depends, recites “second transistors channel”.
Claim 11 recites the limitation "said third transistors" in lines 5-6 There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "said at least one of third transistors" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim.
Claim 15 recites the limitation "said third transistors" in line 7 There is insufficient antecedent basis for this limitation in the claim.
Claims 16-20 are rejected, since they inherit the indefiniteness of the claims from which they depend.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in a patent granted on an application for patent by another filed in the United States before the invention thereof by the applicant for patent, or on an international application by another who has fulfilled the requirements of paragraphs (1), (2), and (4) of section 371(c) of this title before the invention thereof by the applicant for patent.
The changes made to 35 U.S.C. 102(e) by the American Inventors Protection Act of 1999 (AIPA) and the Intellectual Property and High Technology Technical Amendments Act of 2002 do not apply when the reference is a U.S. patent resulting directly or indirectly from an international application filed before November 29, 2000. Therefore, the prior art date of the reference is determined under 35 U.S.C. 102(e) prior to the amendment by the AIPA (pre-AIPA 35 U.S.C. 102(e)).
Claims 1-20 are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Or-Bach et al., US 2011/0108888, of record.
The applied reference has a common inventor with the instant application. Based upon the pre-AIA 35 U.S.C. 102(e) date of the reference, it constitutes prior art. This rejection under pre-AIA 35 U.S.C. 102(e) might be overcome either by a showing under 37 CFR 1.132 that any invention disclosed but not claimed in the reference was derived from the inventor or joint inventors (i.e., the inventive entity) of this application and is thus not the invention “by another,” or if the same invention is not being claimed, by an appropriate showing under 37 CFR 1.131(a).
With respect to claim 1, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
first transistors channel M1 and M2 disposed atop of said second metal layer 5342 (middle PMOS transistors, shown in Fig. 53D), see paragraph [0759];
second transistors channel M8-M10 disposed atop of said second transistors M1 and M2 (top NMOS transistors, shown in Fig. 53D);
wherein at least one of said second transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material, see paragraph [0648];
wherein said first transistors channel is aligned to said second transistors channel with less than 40 nm misalignment, see paragraph [0306]. Or-Bach et al. disclose that a metal such as aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082], which exhibits high temperature resistance and can withstand high temperatures.
The present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a metal based metal gate (see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082]). Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
With respect to claim 2, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type.
With respect to claim 3, Or-Bach et al. disclose that the channel of a junction-less transistor comprise a gate all around, see paragraph [0380].
With respect to claim 4, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors.
With respect to claim 5, Or-Bach et al. disclose that said second transistors channel M1 and M2 and said first transistors M8-M10 are self-aligned, being processed following a same lithography step, as shown in Fig. 53E, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 6, Or-Bach et al. disclose a third metal layer 5308 overlaying said second transistors channel M8-M10 (top NMOS transistors, shown in Fig. 53D.
With respect to claim 7, Or-Bach et al. disclose a third metal layer 5308 overlaying said second transistors channel M8-M10 (top NMOS transistors, shown in Fig. 53D), a via 5324 as part of a connection path between said third metal layer 5308 and said second metal layer 5342, wherein said via diameter is less than 400 nm, as shown in annotated Fig. 53E below, see paragraph [0777], [0895], [0749], and [1053].
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With respect to claim 8, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
first transistors M1 and M2 disposed atop of said second metal layer 5342 (middle PMOS transistors, shown in Fig. 53D), see paragraph [0759];
second transistors M8-M9 disposed atop of said first transistors M1 and M2 (top NMOS transistors, shown in Fig. 53D),
wherein at least one of said second transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material,
a third metal layer 5308 overlaying said second transistors channel M8-M10 (top NMOS transistors, shown in Fig. 53D),
a via 5324 as part of a connection path between said third metal layer 5308 and said second metal layer 5342,
wherein said via diameter is less than 400 nm, as shown in annotated Fig. 53E below, see paragraph [0777], [0895], [0749], and [1053].
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The present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a metal based metal gate. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
With respect to claim 9, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type.
With respect to claim 10, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0329].
With respect to claim 11, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors M10 (top NMOS transistors, shown in Fig. 53D).
With respect to claim 12, Or-Bach et al. shows in Fig. 53E that said forming at least one of second transistors and said forming at least one of third transistors comprise both said at least one of second transistors and said at least one of third transistors being processed following a same lithography step, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 13, Or-Bach et al. disclose that tungsten has a high temperature resistance, can be used as a high resistance multiple-level interconnect to connect together transistors, and can withstand high temperature processing, see paragraphs [0607], [0726], and [0730]. Therefore, the first metal layer 5320 and the second metal layer 5342can comprise tungsten.
With respect to claim 14, Or-Bach et al. disclose that the channel of a junction-less transistor comprise a gate all around, see paragraph [0380].
With respect to claim 15, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
first transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0759];
second transistors M8-M10 disposed atop of said first transistors;
wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material (Or-Bach et al. disclose that aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082]);
wherein said second transistors are aligned to said first single crystal transistors, as shown in Fig. 53E, with less than a 40 nm error, see paragraph [0306] (Or-Bach et al. disclose that transistors have less than a 40 nm alignment error.);
wherein said device comprise a bonding layer (STI oxide), see paragraph [0280].
The present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a tungsten based metal gate. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
With respect to claim 16, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type.
With respect to claim 17, Or-Bach et al., shows in Fig. 53E, disclose aid forming at least one of second transistors and said forming at least one of first transistors comprise both said at least one of second transistors and said at least one of first transistors being processed following a same lithography step, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 18, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said first transistors.
With respect to claim 19, Or-Bach et al. disclose a third metal layer 5308 overlaying said second transistors channel M8-M10 (top NMOS transistors, shown in Fig. 53D), a via 5324 as part of a connection path between said third metal layer 5308 and said second metal layer 5342, wherein said via diameter is less than 400 nm, as shown in annotated Fig. 53E below, see paragraph [0777], [0895], [0749], and [1053].
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With respect to claim 20, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0329].
Response to Arguments
Applicant's arguments filed 24 February 2026 have been fully considered but they are not persuasive. In light of the filing of the terminal disclaimer on 24 February 2026, the provisional rejection on the grounds of non-statutory double patenting over co-pending application Serial No. 17/693,282 has been withdrawn.
The previous rejection based on Or-Bach et al., US 2011/0108888 was made under 35 USC 103, since Or-Bach et al. dis not teach “a distance from at least one of said third transistors to at least one of said second transistors is less than 1 micron, as required in independent claims 1, 8, and 15. However, this limitation has been cancelled from the above-identified claims. Hence claims 1-20 have been rejected as anticipated by Or-Bach et al., US 2011/0108888, in this Office action.
Applicant has argued that Or-Bach et al., US 2011/0108888, is not effective as a 102 reference against the instant application, since it fails the test of being published before the instant’s EFD. However, Or-Bach et al., US 2011/0108888, is available as a 102 reference against the instant application, since it has an effective filing date before that of the instant application and is “by another”, since Or-Bach et al., US 2011/0108888, names Israel Beinglass and J. L. de Jong as inventors, in addition to Or-Bach, Cronquist, and Sekar.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898