Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 11-20 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Korea Patent No.: 1020160143280 (hereinafter `280) [using machine’s translation language] in view of LEE et al. (Pub. No.: US 2017/0179037) (hereinafter LEE) and further in view of Jung (Patent No.: 10229953) and Ahn (Patent No.: US 10522780).
Re claim 1, `280, FIG. 5 teaches a display device comprising:
a first substrate (350);
a second substrate (332) disposed on the first substrate;
at least one inorganic layer (324, ¶ [0126]) disposed on the second substrate; the second substrate (332) being disposed between the at least one inorganic layer (324) and the first substrate (350);
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a semiconductor layer (322+336, note that 336 could be a semiconductor material such as polysilicon as teaches in LIU below) with a channel region (322) disposed on and above each of the at least one inorganic layer (324), the second substrate (332), and the first substrate (350), the at least one inorganic layer (324) being disposed between the semiconductor layer (322+336) and the second substrate (350);
a lower gate insulating layer (324) disposed on the semiconductor layer;
a gate electrode (330) disposed on the lower gate insulating layer;
a light-emitter (D=364/362/360, [0142]) disposed on and above the source electrode and the drain electrode (334/336),
wherein the second substrate (332) is in direct contact with the at least one inorganic layer (324, note that “324 may be made of an inorganic insulating material such as silicon oxide or silicon nitride”, [0126]).
`280 fails to disclose a second substrate comprising a plurality of voids and a porous dielectric layer is having dielectric constant less that inorganic layer of silicon oxide material.
LEE teaches a second substrate comprising a plurality of voids (150) and a porous dielectric layer is having dielectric constant (silicon oxide having porous) less that inorganic layer of silicon oxide material (150, Fig. 3, ¶ [0027]).
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of optimizing performance of individual IC dies as taught by LEE, [0027].
Moreover, after the combining of `280 and LEE would teach wherein the second substrate has a dielectric constant less than a dielectric constant of the at least one inorganic layer because the pores (air) reducing the dielectric constant.
In re claim 1, `280, FIG. 5 fails to teach a semiconductor channel layer disposed on and above each of the at least one inorganic layer, the second substrate, and the first substrate.
Jung teaches a semiconductor channel layer (211) disposed on and above each inorganic layer (103), the second substrate (102), and the first substrate (101).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the light visibility of the display device by implementing the colored polymer substrate as taught by Jung, BACKGROUND.
Furthermore, `280/Jung fails to teach an upper gate insulating layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the upper gate insulating layer; and
Ahn, FIG. 18 teaches an upper gate insulating layer (190, col. 7, lines 1-12) disposed on the gate electrode (170); and a source electrode and a drain electrode (210/230) disposed on the upper gate insulating layer (190).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing or minimizing a coupling effect between wirings in a pixel circuit.as taught by Ahn, col. 1, lines 33-42.
Re claim 2, in the combination, LEE teaches the display device of claim 1, wherein the voids in the second substrate comprise pores having a porosity in the range of about 10% to about 40% (150, Fig. 3, ¶ [0027]).
Re claim 3, in the combination, LEE, Fig. 3 teaches the display device of claim 1, wherein the second substrate has a dielectric constant of about 2 to about 3 (porous silicon oxide dielectric constant, ¶ [0027]), and the at least one inorganic layer has a dielectric constant of about 3.5 or less (normal SiO2 dielectric constant).
Re claim 4, in the combination, LEE and `280, FIG. 5 teaches the display device of claim 1, wherein the first substrate (332) comprises at least one non-porous base substrate, and the second substrate (332 with material of 150 of LEE) comprises at least one porous sub-substrate including the plurality of voids (150, Fig. 3, ¶ [0027]).
Re claim 5, in the combination, LEE, Fig. 3 teaches the display device of claim 3, wherein the at least one inorganic layer comprises a polymer resin or a silica-based material, and
wherein the silica-based material comprises one selected from the group consisting of: porous silica, HSQ, OSG, and FSG; and the polymer resin comprises one selected from the group consisting of: PTFE, BPDA-PDA, PAE, SiLK, BCB, Parylene-N, and Parylene-F (150, [0027]).
Re claim 6, in the combination, LEE, Fig. 3 teaches the display device of claim 3, wherein the at least one inorganic layer comprises a plurality of voids (“porous organic series material”, [0027]).
Re claim 7, in the combination, LEE, Fig. 3 teaches the display device of claim 3, wherein the at least one inorganic layer comprises at least one of fluorine, boron, phosphorus, arsenic and argon (“FSG (SiOF series material)”, [0027]).
Re claim 8, in the combination, LEE, Fig. 3 teaches the display device of claim 1, wherein the first substrate comprises a first base substrate (350/366) and a second base substrate disposed on the first base substrate, and wherein the second substrate (332) is disposed on the second base substrate (310/320/324).
Re claim 11, in the combination, `280, FIG. 5 teaches the display device of claim 1, wherein the at least one inorganic layer (324) comprises at least one barrier layer (322) and at least one buffer layer (336) disposed on the at least one barrier layer.
Re claim 12, in the combination, LEE and `280, FIG. 5 teaches the display device of claim 1, wherein the second substrate (332) comprises a plurality of recesses (porous) formed on at least one surface.
Re claim 13, in the combination, `280, FIG. 5 teaches the display device of claim 1, wherein the light-emitter comprises an organic light-emitting diode [0003].
Re claim 14, `280, FIG. 5 teaches a display device comprising:
a plurality of base substrates (350/366);
a first sub-substrate (332) disposed on the plurality of base substrates;
at least one inorganic layer (324) disposed on the base substrates, the first sub-substrate (332) being disposed between the at least one inorganic layer (324) and the base substrates (350/366);
a semiconductor channel layer (322) disposed on each of the at least one inorganic layer (324), the first sub-substrate (332), and the plurality of base substrates (350/324), the at least one inorganic layer (324) being disposed between the semiconductor layer (322+336) and the first sub-substrate (332);
a lower gate insulating layer (324) disposed on the semiconductor layer;
a gate electrode (330) disposed on the lower gate insulating layer;
a light-emitter (D=364/362/360, [0142]) disposed on and above the source electrode and the drain electrode (334/336),
wherein the first sub-substrate (332) is in direct contact with the at least one inorganic layer (324, note that “324 may be made of an inorganic insulating material such as silicon oxide or silicon nitride”, [0126]).
`280 fails to disclose a first sub-substrate comprising a plurality of voids and a porous dielectric layer is having dielectric constant less that inorganic layer of silicon oxide material.
LEE teaches a first sub-substrate comprising a plurality of voids (150) and a porous dielectric layer is having dielectric constant (silicon oxide having porous) less that inorganic layer of silicon oxide material (150, Fig. 3, ¶ [0027]).
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of optimizing performance of individual IC dies as taught by LEE, [0027].
Moreover, after the combining of `280 and LEE would teach wherein the first sub-substrate has a dielectric constant less than a dielectric constant of the at least one inorganic layer.
In re claim 14, `280, FIG. 5 fails to teach a semiconductor channel layer region disposed on and above each of inorganic layer, the first sub-substrate, and the plurality of base substrates.
Jung teaches a semiconductor channel layer (211) region disposed on and above each of inorganic layer (103), the first sub-substrate (102a), and the plurality of base substrates (102b/101).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of enhancing the light visibility of the display device by implementing the colored polymer substrate as taught by Jung, BACKGROUND.
Furthermore, `280 fails to teach an upper gate insulating layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the upper gate insulating layer.
Ahn, FIG. 18 teaches an upper gate insulating layer (190, col. 7, lines 1-12) disposed on the gate electrode (170); and
a source electrode and a drain electrode (210/230) disposed on the upper gate insulating layer 190).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing or minimizing a coupling effect between wirings in a pixel circuit.as taught by Ahn, col. 1, lines 33-42.
Re claim 15, in the combination, LEE teaches the display device of claim 14, the voids in the first sub-substrate comprise pores having a porosity ranging from about 10% to about 40% (150, Fig. 3, ¶ [0027]).
Re claim 16, in the combination, `280, FIG. 5 teaches the display device of claim 14, wherein the first sub-substrate has a dielectric 2 constant of about 2 to about 3 (porous silicon oxide dielectric constant, ¶ [0027]), and the at least one inorganic layer has a dielectric constant of 3 about 3.5 or less (normal SiO2 dielectric constant).
Re claim 17, in the combination, LEE, Fig. 3 teaches the display device of claim 16, wherein the at least one inorganic layer comprises a polymer resin or a silica-based material, and wherein the silica-based material comprises one selected from the group consisting of: porous silica, HSQ, OSG and FSG; and the polymer resin comprises one selected from the group consisting of: PTFE, BPDA-PDA, PAE, SiLK, BCB, Parylene-N, and Parylene-F (“FSG (SiOF series material)”, [0027]).
Re claim 18, in the combination, LEE, Fig. 3 teaches the display device of claim 16, wherein the at least one inorganic layer comprises a plurality of voids (“porous organic series material”, [0027]).
Re claim 19, in the combination, LEE, Fig. 3 teaches the display device of claim 16, wherein the at least one inorganic layer includes at least one of fluorine, boron, phosphorus, arsenic and argon (“FSG (SiOF series material)”, [0027]).
Re claim 20, in the combination, `280, FIG. 5 teaches the display device of claim 14, wherein the plurality of base substrates (350/366) comprises a first base substrate (350) and a second base substrate (320/310) disposed on the first base substrate, and wherein the first sub-substrate (332) is disposed between the first base substrate (350/366) and the second base substrate (320/310).
Re claim 22, in the combination, `280, FIG. 5 teaches the display device of claim 14, wherein the light-emitter comprises an organic light-emitting diode (D=364/362/360).
Claim(s) 9-10 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over `280 in view of LEE/Jung/Ahn and further in view of Gronbeck et al. (Pub. No.: US 2004/0130032) (hereinafter Gronbeck).
`280/LEE/Jung/Ahn teaches all the limitation of claim 1/20.
`280/LEE/Jung/Ahn fails to teach the limitation of claim 9-10/21.
Gronbeck, Fig. 3B teaches a third substrate (120, ¶ [0075]) disposed between the first base substrate (105) and the second base substrate (130), wherein the third substrate comprises a plurality of voids (note that porous materials are including a plurality of voids, [0023]) (claim 9).
wherein each of the first base substrate (105), the second base substrate, the second substrate (130) and the third substrate (120) comprises a polyimide resin [0003] (claim 10).
a second sub-substrate (130) disposed on the second base substrate (125/130/135), wherein the second sub-substrate comprises a plurality of voids (of pores 130) (claim 21).
It would have been for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing crosstalk or capacitive coupling, and also to increase the speed of signal propagation as taught by Gronbeck, [0002].
Claim(s) 1, 4, 8, 11-12, 14 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jung (Patent No.: 10229953) in view of Ahn.
Re claim 1, Jung, FIG. 4 teaches a display device comprising:
a first substrate (101);
a second substrate (101a/102b, note that 102b layer is the same as layer 2 of FIG. 2 wherein it is including a porous material which is containing voids or pores, col. 5, lines 20-25) disposed on the first substrate and comprising a plurality of voids;
at least one inorganic layer (103, note that 103 lack carbon-hydrogen bond, therefore, it is considered as an inorganic material, col. 6, lines 20-25) disposed on the second substrate, the second substrate (102) being disposed between the at least one inorganic layer (103) and the first substrate (101);
a semiconductor channel layer (211) disposed on and above each inorganic layer (103), the second substrate (102), and the first substrate (101), the at least one inorganic layer being disposed between the semiconductor layer and the second substrate;
a lower gate insulating layer (212) disposed on the semiconductor layer;
a gate electrode (213) disposed on the lower gate insulating layer; and
a light-emitter (218/219/220) disposed on and above the source electrode and the drain electrode,
wherein the second substrate (102b) is in direct contact with the at least one inorganic layer (103) and has a dielectric constant (dielectric constant of polyimide typically ranges from 5.0 to 6.0, col. 5, lines 45-47) less than a dielectric constant of the at least one inorganic layer (dielectric constant of silicon nitride typically ranges from 7.0 to 9.0 col. 6, lines 20-25).
Re claim 14, Jung, FIG. 4 teaches a display device comprising:
a plurality of base substrates (102b/101);
a first sub-substrate (102a) disposed on the plurality of base substrates and comprising a plurality of voids;
at least one inorganic layer (103) disposed on the base substrates, the first sub-substrate (102a) being disposed between the at least one inorganic layer (103) and the base substrates (102b/101);
a semiconductor channel layer (211) region disposed on and above each of inorganic layer (103), the first sub-substrate (102a), and the plurality of base substrates (102b/101), the at least one inorganic layer (103) being disposed between semiconductor channel layer (211) and the first sub- substrate (102a);
a lower gate insulating layer (212) disposed on the semiconductor channel layer;
a gate electrode (213) disposed on the lower gate insulating layer; and
a light-emitter (218/219/220) disposed on and above the source electrode (215a) and the drain electrode (215b),
wherein the first sub-substrate (102a) is in direct contact with the at least one inorganic layer (103) and has a dielectric constant (dielectric constant of polyimide typically ranges from 5.0 to 6.0, col. 5, lines 45-47) less than a dielectric constant of the at least one inorganic layer (dielectric constant of silicon nitride typically ranges from 7.0 to 9.0 col. 6, lines 20-25).
In re claims 1 and 14, Jung fails to teach an upper gate insulating layer disposed on the gate electrode; and a source electrode and a drain electrode disposed on the upper gate insulating layer.
Ahn, FIG. 18 teaches an upper gate insulating layer (190, col. 7, lines 1-12) disposed on the gate electrode (170); and
a source electrode and a drain electrode (210/230) disposed on the upper gate insulating layer (190).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of reducing or minimizing a coupling effect between wirings in a pixel circuit.as taught by Ahn, col. 1, lines 33-42.
Re claim 4, in the combination, Jung, FIG. 4 teaches the display device of claim 1, wherein the first substrate comprises at least one non-porous base substrate (101), and the second substrate comprises at least one porous sub-substrate including the plurality of voids (101a/102b, note that 102b layer is the same as layer 2 of FIG. 2 wherein it is including a porous material which is containing voids or pores, col. 5, lines 20-25).
Re claim 8, Jung, FIG. 4 teaches the display device of claim 1, wherein the first substrate (102b/101) comprises a first base substrate (102b) and a second base substrate (102a) disposed on the first base substrate, and wherein the second substrate (102) is disposed on the second base substrate.
Re claim 11, Jung, FIG. 4 teaches the display device of claim 1, wherein the at least one inorganic layer comprises at least one barrier layer and at least one buffer layer disposed on the at least one barrier layer (“The barrier layer 103 can be multilayer films”, col. 6, lines 20-25).
Re claim 12, Jung, FIG. 4 teaches the display device of claim 1, wherein the second substrate comprises a plurality of recesses formed on at least one surface (102b, note that 102b layer is the same as layer 2 of FIG. 2 wherein it is including a porous material which is containing voids or pores, col. 5, lines 20-25).
Re claim 13/22, Jung, FIG. 4 teaches the display device of claim 1/14, wherein the light-emitter comprises an organic light-emitting diode (Abstract).
Response to Arguments
Applicant's arguments filed 02/25/2026 have been fully considered but they are moot due to a new ground of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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