Attorney Docket Number: 0941-4636PUS2
Filing Date: 3/03/2022 (Claimed PRO Date of 10/13/2021)
Inventors: Chen et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendment filed 1/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The amendment filed on 1/09/2026, responding the Office action mailed on 10/09/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendment
Applicant’s amendments to the claims have overcome the claim rejections under 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 10/09/2025. Applicant amended claims 1-2, 5, and 11, cancelled claims 7-8, and 12, and added new claims 26-28. Accordingly, pending in this application are claims 1-5, 9-16, and 21-28. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, and 27 are rejected under 35 U.S.C. 103 over Thomas (US 20230037957 A1) in view of Kim (US 20220293730 A1).
Regarding claim 1, Thomas (see, e.g., fig. 11) shows most aspects of the instant invention including a semiconductor device structure comprising:
A plurality of nanostructures (e.g., nanoribbons 101a) stacked over a substrate (e.g., substrate 101a, see, e.g., massive 101a layer of fig. 11) in a vertical direction,
A first bottom layer (e.g., source region 109) formed adjacent to the first nanostructures (e.g., nanoribbons 101a) wherein the first bottom layer (e.g., source region 109) comprises Si, SiGe or a combination thereof (see, e.g., paragraph 35 “The source and drain regions 109-110 and 113-114 can be any suitable semiconductor material and may include any dopant scheme”) of Si or SiGe (see, e.g., paragraph 35 “For instance, source and drain regions 109-110…include, for example, group IV semiconductor materials such as silicon, germanium, SiGe…”);
A gate structure (e.g., gate structure 116 + gate structure 122) surrounding the first nanostructures (e.g., nanoribbons 101a);
A first source/drain (S/D) structure (e.g., source region 113) formed over the first bottom layer (e.g., source region 109), wherein the first bottom layer (e.g., source region 109) is separated from at least one of the first nanostructures (e.g., nanoribbons 101a) by the first S/D structure (e.g., source region 113).
Thomas (see, e.g., fig. 11), however, fails to show wherein a bottommost surface of the first bottom layer is lower than a bottommost surface of the gate structure.
Kim (see, e.g., fig. 3A), in a similar device to Thomas, teaches a bottommost surface (e.g., bottommost surface of SD2) of a bottom layer (e.g., source/drain region 2) is lower than a bottommost surface of a gate structure (e.g., main gate portion 160M of gate line 160).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the depth extension source/drain configuration of Kim within the configuration of Thomas, in order to allow a cross section between the source region, drain region, and lower substrate semiconductor body, providing a potential additional channel region within the device.
Regarding claim 2, Thomas (see, e.g., fig. 11) shows a first dielectric layer (e.g., isolation structure 111) formed over the first bottom layer (e.g., source region 109), and an inner space (e.g., gate spacers 105c) between the gate structure (e.g., gate structure 116) and the first S/D structure (e.g., source region 113), wherein the inner spacer (e.g., gate spacer 105c) is in direct contact with the first dielectric layer (e.g., isolation structure 111).
Regarding claim 3, Thomas (see, e.g., fig. 11) shows a top surface of the first dielectric layer (e.g., isolation structure 111) is lower than a top surface of the inner spacer (e.g., gate spacer 105c).
Regarding claim 4, Thomas (see, e.g., fig. 11) shows a height of the inner spacer (e.g., gate spacer 105c) is greater than a height of the first dielectric layer (e.g., isolation structure 111).
Regarding claim 5, Thomas (see, e.g., fig. 11) shows the first dielectric layer (e.g., isolation structure 111) is higher than a bottommost nanostructure of the first nanostructures (e.g., nanoribbons 101a).
Regarding claim 9, Thomas (see, e.g., fig. 11) shows the first bottom layer (e.g., paragraph 32: 109…may…include, for example… germanium tin (GeSn)) and the substrate (e.g., paragraph 37: includes…alternating levels of silicon… and SiGe…) are made of different materials.
Regarding claim 10, Thomas (see, e.g., fig. 11) shows a top surface of the first bottom layer (e.g., source region 109) is higher than a bottommost nanostructure of the first nanostructures (e.g., nanoribbons 101a).
Regarding claim 27, Thomas (see, e.g., fig. 11) shows wherein a bottom surface of the first dielectric layer (e.g., isolation structure 111) is aligned (e.g., note that isolation structure 111 protrudes downward and is aligned with the top surface of a left-most nanoribbon 101a) with a top surface of one of the first nanostructures (e.g., nanoribbons 101a).
Claims 11 and 13-15 are rejected under 35 U.S.C. 103 over Balakrishnan (US 9837414 B1) in view of Suh (US 11810964 B2).
Regarding claim 11, Balakrishnan (see, e.g., fig. 12) shows most aspects of the instant invention including a semiconductor device comprising:
a substrate (e.g., semiconductor substrate 10), wherein the substrate (e.g., semiconductor substrate 10) comprises a first region (e.g., region corresponding to leftmost transistor) and a second region (e.g., region corresponding to rightmost transistor);
a plurality of first nanostructures (e.g., leftmost semiconductor nanowires 62) stacked over the first region (e.g., region corresponding to leftmost transistor) in a vertical direction;
a first bottom layer (e.g., leftmost epitaxial semiconductor region 50) adjacent to the first nanostructures (e.g., leftmost semiconductor nanowires 62);
a first source/drain (S/D) structure (e.g., leftmost epitaxial S/D region 54) formed over the first bottom layer (e.g., leftmost epitaxial semiconductor region 50);
A plurality of second nanostructures (e.g., rightmost semiconductor nanowires 62) stacked over the second region (e.g., region corresponding to rightmost transistor) in a vertical direction;
A second bottom layer (e.g., rightmost epitaxial semiconductor region 50) formed adjacent to the second nanostructures (e.g., rightmost semiconductor nanowires 62);
A second source/drain (S/D) structure (e.g., rightmost epitaxial S/D region 54) formed over the second bottom layer (e.g., rightmost epitaxial semiconductor region 50), and a first thickness (see, e.g., left-side green bar in annotated fig. 1) of the first S/D structure (e.g., leftmost epitaxial S/D region 54) is smaller (see, e.g., annotated fig. 1) than a second thickness (see, e.g., right-side green bar in annotated fig. 1) of the second S/D structure (e.g., rightmost epitaxial S/D region 54).
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Annotated Fig. 1
Balakrishnan (see, e.g., fig. 12), however, fails to show wherein the first bottom layer comprises a curved bottom surface.
Suh (see, e.g., fig. 2), in a similar device to Balakrishnan, teaches a first (e.g., first layer 47A) or second layer (second layer 47B) comprises a curved bottom surface (see, e.g., curved bottom surface of 47 in fig. 2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the curved shape of Suh within the bottom layer of Balakrishnan, in order to allow protrusion into part of the substrate surface using a curved geometry, providing a larger surface area of interfacial contact between the substrate and the bottom layer.
Regarding claim 13, Balakrishnan (see, e.g., fig. 12) shows a first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) formed over the first bottom layer (e.g., epitaxial semiconductor region 50), a first gate structure (e.g., gate functional stack 74) surrounding the first nanostructures (e.g., leftmost semiconductor nanowires 62) and an inner spacer (e.g., gate dielectric 72) between the first gate structure (e.g., functional gate stack 74) and the first S/D structure (e.g., leftmost epitaxial S/D region 54), wherein the inner spacer (e.g., gate dielectric 72) is in direct contact with the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”).
Regarding claim 14, Balakrishnan (see, e.g., fig. 12) shows a height of the inner spacer (e.g., gate dielectric 72) is greater than a height of the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”).
Regarding claim 15, Balakrishnan (see, e.g., fig. 12) shows wherein an interface between the first bottom layer (e.g., epitaxial semiconductor region 50) and the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) is higher than a bottommost nanostructure (e.g., bottommost nanowire 62 of first nanostructures) of the first nanostructures (e.g., leftmost semiconductor nanowires 62).
Claim 26 is rejected under 35 U.S.C. 103 over Thomas in view of Kim further in view of Cheng (US 11538720 B2).
Regarding claim 26, Thomas in view of Kim fails to teach a first number of the first nanostructures higher than a top surface of the first dielectric layer is greater than a second number of the first nanostructures lower than the top surface of the first dielectric layer.
Cheng (see, e.g., fig. 10), in a similar device to Thomas in view of Kim, teaches a first number of nanostructures (e.g., nanosheets 106 over top surface of 702) higher than a top surface of a first dielectric layer (e.g., dielectric material 702) is greater than a second number of the first nanostructures (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the higher-nanosheet-number-over-dielectric configuration of Cheng within the device of Thomas in view of Kim, in order to achieve the expected result of providing additional nanosheet functionality in another area of the device as desired.
In addition, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to duplicate the nanosheets above the top surface of the dielectric layer of Thomas in view of Kim in order to achieve the expected result of increasing the nanosheet density and improving the performance characteristics within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Claim 28 is rejected under 35 U.S.C. 103 over Balakrishnan in view of Suh further in view of Cheng.
Regarding claim 13, Balakrishnan (see, e.g., fig. 12) shows a first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) formed over the first bottom layer (e.g., epitaxial semiconductor region 50).
Balakrishnan in view of Suh, however, fails to teach wherein a first number of the first nanostructures higher than a top surface of the first dielectric layer is greater than a second number of the first nanostructures lower than the top surface of the first dielectric layer.
Cheng (see, e.g., fig. 10), in a similar device to Balakrishnan in view of Suh, teaches a first number of nanostructures (e.g., nanosheets 106 over top surface of 702) higher than a top surface of a first dielectric layer (e.g., dielectric material 702) is greater than a second number of the first nanostructures (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the higher-nanosheet-number-over-dielectric configuration of Cheng within the device of Balakrishnan in view of Suh, in order to achieve the expected result of providing additional nanosheet functionality in another area of the device as desired.
In addition, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to duplicate the nanosheets above the top surface of the dielectric layer of Balakrishnan in view of Suh in order to achieve the expected result of increasing the nanosheet density and improving the performance characteristics within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Allowable Subject Matter
Claim 16 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 21-25 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 21, the closest identified prior art, Balakrishnan (US 9837414 B1)(see, e.g., fig. 12) shows most aspects of the semiconductor device structure.
However, Balakrishnan fails to disclose or suggest wherein a first height of the first S/D structure is different from a second height of the second S/D structure.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814