Attorney Docket Number: 0941-4636PUS2
Filing Date: 3/03/2022 (Claimed PRO Date of 10/13/2021)
Inventors: Chen et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the RCE amendments filed 6/24/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued
examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the
finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's
submission filed on 6/24/2026 has been entered.
Amendment Status
The RCE submission filed on 6/24/2026 as an amendment in reply to the Office action mailed on
3/25/2026 has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this Office action are claims 1-5, 9-11, 13-16, and 21-28.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 26 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 26 recites the limitation "the first dielectric layer" in lines 3-4. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9-10, and 26-27 are rejected under 35 U.S.C. 103 over Thomas (US 20230037957 A1) in view of Cheng (US 11538720 B2) further in view of Kim (US 20220293730 A1).
Regarding claim 1, Thomas (see, e.g., fig. 11) shows most aspects of the instant invention including a semiconductor device structure comprising:
A plurality of nanostructures (e.g., nanoribbons 101a) stacked over a substrate (e.g., substrate 101a, see, e.g., massive 101a layer of fig. 11) in a vertical direction,
A first bottom layer (e.g., source region 109) formed adjacent to the first nanostructures (e.g., nanoribbons 101a) wherein the first bottom layer (e.g., source region 109) comprises Si, SiGe or a combination thereof (see, e.g., paragraph 35 “The source and drain regions 109-110 and 113-114 can be any suitable semiconductor material and may include any dopant scheme”) of Si or SiGe (see, e.g., paragraph 35 “For instance, source and drain regions 109-110…include, for example, group IV semiconductor materials such as silicon, germanium, SiGe…”);
A gate structure (e.g., gate structure 116 + gate structure 122) surrounding the first nanostructures (e.g., nanoribbons 101a);
A first source/drain (S/D) structure (e.g., source region 113) formed over the first bottom layer (e.g., source region 109), wherein the first bottom layer (e.g., source region 109) is separated from at least one of the first nanostructures (e.g., nanoribbons 101a) by the first S/D structure (e.g., source region 113).
While the current embodiment of Thomas fails to explicitly show a number of first nanostructures connecting the first bottom layer is smaller than a number of the first nanostructures connecting the first S/D structure, an alternate embodiment of Thomas (see, e.g., paragraph 23) teaches either of the channel regions can comprise a larger quantity of nanostructures (see, e.g., paragraph 23 “Other examples may include fewer nanoribbons 101a per channel region (e.g., one or two), or more nanoribbons 101a per channel region (e.g., five or six)” – note the current embodiment shows 4 nanoribbons within the channel region).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the six-nanostructure embodiment of Thomas within the upper channel region, in order to achieve the expected result of increasing the nanostructure stacking density within the upper region as desired.
In addition, Cheng (see, e.g., fig. 10), in a similar device to Thomas, teaches a first number of nanostructures (e.g., nanosheets 106 over top surface of 702) higher than a top surface of a first dielectric layer (e.g., dielectric material 702) is greater than a second number of the first nanostructures (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the higher-nanosheet-number-over-dielectric configuration of Cheng within the device of Thomas, in order to achieve the expected result of providing additional nanosheet functionality in another area of the device as desired. In addition, it also would have been obvious to one of ordinary skill in the art to duplicate the nanostructures within the channel region, in order to increase the effective channel footprint and improving performance characteristics within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art.
Thomas (see, e.g., fig. 11) in view of Cheng, however, fails to show wherein a bottommost surface of the first bottom layer is lower than a bottommost surface of the gate structure.
Kim (see, e.g., fig. 3A), in a similar device to Thomas in view of Cheng, teaches a bottommost surface (e.g., bottommost surface of SD2) of a bottom layer (e.g., source/drain region 2) is lower than a bottommost surface of a gate structure (e.g., main gate portion 160M of gate line 160).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the depth extension source/drain configuration of Kim within the configuration of Thomas in view of Cheng, in order to allow a cross section between the source region, drain region, and lower substrate semiconductor body, providing a potential additional channel region within the device.
Regarding claim 2, Thomas (see, e.g., fig. 11) shows a first dielectric layer (e.g., isolation structure 111) formed over the first bottom layer (e.g., source region 109), and an inner space (e.g., gate spacers 105c) between the gate structure (e.g., gate structure 116) and the first S/D structure (e.g., source region 113), wherein the inner spacer (e.g., gate spacer 105c) is in direct contact with the first dielectric layer (e.g., isolation structure 111).
Regarding claim 3, Thomas (see, e.g., fig. 11) shows a top surface of the first dielectric layer (e.g., isolation structure 111) is lower than a top surface of the inner spacer (e.g., gate spacer 105c).
Regarding claim 4, Thomas (see, e.g., fig. 11) shows a height of the inner spacer (e.g., gate spacer 105c) is greater than a height of the first dielectric layer (e.g., isolation structure 111).
Regarding claim 5, Thomas (see, e.g., fig. 11) shows the first dielectric layer (e.g., isolation structure 111) is higher than a bottommost nanostructure of the first nanostructures (e.g., nanoribbons 101a).
Regarding claim 9, Thomas (see, e.g., fig. 11) shows the first bottom layer (e.g., paragraph 32: 109…may…include, for example… germanium tin (GeSn)) and the substrate (e.g., paragraph 37: includes…alternating levels of silicon… and SiGe…) are made of different materials.
Regarding claim 10, Thomas (see, e.g., fig. 11) shows a top surface of the first bottom layer (e.g., source region 109) is higher than a bottommost nanostructure of the first nanostructures (e.g., nanoribbons 101a).
Regarding claim 26, Cheng (see, e.g., fig. 10), teaches a first number of nanostructures (e.g., nanosheets 106 over top surface of 702) higher than a top surface of the first dielectric layer (e.g., dielectric material 702) is greater than a second number of the first nanostructures (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the higher-nanosheet-number-over-dielectric configuration of Cheng within the device of Thomas in view of Cheng further in view of Kim, in order to achieve the expected result of providing additional nanosheet functionality in another area of the device as desired. Also see the comments regarding the rejection of claim 1, which are considered to be relevant here.
Regarding claim 27, Thomas (see, e.g., fig. 11) shows wherein a bottom surface of the first dielectric layer (e.g., isolation structure 111) is aligned (e.g., note that isolation structure 111 protrudes downward and is aligned with the top surface of a left-most nanoribbon 101a) with a top surface of one of the first nanostructures (e.g., nanoribbons 101a).
Claims 11 and 13-15 are rejected under 35 U.S.C. 103 over Balakrishnan (US 9837414 B1) in view of Suh (US 11810964 B2) further in view of Sharma (US 20200235246 A1).
Regarding claim 11, Balakrishnan (see, e.g., fig. 12) shows most aspects of the instant invention including a semiconductor device comprising:
a substrate (e.g., semiconductor substrate 10), wherein the substrate (e.g., semiconductor substrate 10) comprises a first region (e.g., region corresponding to leftmost transistor) and a second region (e.g., region corresponding to rightmost transistor);
a plurality of first nanostructures (e.g., leftmost semiconductor nanowires 62) stacked over the first region (e.g., region corresponding to leftmost transistor) in a vertical direction;
a first bottom layer (e.g., leftmost epitaxial semiconductor region 50) adjacent to the first nanostructures (e.g., leftmost semiconductor nanowires 62);
a first source/drain (S/D) structure (e.g., leftmost epitaxial S/D region 54) formed over the first bottom layer (e.g., leftmost epitaxial semiconductor region 50);
A plurality of second nanostructures (e.g., rightmost semiconductor nanowires 62) stacked over the second region (e.g., region corresponding to rightmost transistor) in a vertical direction;
A second bottom layer (e.g., rightmost epitaxial semiconductor region 50) formed adjacent to the second nanostructures (e.g., rightmost semiconductor nanowires 62);
A second source/drain (S/D) structure (e.g., rightmost epitaxial S/D region 54) formed over the second bottom layer (e.g., rightmost epitaxial semiconductor region 50), a first sidewall surface (e.g., sidewall of first S/D structure touching nanostructures) of the first S/D structure (e.g., leftmost epitaxial S/D region 54), interfaces with the first nanostructures (e.g., leftmost semiconductor nanowires 62), and a second sidewall surface (e.g., sidewall of second S/D structure touching nanostructures) interfaces with the second nanostructures (e.g., rightmost semiconductor nanowires 62).
PNG
media_image1.png
321
512
media_image1.png
Greyscale
Annotated Fig. 1
Balakrishnan (see, e.g., fig. 12), however, fails to show wherein the first bottom layer comprises a curved bottom surface, and the first sidewall surface of the first S/D structure is smaller than a second thickness of the second sidewall surface of the second S/D structure.
Suh (see, e.g., figs. 3-7), in a similar device to Balakrishnan, teaches a first (e.g., first layer 47A) or second layer (second layer 47B) comprises a curved bottom surface (see, e.g., curved bottom surface of 47 in fig. 2).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the curved shape of Suh within the bottom layer of Balakrishnan, in order to allow protrusion into part of the substrate surface using a curved geometry, providing a larger surface area of interfacial contact between the substrate and the bottom layer.
Sharma (see, e.g., fig. 4), in a similar device to Balakrishnan in view of Suh, teaches a first height of a first S/D structure (e.g., second S/D region 333) is different from a second height of a second S/D structure (e.g., S/D region 331).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the asymmetric S/D configuration (see, e.g., the asymmetry of the setup within figure 4) of Sharma within the device of Balakrishnan in view of Suh, in order to manipulate the current driving profile and resistance within certain regions of the transistor, improving drive current within the device as desired.
Regarding claim 13, Balakrishnan (see, e.g., fig. 12) shows a first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) formed over the first bottom layer (e.g., epitaxial semiconductor region 50), a first gate structure (e.g., gate functional stack 74) surrounding the first nanostructures (e.g., leftmost semiconductor nanowires 62) and an inner spacer (e.g., gate dielectric 72) between the first gate structure (e.g., functional gate stack 74) and the first S/D structure (e.g., leftmost epitaxial S/D region 54), wherein the inner spacer (e.g., gate dielectric 72) is in direct contact with the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”).
Regarding claim 14, Balakrishnan (see, e.g., fig. 12) shows a height of the inner spacer (e.g., gate dielectric 72) is greater than a height of the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”).
Regarding claim 15, Balakrishnan (see, e.g., fig. 12) shows wherein an interface between the first bottom layer (e.g., epitaxial semiconductor region 50) and the first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) is higher than a bottommost nanostructure (e.g., bottommost nanowire 62 of first nanostructures) of the first nanostructures (e.g., leftmost semiconductor nanowires 62).
Claims 16 is rejected under 35 U.S.C. 103 over Balakrishnan in view of Suh further in view of Sharma, Thomas, and Cheng.
Regarding claim 16, Balakrishnan in view of Suh further in view of Sharma fails to teach wherein the first dielectric layer is in direct contact with a bottommost nanostructure of the first nanostructures.
Thomas (see, e.g., fig. 11), in a similar device to Balakrishnan in view of Suh further in view of Sharma, teaches a first dielectric layer (e.g., isolation structure 111 + paragraph 30 “…isolation structure 111 is silicon dioxide…”) is in direct contact with a nanostructure (see, e.g., contact between protruding portion of isolation structure 111 and nanoribbon 101a).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the geometry of the first dielectric layer of Thomas within the first dielectric layer of Balakrishnan in view of Suh further in view of Sharma, in order to achieve the expected result of providing additional electrical isolation protection connected to the nanostructure while still maintaining the connectivity to the lower epitaxial regions.
Balakrishnan in view of Suh further in view of Sharma and Thomas, however, fails to teach the first dielectric layer makes direct contact with the bottommost nanostructure of the first nanostructures.
Cheng (see, e.g., fig. 10), in a similar device to Balakrishnan in view of Suh further in view of Sharma and Thomas, teaches a single nanostructure (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the single nanostructure setup of Cheng within the arrangement of Balakrishnan in view of Suh further in view of Sharma and Thomas, in order to achieve the expected result of reducing the cost of fabrication while manufacturing the device by reducing the underlying nanostructure footprint.
Claim 28 is rejected under 35 U.S.C. 103 over Balakrishnan in view of Suh further in view of Sharma and Cheng.
Regarding claim 28, Balakrishnan (see, e.g., fig. 12) shows a first dielectric layer (e.g., ILD layer 58 filling void 56 + insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material…”) formed over the first bottom layer (e.g., epitaxial semiconductor region 50).
Balakrishnan in view of Suh further in view of Sharma, however, fails to teach wherein a first number of the first nanostructures higher than a top surface of the first dielectric layer is greater than a second number of the first nanostructures lower than the top surface of the first dielectric layer.
Cheng (see, e.g., fig. 10), in a similar device to Balakrishnan in view of Suh further in view of Sharma, teaches a first number of nanostructures (e.g., nanosheets 106 over top surface of 702) higher than a top surface of a first dielectric layer (e.g., dielectric material 702) is greater than a second number of the first nanostructures (e.g., individual nanosheet 106 under top surface of 702) lower than a top surface of the first dielectric layer (e.g., dielectric material 702).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the higher-nanosheet-number-over-dielectric configuration of Cheng within the device of Balakrishnan in view of Suh further in view of Sharma, in order to achieve the expected result of providing additional nanosheet functionality in another area of the device as desired.
In addition, it would have been obvious to one of ordinary skill in the art before the effective
filing date of the invention to duplicate the nanosheets above the top surface of the dielectric layer of Balakrishnan in view of Suh further in view of Sharma in order to achieve the expected result of increasing the nanosheet density and improving the performance characteristics within the device, since it has been held that a mere duplication of working parts of a device involves only routine skill in the art. In re Harza 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04.
Claims 21-25 are rejected under 35 U.S.C. 103 over Balakrishnan in view of Sharma.
Regarding claim 21, the closest identified prior art, Balakrishnan (see, e.g., fig. 12) shows most aspects of the semiconductor device structure comprising:
a substrate (e.g., semiconductor substrate 10), wherein the substrate comprises a first region (e.g., region corresponding to leftmost transistor) and a second region (e.g., region corresponding to rightmost transistor);
a plurality of first nanostructures (e.g., leftmost semiconductor nanowires 62) stacked over the first region (e.g., region corresponding to leftmost transistor) in a vertical direction;
a first dielectric layer (e.g., void 56 + paragraph 53) adjacent to the first nanostructures (e.g., leftmost semiconductor nanowires 62);
a first source/drain (S/D) structure (e.g., leftmost epitaxial S/D region 54) formed over the first dielectric layer (e.g., void 56 + paragraph 53);
a plurality of second nanostructures (e.g., rightmost semiconductor nanowires 62) stacked over the second region (e.g., region corresponding to rightmost transistor) in a vertical direction;
a second dielectric layer (e.g., rightmost insulator layer 52 + paragraph 49 “The insulator layer 52 may include a dielectric material”) formed adjacent to the second nanostructures (e.g., rightmost semiconductor nanowires 62), wherein the first dielectric layer (e.g., void 56 + paragraph 53) is higher than the second dielectric layer (e.g., rightmost insulator layer 52); and
a second source/drain (S/D) structure (e.g., rightmost epitaxial S/D region 54) formed over the second dielectric layer (e.g., rightmost insulator layer 52)
Balakrishnan (see, e.g., fig. 12), however, fails to show wherein a first height of the first S/D structure is different from a second height of the second S/D structure.
Sharma (see, e.g., fig. 4), in a similar device to Balakrishnan, teaches a first height of a first S/D structure (e.g., second S/D region 333) is different from a second height of a second S/D structure (e.g., S/D region 331).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the asymmetric height configuration of Sharma within the device of Balakrishnan, in order to manipulate the current driving profile and resistance within certain regions of the transistor, improving drive current within the device as desired.
Regarding claim 22, Balakrishnan (see, e.g., fig. 12) shows a first gate structure (e.g., gate functional stack 74) surrounding the first nanostructures (e.g., leftmost semiconductor nanowires 62), and an inner spacer (e.g., gate dielectric 72) between the first gate structure (e.g., functional gate stack 74) and the first S/D structure (e.g., leftmost epitaxial S/D region 54), wherein the inner spacer (e.g., gate dielectric 72) is in direct contact with the first dielectric layer (e.g., void 56 + paragraph 53)
Regarding claim 23, Balakrishnan (see, e.g., fig. 12) shows a top surface of a first dielectric layer (e.g., void 56 + paragraph 53) is higher than a top surface of the bottommost first nanostructure (e.g., bottommost semiconductor wires 62).
Regarding claim 24, Sharma (see, e.g., fig. 4) teaches wherein a bottom surface of the first S/D structure (e.g., second S/D region 333) is higher (see, e.g., fig. 4, T1 and T3) than a bottom surface of the second S/D structure (e.g., S/D region 331).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the asymmetric height configuration of Sharma within the device of Balakrishnan in view of Sharma, in order to manipulate the current driving profile and resistance within certain regions of the transistor, improving drive current within the device as desired. Also see the comments above regarding the rejection of claim 21, which are considered to be relevant here.
Regarding claim 25, Balakrishnan (see, e.g., fig. 12) shows wherein a top surface of the first dielectric layer (e.g., void 56 + paragraph 53) is lower than a topmost surface of the inner spacer (e.g., gate dielectric 72).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and ttps://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Prosecution Insights