DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 23 Jan 2026 for application number 17/686,074. The Office hereby acknowledges receipt of the following and placed of record in file: Applicant Arguments/Remarks, and Claims.
Claims 1-15, 21-22, and 24-26 are presented for examination (Examiner notes that claim 15 has been withdrawn).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Arguments towards claim 1 are moot, as claim 1 is allowable.
Regarding claim 10, Wang teaches A semiconductor device structure, comprising:
a plurality of first nanostructures [channel layer 202; Fig. 17, paras 0111-0112] over a substrate [substrate 200; Fig. 17, paras 0111-0112];
a gate structure [gate electrode layer 225/work function layer 224; Fig. 17, paras 0111-0112] surrounding the first nanostructures [202], wherein the gate structure [225/224] comprises a gate dielectric [224; para 0115 discloses 224 may be tantalum nitride, which may be a dielectric] and a gate electrode [225] on the gate dielectric [224];
a hard mask layer [dummy gate dielectric layer 205; Fig. 17, para 0058]; and
a first gate spacer [first sidewall spacer 209; Fig. 17, para 0113] formed over the hard mask layer [205], wherein the first gate spacer [209] is interfacing with the hard mask layer [205].
However, Wang does not explicitly teach:
a metal layer formed over the gate structure; a hard mask layer adjacent to the metal layer; wherein a top surface of the metal layer is lower than a top surface of the first gate spacer.
Wang and Cartier teach a metal layer [metal gate layer 726 of Cartier; Figs. 3 & 5, para 0021] formed over the gate electrode [gate electrode of Wang; see annotated Fig. 17 below] of the gate structure [225/224 of Wang, analogously gate stack of Cartier (Figs. 3 & 5, para 0021)]; a hard mask layer [205 of Wang, analogously high-k dielectric layer 724 of Cartier; Figs. 3 & 5, para 0021] adjacent to the metal layer [726 of Cartier]; wherein a top surface of the metal layer [726 of Cartier] is lower than a top surface [top of 726 of Cartier is lower than top of 1140 of Cartier] of the first gate spacer [209 of Wang, analogously thin nitride layer 1140 of Cartier; Fig. 5, para 0022].
Regarding claim 21, Wang teaches A semiconductor device structure, comprising:
a plurality of first nanostructures [channel layer 202; Fig. 17, paras 0111-0112] over a substrate [substrate 200; Fig. 17, paras 0111-0112];
a gate structure [gate electrode layer 225/work function layer 224; Fig. 17, paras 0111-0112] surrounding a top surface of a topmost first nanostructure [topmost 202], wherein the gate structure [225/224] comprises a gate dielectric [224; para 0115 discloses 224 may be tantalum nitride, which may be a dielectric] and a gate electrode [225];
a first gate spacer layer [first sidewall spacer 209; Fig. 17, para 0113] and a second gate spacer layer [gate dielectric layer 223; Fig. 17, para 0113] formed adjacent to the gate structure [225/224], wherein a bottom surface of the second gate spacer layer [223] is lower than [there is a bottom surface of 223 that is lower than bottom surface of 209] a bottom surface of the first gate spacer layer [209]; and
a mask layer [205] formed below the first gate spacer layer [209] and the second gate spacer layer [223; 205 is below portions of 223], wherein the mask layer [205] has a step height [205 has a height, i.e. step height], wherein the mask layer [205] is spaced apart [205 is spaced apart from 225/224] from the gate dielectric [224 is spaced apart from 205] of gate structure [225/224].
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 21-22 and 24-25 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wang (US 2022/0005931 A1).
In reference to claim 21, Wang teaches A semiconductor device structure, comprising:
a plurality of first nanostructures [channel layer 202; Fig. 17, paras 0111-0112] over a substrate [substrate 200; Fig. 17, paras 0111-0112];
a gate structure [gate electrode layer 225/work function layer 224; Fig. 17, paras 0111-0112] surrounding a top surface of a topmost first nanostructure [topmost 202], wherein the gate structure [225/224] comprises a gate dielectric [224; para 0115 discloses 224 may be tantalum nitride, which may be a dielectric] and a gate electrode [225];
a first gate spacer layer [first sidewall spacer 209; Fig. 17, para 0113] and a second gate spacer layer [gate dielectric layer 223; Fig. 17, para 0113] formed adjacent to the gate structure [225/224], wherein a bottom surface of the second gate spacer layer [223] is lower than [there is a bottom surface of 223 that is lower than bottom surface of 209] a bottom surface of the first gate spacer layer [209]; and
a mask layer [205] formed below the first gate spacer layer [209] and the second gate spacer layer [223; 205 is below portions of 223], wherein the mask layer [205] has a step height [205 has a height, i.e. step height], wherein the mask layer [205] is spaced apart [205 is spaced apart from 225/224] from the gate dielectric [224 is spaced apart from 205] of the gate structure [225/224].
In reference to claim 22, Wang teaches The semiconductor device structure as claimed in claim 21, further comprising: an S/D structure [source/drain doped layer 218; Fig. 17, para 0097] formed adjacent to the gate structure [225/224], wherein the S/D structure [218] is in direct contact with the mask layer [205].
In reference to claim 24, Wang teaches The semiconductor device structure as claimed in claim 21, further comprising: a dielectric feature [dielectric layer 219; Fig. 17, para 0099] adjacent to the gate structure [225/224], wherein a top surface of the dielectric feature [219] is higher than [top of 219 higher than 205] a top surface of the mask layer [205].
In reference to claim 25, Wang teaches The semiconductor device structure as claimed in claim 21, wherein a thickness of the mask layer [205] is smaller than [thickness of 205 is smaller than thickness of 202] a thickness of one of the first nanostructures [202].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 10-14 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2022/0005931 A1) in view of Cartier et al. [hereinafter as Cartier] (US 2009/0039426 A1).
In reference to claim 10, Wang teaches A semiconductor device structure, comprising:
a plurality of first nanostructures [channel layer 202; Fig. 17, paras 0111-0112] over a substrate [substrate 200; Fig. 17, paras 0111-0112];
a gate structure [gate electrode layer 225/work function layer 224; Fig. 17, paras 0111-0112] surrounding the first nanostructures [202], wherein the gate structure [225/224] comprises a gate dielectric [224; para 0115 discloses 224 may be tantalum nitride, which may be a dielectric] and a gate electrode [225] on the gate dielectric [224];
a hard mask layer [dummy gate dielectric layer 205; Fig. 17, para 0058]; and
a first gate spacer [first sidewall spacer 209; Fig. 17, para 0113] formed over the hard mask layer [205], wherein the first gate spacer [209] is interfacing with the hard mask layer [205].
However, Wang does not explicitly teach:
a metal layer formed over the gate electrode of the gate structure; a hard mask layer adjacent to the metal layer; wherein a top surface of the metal layer is lower than a top surface of the first gate spacer.
Wang and Cartier teach a metal layer [metal gate layer 726 of Cartier; Figs. 3 & 5, para 0021] formed over the gate electrode [gate electrode of Wang; see annotated Fig. 17 below] of the gate structure [225/224 of Wang, analogously gate stack of Cartier (Figs. 3 & 5, para 0021)]; a hard mask layer [205 of Wang, analogously high-k dielectric layer 724 of Cartier; Figs. 3 & 5, para 0021] adjacent to the metal layer [726 of Cartier]; wherein a top surface of the metal layer [726 of Cartier] is lower than a top surface [top of 726 of Cartier is lower than top of 1140 of Cartier] of the first gate spacer [209 of Wang, analogously thin nitride layer 1140 of Cartier; Fig. 5, para 0022].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Wang and Cartier before the effective filing date of the claimed invention, to include the metal layer as disclosed by Cartier into the semiconductor device of Wang in order to obtain a semiconductor device with a metal layer over a gate structure.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with a metal layer over a gate structure to provide the predictable result of maintaining performance, power efficiency, and reliability in electrically connecting semiconductor components.
PNG
media_image1.png
366
606
media_image1.png
Greyscale
In reference to claim 11, Wang and Cartier teach the invention of claim 10.
Wang teaches The semiconductor device structure as claimed in claim 10, further comprising: an S/D structure [218] formed adjacent to the gate structure [225/224], wherein the S/D structure [218] is in direct contact with the hard mask layer [205].
In reference to claim 12, Wang and Cartier teach the invention of claim 11.
Wang teaches The semiconductor device structure as claimed in claim 11, further comprising: an inner spacer layer [217] formed between the gate structure [225/224] and the S/D structure [218], wherein the hard mask layer [205] is between the inner spacer layer [217] and the first gate spacer [209].
In reference to claim 13, Wang and Cartier teach the invention of claim 10.
Wang teaches The semiconductor device structure as claimed in claim 10, further comprising: a second gate spacer [223] adjacent to the first gate spacer [209], wherein the second gate spacer [223] is in direct contact with the hard mask layer [205].
In reference to claim 14, Wang and Cartier teach the invention of claim 13.
Wang teaches The semiconductor device structure as claimed in claim 13, wherein a bottom surface of the second gate spacer [223] is lower than [there is a bottom surface of 223 that is lower than bottom surface of 209] a bottom surface of the first gate spacer [209].
In reference to claim 26, Wang teaches the invention of claim 21.
However, Wang does not explicitly teach The semiconductor device structure as claimed in claim 21, further comprising: a metal layer formed over the gate structure, wherein a bottom surface of the metal layer is lower than the bottom surface of the second gate spacer layer.
Wang and Cartier teach The semiconductor device structure as claimed in claim 21, further comprising: a metal layer [metal gate layer 726 of Cartier; Figs. 3 & 5, para 0021] formed over the gate structure [225/224 of Wang, analogously gate stack of Cartier (Figs. 3 & 5, para 0021)], wherein a bottom surface of the metal layer [726 of Cartier] is lower than the bottom surface [bottom of 726 of Cartier is lower than bottom of 1242 of Cartier] of the second gate spacer layer [223 of Wang, analogously oxide layer 1242 of Cartier; Fig. 5, para 0024].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Wang and Cartier before the effective filing date of the claimed invention, to include the metal layer as disclosed by Cartier into the semiconductor device of Wang in order to obtain a semiconductor device with a metal layer over a gate structure.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with a metal layer over a gate structure to provide the predictable result of maintaining performance, power efficiency, and reliability in electrically connecting semiconductor components.
Allowable Subject Matter
Claims 1-9 are allowed.
The following is an examiner’s statement of reasons for allowance:
The Examiner has carefully considered independent claim 1. The prior art of record, alone or in combination, does not teach or fairly suggest the following limitations in claim 1:
“a plurality of first nanostructures stacked over a substrate in a vertical direction;
a gate structure surrounding the first nanostructures, wherein the gate structure comprises a gate dielectric and a gate electrode on the gate dielectric;
an S/D structure adjacent to the gate structure;
an inner spacer layer formed between the gate structure and the S/D structure;
a hard mask layer formed over the inner spacer layer, wherein the hard mask layer is between the gate structure and the S/D structure; and
a metal layer formed over the gate structure, wherein a bottom surface of the metal layer interfaces the gate electrode of the gate structure, and a sidewall surface of the metal layer interfaces the hard mask layer”
These limitations, in specific combinations as recited in independent claim 1, define the patentability of the claims.
The dependent claims are allowed based on the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached on 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ANDREW CHUNG/
Examiner, Art Unit 2898