DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1 through 9, 12 through 14, and 16 through 21 rejected.
Present action: claims 1 through 9, 12 through 14, and 16 through 21 rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 6, 9, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0001392)
Regarding claim 1.
Lee teaches:
A light-emitting diode (LED) package (fig 2:100; [para 0021]) comprising: a housing (fig 2:101; [para 0021]) comprising an insulating material ([para 0022]), the housing (fig 2:101; [para 0021]) forming a recess (fig 2:111,121; [para 0023]) with a recess floor and one or more recess sidewalls (fig 2:115,125; [para 0025]) of the insulating material;
a lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) extending through the housing (fig 2:101; [para 0021]), wherein a portion (fig 2:119,129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) is arranged along the recess floor;
at least one LED chip (fig 2:113; [para 0032]) arranged within the recess (fig 2:111,121; [para 0023]) and electrically coupled with the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]);
a first encapsulation layer (fig 2:130; [para 0037]) arranged on the recess floor and contacting only a portion (fig 2:115; [para 0025]) of the one or more recess sidewalls (fig 2:115,125; [para 0025]) of the insulating material, the first encapsulation layer (fig 2:130; [para 0037]) on the portion (fig 2:119,129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) that is arranged along the recess floor, and on one or more sidewalls of the at least one LED chip (fig 2:113; [para 0032]), wherein the first encapsulation layer (fig 2:130; [para 0037]) covers a top surface of the at least one LED chip (fig 2:113; [para 0032]), and the top surface is positioned opposite the recess floor;
and a second encapsulation layer (fig 2:132; [para 0037]) arranged within the recess (fig 2:111,121; [para 0023]) on the first encapsulation layer (fig 2:130; [para 0037]), wherein a percentage of the first encapsulation layer (fig 1, 2:130; [para 0037]) is less than 50% of a total encapsulation (fig 1, 2:130,132; [para 0037]) that is a sum of(interpreted based on illustrated volumes in fig 1,2) of the first encapsulation layer (fig 2:130; [para 0037]) and the second encapsulation layer (fig 2:132; [para 0037]), and wherein the first encapsulation layer (fig 2:130; [para 0037]) and the second encapsulation layer (fig 2:132; [para 0037])comprise a same material ([para 0037]) and the first encapsulation layer (fig 2:130; [para 0037]) and the second encapsulation layer (fig 2:132; [para 0037]) are light-transparent to wavelengths of light ([para 0037]) generated by the at least one LED chip (fig 2:113; [para 0032]).
Lee does not teach that the weight percentage is less than 50%.
Lee teaches:
the first encapsulation layer (fig 2:130; [para 0037])
and the second encapsulation layer (fig 2:130,132; [para 0037]) comprises epoxy.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first encapsulation layer is less than 50% of the weight percentage of the total encapsulation weight because the material of the first and second encapsulation layers have the same density and the first encapsulation layer occupies less than 50% of the volume.
Regarding claim 2.
Lee teaches the LED package of claim 1, further
the percentage of the first encapsulation layer (fig 2:130; [para 0037]) is less than 25% of the total encapsulation (fig 2:130,132; [para 0037]) (interpreted based on illustrated volumes in fig 1,2).
Lee does not teach that the weight percentage is less than 25%.
Lee teaches:
the first encapsulation layer (fig 2:130; [para 0037])
and the second encapsulation layer (fig 2:130,132; [para 0037]) comprises epoxy.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first encapsulation layer is less than 25% of the weight percentage of the total encapsulation weight because the material of the first and second encapsulation layers have the same density and the first encapsulation layer occupies less than 50% of the volume.
Regarding claim 3.
Lee teaches the LED package of claim 1, further
the percentage of the first encapsulation layer (fig 2:130; [para 0037]) is in a range from 3% to 10% of the total encapsulation (fig 2:130,132; [para 0037]) (interpreted based on illustrated volumes in fig 1,2).
Lee does not teach that the weight percentage is less than 25%.
Lee teaches:
the first encapsulation layer (fig 2:130; [para 0037])
and the second encapsulation layer (fig 2:130,132; [para 0037]) comprises epoxy.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that where the first encapsulation layer is 3% to 10% of the weight percentage of the total encapsulation weight because the material of the first and second encapsulation layers have the same density and the first encapsulation layer occupies a 3% to 10% of the volume.
Regarding the weight percentages recited in claims 1, 2, and 3, differences in weight percent will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such weight percents are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph), and this weight percent has been used in similar devices in the art (see, e.g., Lee) it would have been obvious to one of ordinary skill in the art to use these values in the device.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed thickness or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 6.
Lee teaches the LED package of claim 1, further
the at least one LED chip (fig 2:113; [para 0032]) comprises a plurality of LED chips (fig 2:113,123; [para 0032]) and a first LED chip (fig 2:123; [para 0032]) of the plurality of LED chips (fig 2:113,123; [para 0032]) includes a top surface that resides within the second encapsulation layer (fig 2:132; [para 0037]).
Regarding claim 9.
Lee teaches the LED package of claim 1, further:
the at least one LED chip (fig 2:113; [para 0032]) comprises a first LED chip (fig 2:113; [para 0032]) and a second LED chip (fig 2:123; [para 0032]), and the first encapsulation layer (fig 2:130; [para 0037]) is on one or more sidewalls of the first LED chip (fig 2:113; [para 0032]) without covering one or more sidewalls of the second LED chip (fig 2:123; [para 0032]).
Regarding claim 12.
Lee teaches the LED package of claim 1, further:
comprising a curved lens ([para 0041]) on the second encapsulation layer (fig 2:132; [para 0041]).
Regarding claim 13.
Lee teaches the LED package of claim 1, further:
the second encapsulation layer (fig 2:132; [para 0041]) forms a lens shape ([para 0041]) that is positioned above the recess (fig 2:111,121; [para 0023]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 4, 5, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0001392) as applied to claim 1 and further in view of Ng (US 2012/0162979)
Regarding claim 4.
Lee teaches the LED package of claim 1, above.
Lee teaches:
the at least one LED chip (fig 2:113,123; [para 0032]) is electrically connected to a portion (fig 2:129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) with a wire bond (fig 7:117; [para 0032]),
Lee does not teach a portion of the wire bond extends from the first encapsulation layer into the second encapsulation layer.
Ng teaches:
the at least one LED chip (fig 7:720; [para 0040]) is electrically connected to a portion of the lead frame structure (fig 7:711; [para 0040]) with a wire bond (fig 7), and a portion of the wire bond extends from the first encapsulation layer (fig 7:741; [para 0040]) into the second encapsulation layer (fig 7:742; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the LED to the lead frame by a wire passing form the first encapsulant to the second encapsulant in order to avoid te formation of a through package via, thereby simplifying the structure and eliminating a step of manufacture.
Regarding claim 5.
Lee in view of Ng teaches the LED package of claim 1, above.
Lee teaches:
wherein the at least one LED chip (fig 2:113,123; [para 0032]) is electrically connected to a portion (fig 2:129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) with a wire bond (fig 7:117; [para 0032]), and a top surface of the first encapsulation layer (fig 2:130; [para 0037]) is registered with the wire bond (fig 7:117; [para 0032]).
Lee does not teach a top surface of the first encapsulation layer forms an upward protrusion that is registered with the wire bond.
Ng teaches:
the at least one LED chip (fig 7:720; [para 0040])is electrically connected to a portion of the lead frame structure (fig 7:711; [para 0040]) with a wire bond (fig 7), and a top surface of the first encapsulation layer (fig 7:741; [para 0040]) forms an upward protrusion that is registered with the wire bond (fig 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a top surface of the first encapsulation layer forms an upward protrusion that is registered with the wire bond in order to accommodate flexibility in the encapsulant fill process.
Regarding claim 7.
Lee in view of Ng teaches the LED package of claim 1, above.
Lee teaches:
a top surface of the first encapsulation layer (fig 2:130; [para 0037]) is registered with the at least one LED chip (fig 2:113,123; [para 0032]).
Lee does not teach the first encapsulation forms an upward protrusion.
Ng teaches:
a top surface of the first encapsulation layer (fig 7:741; [para 0040]) forms an upward protrusion (fig 7) that is registered with the at least one LED chip (fig 7:720; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a top surface of the first encapsulation layer forms an upward protrusion that is registered with the LED chip in order to accommodate flexibility in the encapsulant fill process.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0001392) as applied to claim 1 and further in view of Matsuda (US 2022/0102596).
Regarding claim 8.
Lee teaches the LED package of claim 1, further
Lee teaches:
the at least one LED chip comprises a first LED chip (fig 2:113; [para 0032]) and a second LED chip (fig 2:123; [para 0032]), and a top surface of the first encapsulation layer (fig 2:130; [para 0037]) between the first LED chip (fig 2:113; [para 0032]) and the second LED chip (fig 2:123; [para 0032]) is positioned at a height above the recess floor (fig 2) that above the recess floor.
Lee does not teach the height of the surface of the first encapsulant is less than the height of the first and second LED chips.
Matsuda teaches:
the at least one LED chip comprises a first LED chip (fig 5d:31; [para 0116]) and a second LED chip (fig 5d:32; [para 0116]),
and a top surface of the first encapsulation layer (fig 5d:50; [para 0111]) between the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) is positioned at a height above the recess floor that is less than a height of the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) above the recess floor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the top surface of the first encapsulant to below the height of the first LED in order to minimize the quantity of encapsulant used.
Claim(s) 14, 16, 17, 18, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0001392) in view of Ng (US 2012/0162979)
Regarding claim 14.
Lee teaches:
A light-emitting diode (LED) package (fig 2:100; [para 0021]) comprising: a housing (fig 2:101; [para 0021]) comprising an insulating material ([para 0021]), the housing (fig 2:101; [para 0021]) forming a recess (fig 2:111,121; [para 0023]) with a recess floor and one or more recess sidewalls (fig 2:115,125; [para 0025]) of the insulating material;
a lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) extending through the housing (fig 2:101; [para 0021]), wherein a portion (fig 2:129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) is arranged along the recess floor;
at least one LED chip (fig 2:113; [para 0031]) arranged within the recess (fig 2:111,121; [para 0023]) and electrically coupled with the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]);
a first encapsulation layer (fig 2:130; [para 0037]) arranged on the recess floor and contacting only a portion (fig 2:115; [para 0025]) of the one or more recess sidewalls (fig 2:115,125; [para 0025]) of the insulating material, the first encapsulation layer (fig 2:130; [para 0037]) on the portion (fig 2:129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027,0028]) that is arranged along the recess floor, and on one or more sidewalls of the at least one LED chip (fig 2:113; [para 0032]), wherein the first encapsulation layer (fig 2:130; [para 0037]) is conformal along the at least one LED chip (fig 2:113; [para 0032]) such that a top surface of the first encapsulation layer (fig 2:130; [para 0037]) is registered with and above a top surface of the at least one LED chip (fig 2:113; [para 0032]);
and a second encapsulation layer (fig 2:132; [para 0037]) arranged within the recess (fig 2:111,121; [para 0023]) on the first encapsulation layer (fig 2:130; [para 0037]), wherein the first encapsulation layer (fig 2:130; [para 0037]) and the second encapsulation layer (fig 2:132; [para 0037]) comprise a same material ([para 0037]) and the first encapsulation layer (fig 2:130; [para 0037]) and the second encapsulation layer (fig 2:132; [para 0037]) are light-transparent to wavelengths of light (0037]) generated by the at least one LED chip (fig 2:113; [para 0032]).
Lee does not teach the first encapsulation forms an upward protrusion.
Ng teaches:
a top surface of the first encapsulation layer (fig 7:741; [para 0040]) forms an upward protrusion (fig 7) that is registered with and above a top surface of the at least one LED chip (fig 7:720; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for a top surface of the first encapsulation layer forms an upward protrusion that is registered with the LED chip in order to accommodate flexibility in the encapsulant fill process.
Regarding claim 16.
Lee in view of Ng teaches the LED package of claim 14, further
Lee teaches:
wherein the first encapsulation layer (fig 2:130; [para 0037]) covers the top surface of the at least one LED chip (fig 2:113; [para 0032]), and the top surface is positioned opposite the recess floor (fig 2).
Regarding claim 17.
Lee in view of Ng teaches the LED package of claim 14, further
Lee teaches:
the at least one LED chip (fig 2:113; [para 0032]) is electrically connected to a portion (fig 2:119,129; [para 0027]) of the lead frame structure (fig 2:102,103,119,129; [para 0027]) with a wire bond (fig 2:117; [para 0032]), a.
Ng teaches:
the at least one LED chip (fig 7:720; [para 0040]) is electrically connected to a portion of the lead frame structure (fig 7:711; [para 0040]) with a wire bond (fig 7), and a portion of the wire bond extends from the first encapsulation layer (fig 7:741; [para 0040]) into the second encapsulation layer (fig 7:742; [para 0040]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the LED to the lead frame by a wire passing form the first encapsulant to the second encapsulant in order to avoid te formation of a through package via, thereby simplifying the structure and eliminating a step of manufacture.
Regarding claim 18.
Lee in view of Ng teaches the LED package of claim 14, further
Lee teaches:
the at least one LED chip (fig 2:113; [para 0032]) is electrically connected to a portion of the lead frame structure (fig 2:102,103,119,129; [para 0027]) with a wire bond (fig 2:117; [para 0032]).
Ng teaches:
the at least one LED chip (fig 7:720; [para 0040]) is electrically connected to a portion of the lead frame structure (fig 7:711; [para 0040]) with a wire bond (fig 7) and the upward protrusion is registered with the wire bond (fig 7).
Regarding claim 20.
Lee in view of Ng teaches the LED package of claim 14, further:
Lee teaches:
comprising a curved lens ([para 0041]) on the second encapsulation layer (fig 2:132; [para 0041]).
Regarding claim 21.
Lee in view of Ng teaches the LED package of claim 14, further:
Lee teaches:
the second encapsulation layer (fig 2:132; [para 0041]) forms a lens shape ([para 0041]) that is positioned above the recess (fig 2:111,121; [para 0023]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2009/0001392) in view of Ng (US 2012/0162979) as applied to claim 14 and further in view of Matsuda (US 2022/0102596)
Regarding claim 19.
Lee in view of Ng teaches the LED package of claim 14, above, further
Lee teaches:
the at least one LED chip comprises a first LED chip (fig 2:113; [para 0032]) and a second LED chip (fig 2:123; [para 0032]), and a top surface of the first encapsulation layer (fig 2:130; [para 0037]) between the first LED chip (fig 2:113; [para 0032]) and the second LED chip (fig 2:123; [para 0032]) is positioned at a height above the recess floor (fig 2) that above the recess floor.
Lee does not teach the height of the surface of the first encapsulant is less than the height of the first and second LED chips.
Matsuda teaches:
the at least one LED chip comprises a first LED chip (fig 5d:31; [para 0116]) and a second LED chip (fig 5d:32; [para 0116]),
and a top surface of the first encapsulation layer (fig 5d:50; [para 0111]) between the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) is positioned at a height above the recess floor that is less than a height of the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) above the recess floor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the top surface of the first encapsulant to below the height of the first LED in order to minimize the quantity of encapsulant used.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Newly applied Lee (US 2009/0001392) and in newly applied combinations anticipates the claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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