DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/17/2026 has been entered.
Claim Status
Previous action: claims 1 through 9, 11 through 14, and 16 through 21 are rejected.
Present action: claims 1 through 9, 12 through 14, and 16 through 21 are rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 3, 4, 5, 6, 7, 9, 12, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng (US 10522518) in view of Sano (US 6603148)
Regarding claim 1.
Ng teaches:
A light-emitting diode (LED) package (fig 7:700; [column 7 lines 50-55) comprising:
a housing (fig 7:730; [column 7 lines 50-55]) that forms a recess with a recess floor and one or more recess sidewalls;
a lead frame structure (fig 7:711,712; [column 7 lines 50-55]) extending through the housing (fig 7:730; [column 7 lines 50-55]),
wherein a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) is arranged along the recess floor;
at least one LED chip (fig 7:720; [column 7 lines 50-55]) arranged within the recess and electrically coupled with the lead frame structure (fig 7:711,712; [column 7 lines 50-55]);
a first encapsulation layer (fig 7:741; [column 7 lines 55-60]) arranged on the recess floor and extending on only a portion of the one or more recess sidewalls,
the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) on the portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) that is arranged along the recess floor,
and on one or more sidewalls of the at least one LED chip (fig 7:720; [column 7 lines 50-55]),
wherein the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) covers a top surface of the at least one LED chip (fig 7:720; [column 7 lines 50-56]),
and the top surface is positioned opposite the recess floor;
and a second encapsulation layer (fig 7:747; [column 7 lines 55-60]) arranged within the recess on the first encapsulation layer (fig 7:741; [column 7 lines 55-60]),
wherein a weight percentage of the first encapsulation layer is less than 50% of a total encapsulation weight that is a sum of weights of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) and the second encapsulation layer (fig 7:741; [column 7 lines 55-60]),
and wherein the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) and the second encapsulation layer (fig 7:741; [column 7 lines 55-60]) comprise a same material (epoxy; [column 6 lines 1-10])
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Ng does not teach the encapsulation materials are transparent.
Sano teaches:
the first encapsulation layer (fig 8:75; [column 7 lines 55-65]) and the second encapsulation layer (fig 8:2; [column 7 lines 55-65])are light-transparent to wavelengths of light generated by the at least one LED chip (; [column 4 line 45, column 7 line 64]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the encapsulant to be transparent in order to avoid filler and thereby maintain a lower glass transition temperature and eliminate a component and mixing step. MPEP 2144.04.II. Ex parte Wu, 10 USPQ 2031 (Bd. Pat. App. & Inter. 1989), In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975)
Regarding claim 2.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the weight percentage of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) is less than 25% of the total encapsulation weight (741+742, estimated based upon the relative volumes illustrated in fig 7).
Sano teaches:
the weight percentage of the first encapsulation layer (fig 8:75; [column 7 lines 55-65]) is less than 25% of the total encapsulation weight (75+2, estimated based up the relative volumes illustrated in fig 8).
Regarding claim 3
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the weight percentage of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) is in a range from 3% to 10% of the total encapsulation weight (741+742, based upon an apparent volume comparison shown in figure 7)
Given the teaching of the references, it would have been obvious to determine the optimum weight of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 4.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) is electrically connected to a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) with a wire bond (annotated fig 7),
and a portion of the wire bond extends from the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) into the second encapsulation layer (fig 7:742; [column 7 lines 55-60]).
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Regarding claim 5.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) is electrically connected to a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) with a wire bond,
and a top surface of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) forms an upward protrusion that is registered with the wire bond (annotated fig 7).
Regarding claim 6.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) comprises a plurality of LED chips (fig 7:720; [column 7 lines 50-55]) and a first LED chip of the plurality of LED chips (fig 7:720; [column 7 lines 50-55]) includes a top surface that resides within the second encapsulation layer (fig 7:742; [column 7 lines 55-60]).
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Regarding claim 7.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
a top surface of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) forms an upward protrusion that is registered with the at least one LED chip (fig 7:720; [column 7 lines 50-55]).
Regarding claim 9.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) comprises a first LED chip and a second LED chip,
and the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) is on one or more sidewalls of the first LED chip without covering one or more sidewalls of the second LED chip.
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Regarding claim 12.
Ng in view of Sano teaches the structure of claim 1.
Sano teaches:
a curved lens (fig 8:3; [column 8 lines 1-5]) on the second encapsulation layer (fig 7:2; [column 7 lines 60-65])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a lens on the encapsulant in order to direct emitted light.
Regarding claim 13.
Ng in view of Sano teaches the structure of claim 1.
Sano teaches:
the second encapsulation layer (fig 8:2; [column 7 lines 60-65]) forms a lens shape (fig 8:3; [column 8 lines 1-5]) that is positioned above the recess (fig 8:43a; [column 8 lines 10-15]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a lens on the encapsulant in order to direct emitted light.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng (US 10522518) in view of Sano (US 6603148) as applied to claim 1 and further in view of Matsuda (US 2022/0102596)
Regarding claim 8.
Ng in view of Sano teaches the structure of claim 1.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) comprises a first LED chip and a second LED chip,
and a top surface of the first encapsulation layer (fig 7:741; [column 7 lines 55-60])between the first LED chip and the second LED chip is positioned at a height above the recess floor that is less than a height the second LED chip above the recess floor.
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Ng in view of Sano does not teach the top surface of the first encapsulant is less than the height of the first LED chip
Matsuda teaches:
the at least one LED chip comprises a first LED chip (fig 5d:31; [para 0116]) and a second LED chip (fig 5d:32; [para 0116]),
and a top surface of the first encapsulation layer (fig 5d:50; [para 0111]) between the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) is positioned at a height above the recess floor that is less than a height of the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) above the recess floor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the top surface of the first encapsulant to below the height of the first LED in order to minimize the quantity of encapsulant used.
Claim(s) 14, 16, 17, 18, 20, and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng (US 10522518) in view of Sano (US 6603148)
Regarding claim 14.
Ng teaches:
A light-emitting diode (LED) package (fig 7:700; [column 7 lines 50-55) comprising:
a housing (fig 7:730; [column 7 lines 50-55]) that forms a recess with a recess floor and one or more recess sidewalls;
a lead frame structure (fig 7:711,712; [column 7 lines 50-55]) extending through the housing (fig 7:730; [column 7 lines 50-55]),
wherein a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) is arranged along the recess floor;
at least one LED chip (fig 7:720; [column 7 lines 50-55]) arranged within the recess and electrically coupled with the lead frame structure (fig 7:711,712; [column 7 lines 50-55]);
a first encapsulation layer (fig 7:741; [column 7 lines 55-60]) arranged on the recess floor and extending on only a portion of the one or more recess sidewalls,
the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) on the portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) that is arranged along the recess floor,
and on one or more sidewalls of the at least one LED chip (fig 7:720; [column 7 lines 50-55]),
wherein the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) is conformal along the at least one LED chip (fig 7:720; [column 7 lines 50-55]) such that a top surface of the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) forms an upward protrusion that is registered with and above a top surface of the at least one LED chip (fig 7:720; [column 7 lines 50-55]);
and a second encapsulation layer (fig 7:747; [column 7 lines 55-60]) arranged within the recess on the first encapsulation layer (fig 7:741; [column 7 lines 55-60]),
wherein the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) and the second encapsulation layer (fig 7:747; [column 7 lines 55-60]) comprise a same material (epoxy; [column 6 lines 1-10]) .
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Ng does not teach the encapsulation materials are transparent.
Sano teaches:
the first encapsulation layer (fig 8:75; [column 7 lines 55-65]) and the second encapsulation layer (fig 8:2; [column 7 lines 55-65])are light-transparent to wavelengths of light generated by the at least one LED chip (; [column 4 line 45, column 7 line 64]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the encapsulant to be transparent in order to avoid filler and thereby maintain a lower glass transition temperature and eliminate a component and mixing step. MPEP 2144.04.II. Ex parte Wu, 10 USPQ 2031 (Bd. Pat. App. & Inter. 1989), In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975)
Regarding claim 16.
Ng in view of Sano teaches the LED package of claim 14, further
Ng teaches:
the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) covers the top surface of the at least one LED chip (fig 7:720; [column 7 lines 50-55]),
and the top surface is positioned opposite the recess floor.
Regarding claim 17.
Ng in view of Sano teaches the LED package of claim 14, further
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) is electrically connected to a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) with a wire bond (fig 7),
and a portion of the wire bond extends from the first encapsulation layer (fig 7:741; [column 7 lines 55-60]) into the second encapsulation layer (fig 7:742; [column 7 lines 55-60]).
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Regarding claim 18.
Ng in view of Sano teaches the LED package of claim 14, further
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) is electrically connected to a portion of the lead frame structure (fig 7:711,712; [column 7 lines 50-55]) with a wire bond and the upward protrusion is registered with the wire bond.
Regarding claim 20.
Ng in view of Sano teaches the LED package of claim 14, further
Sano teaches:
a curved lens (fig 8:3; [column 8 lines 1-5]) on the second encapsulation layer (fig 7:2; [column 7 lines 60-65])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a lens on the encapsulant in order to direct emitted light.
Regarding claim 21.
Ng in view of Sano teaches the structure of claim 14.
Sano teaches:
the second encapsulation layer (fig 8:2; [column 7 lines 60-65]) forms a lens shape (fig 8:3; [column 8 lines 1-5]) that is positioned above the recess (fig 8:43a; [column 8 lines 10-15]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a lens on the encapsulant in order to direct emitted light.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ng (US 10522518) in view of Sano (US 6603148) as applied to claim 14 and further in view of Matsuda (US 2022/0102596)
Regarding claim 19.
Ng in view of Sano teaches the structure of claim 14.
Ng teaches:
the at least one LED chip (fig 7:720; [column 7 lines 50-55]) comprises a first LED chip and a second LED chip,
and a top surface of the first encapsulation layer (fig 7:741; [column 7 lines 55-60])between the first LED chip and the second LED chip is positioned at a height above the recess floor that is less than a height the second LED chip above the recess floor.
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Ng in view of Sano does not teach the top surface of the first encapsulant is less than the height of the first LED chip
Matsuda teaches:
the at least one LED chip comprises a first LED chip (fig 5d:31; [para 0116]) and a second LED chip (fig 5d:32; [para 0116]),
and a top surface of the first encapsulation layer (fig 5d:50; [para 0111]) between the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) is positioned at a height above the recess floor that is less than a height of the first LED chip (fig 5d:31; [para 0116]) and the second LED chip (fig 5d:32; [para 0116]) above the recess floor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the top surface of the first encapsulant to below the height of the first LED in order to minimize the quantity of encapsulant used.
Response to Arguments
Applicant's arguments filed 2/24/26 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach “a first encapsulation layer arranged on the recess floor and extending on only a portion of the or more recess sidewalls.”
The applicant will note that Ng teaches this limitation
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For, further detail see rejection above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 6, 2026
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