DETAILED ACTION
This office action is in response to amendment filed 7/9/2026.
Claims 1, 4-5, 7-14, 17-18, 25-26, 29, 31-33, and 35 are pending. Claims 2-3, 6, 15-16, 19-24, 27-28, 30, and 34 have been canceled. Claim 35 is new. Claims 1, 13, and 17 have been amended.
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 119(e) as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 62/725,675, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application.
The specification of the provisional application does not describe “forming an additional shielding element over a circuit board” as recited in claim 31. Thus, claim 31 does not benefit from the priority date of the provisional application.
Therefore, claim 31 has the earliest effective filing date of 2/25/2019 for prior art purposes.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-5, 7-14, 17-18, 25-26, 29, 31-33, and 35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “a vertical distance between the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the second conductive bump and the semiconductor die is substantially equal to a vertical distance between a central portion of the bottom surface of the shielding element that is in physical contact with the first protective layer and the semiconductor die” renders the claim indefinite.
Firstly, it is unclear what constitutes “substantially equal”. The term “substantially” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention.
Furthermore, “a vertical distance between the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the second conductive bump and the semiconductor die” is indefinite because it is unclear how is the vertical distance defined relative to both the “first conductive bump” and “second conductive bump”. Is the “vertical distance” between the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the semiconductor die. Or is the “vertical distance” between the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the second conductive bump and the semiconductor die.
Furthermore, it is unclear what constitutes “vertical distance”. The peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the second conductive bump does not overlap the semiconductor die in plan view. The distance between the peripheral portion of the bottom surface of the shielding element and the semiconductor die would be measured at an angle. See annotated drawing below. Thus, it is unclear what constitutes a “vertical” distance.
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Furthermore, the distance between the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the second conductive bump and the semiconductor die (d1 labeled in annotated drawing above) is greater than the distance between a central portion of the bottom surface of the shielding element that is in physical contact with the first protective layer and the semiconductor die (d2 labeled in annotated drawing above) due to the angled direction of the distance between the peripheral portion of the bottom surface of the shielding element and the semiconductor die. Therefore, it is further unclear what constitutes “substantially equal” as claimed.
Claims 13 and 17 reciting similar limitations as claim 1 are indefinite for same reason as detailed for claim 1 above.
Claim 35 reciting “the first protective layer has a contact surface in physical contact with the central portion of the bottom surface of the shielding element, and an entirety of the bottom surface of the shielding element overlies the contact surface of the first protective layer” renders the claim indefinite. The bottom surface of the shielding element as previously recited in claim 1 include “a peripheral portion in physical contact with the first portion of the first conductive bump and the second conductive bump” and “a central portion … that is in physical contact with the first protective layer”. Thus, at least the peripheral portion of the bottom surface of the shielding element that is in physical contact with the first portion of the first conductive bump and the second conductive bump would not overly the contact surface of the first protective layer. It is unclear what constitutes “overlies” and how would the peripheral portion of the bottom surface of the shielding element overly the contact surface of the first protective layer.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-5, 7-11, 17, 31-33 and 35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamano et al. US 2009/0008765 A1 in view of Cheah et al. US 2019/0181126 A1 (Cheah) and Chiang et al. US 2020/0013721 A1 (Chiang).
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In re claim 1, as best understood, Yamano discloses (e.g. FIGs. 11, 32 & 44) a method for forming a chip package, comprising:
forming a plurality of shielding conductive structures PS2 (FIG. 11, e.g. between 100 and 200 of the left side package shown in FIG. 44B) and a plurality of signal conductive structures (PS2 between 100 and 200 of another package, e.g. right side package in FIG. 44B) over a carrier substrate 101 (no specific “shielding conductive structures” and “signal conductive structures” claimed that would distinguish over different ones of PS2 of adjacent package as shown in FIG. 44B, that provide both electrical signal and electromagnetic shielding to the chips 110, ¶ 303-305);
disposing a semiconductor die 110 over the carrier substrate such that the shielding conductive structures (PS2 of left side package show in FIG. 44B) surround the semiconductor die 110, wherein the shielding conductive structures (PS2 of left side package in FIG. 44B) are closer to the semiconductor die 110 (of left side package in FIG. 44B) than the signal conductive structures (PS2 of right side package in FIG. 44B);
forming a shielding element (including 205B,203B,202b,and 200P of left side package, see FIG. 32, ¶ 304, wherein L1 is formed to have the structure of L4 as shown in FIG. 11) over a protective substrate 201;
forming a first protective layer (layer surrounding 203B and 205B) over the shielding element 205B,202b,203B,200P;
forming a first conductive bump AD2 (on the left of FIG. 11) and a second conductive bump AD2 (on the right of FIG. 11) over the first protective layer and the shielding element 205B,202b,203B,200P,
bonding the protective substrate 201 to the shielding conductive structures PS2 and the signal conductive structures PS2 (FIG. 44B) after the first protective layer, the first conductive bump AD2, and the second conductive bump AD2 are formed (that are formed as part of 200), such that the shielding element (including 205B,203B,202b,200P, see FIG. 32) has a bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) including a peripheral portion 205B in physical contact with the first conductive bump (left side AD2 in physical contact with bottom of portion 205B) and the second conductive bump (right side AD2 in physical contact with bottom of portion 205B), wherein the bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) of the shielding element (including 205B,203B,202b,200P of left side package in FIG. 44B) at least partially vertically overlaps the semiconductor die 110 and the shielding conductive structures PS2 (bottom of 205B,200P overlaps 110,PS2 of left side package in FIG. 44B) without vertically overlapping the signal conductive structures (PS2 of right side package in FIG. 44B do not overlap with shielding element 205B+203B+202b+200P of left side package), and “a vertical distance between the peripheral portion of the bottom surface of the shielding element (bottom of 205B) that is in physical contact with the first conductive bump (left AD2) and the second conductive bump (right AD2) and the semiconductor die 110 is substantially equal to a vertical distance between a central portion of the bottom surface of the shielding element (bottom of center of 200P) that is in physical contact with the first protective layer and the semiconductor die 110” (see Examiner’s first annotated drawing of FIG. 32 above, where d1 and d2 are considered “substantially equal” similar to applicant’s disclosure as depicted in annotated FIG. 11 on page 4 above, as best understood); and
forming a second protective layer D1 in physical contact with the first conductive bump AD2, the second conductive bump AD2, the shielding conductive structures PS2 (of left side package in FIG. 44E), the signal conductive structures PS2 (of right side package in FIG. 44E), and the semiconductor die 110 (FIG. 11) after the protective substrate 201 is bonded to the shielding conductive structures PS2 (of left side package in FIG. 44E) and the signal conductive structures PS2 (of right side package in FIG. 44E) (see ¶ 339), and
wherein the first conductive bump AD2 and the second conductive bump AD2 are in physical contact with the shielding conductive structures PS2 on opposite sides of the semiconductor die 110 (FIG. 11).
In an alternative interpretation, the “vertical distances” (as best understood) can correspond to the distances show in Examiner’s second annotated drawing of FIG. 32 below. Distances d1 and d2 are defined at different angles such that the magnitude of the distances are “substantially equal”.
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Furthermore, Cheah discloses (e.g. FIGs. 1-3) a method for forming a chip package comprising forming shielding conductive structures 134,144 and a shielding element 128 around a semiconductor die 114 disposed a shielded region (¶ 47), wherein the shielding element 128 vertically overlaps the shielding conductive structure 134,144 and the semiconductor die 114 in the shielded region without vertically overlapping the signal structure structures 132,142 that are disposed away further from the shield semiconductor die 114 outside the shielded region. Cheah discloses such arrangement shields the semiconductor die 114 and reduce EMI from reaching the processor die 110 disposed outside the shielded region.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yamano’s chip package having a shielded semiconductor die, by arranging another semiconductor die and additional signal conductive structures outside the shielded region to incorporate different dies having different functions in the same package to improve package density and reduce signal delay while reducing EMI effect as taught by Cheah. As such, the shielding element (including 205B,203B,202b,and 200P, see FIG. 32 of Yamano) vertically overlaps the semiconductor die 110 and shielding conductive structures PS2 without vertically overlapping signal conductive structures for additional processor die located outside the shielded region.
Yamano discloses the first conductive bump AD2 and the second conductive bump AD2 formed on the protective substrate 201 (FIG. 11). Yamano does not explicitly disclose the first conductive bump and the second conductive bump each comprises a first portion extending through the first protective layer and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process.
However, Chiang discloses a method of forming a chip package (FIG. 4) comprising conductive bumps 240 formed on the upper wiring substrate 220, wherein the conductive bumps 240 each comprises a first portion extending through the first protective layer (lowermost dielectric layer of 220) and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process. By forming the conductive bumps 240 recessed into the dielectric layer of the wiring substrate 220, the contact surface area between the conductive bumps and the wiring substrate 220 can be increased to improve bonding strength as is known in the art.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yamano’s conductive bumps AD2 (FIG. 11) to have a portion recess into the first protective layer as taught by Chiang to improve bonding strength as is known in the art.
In re claim 4, Yamano discloses the claimed invention including a method for forming a chip package (see FIGs. 11, 32) comprising a semiconductor die surround by conductive structures PS2 and bonding a protective substrate 201 to the conductive structures PS2.
Yamano further disclose forming the chip package includes electronic parts EL2,EL3 over the protective substrate 201, wherein the electronic parts include communications device (¶ 296).
Yamano does not explicitly disclose forming an antenna element over the protective substrate.
However, Cheah discloses (e.g. FIGs. 1-3) a method for forming a chip package comprising forming a plurality of conductive structures 134-144 (FIG. 1H) to surround a semiconductor die 114 and bonding a package substrate 206 (FIG. 3) to the conductive structures, and further forming an antenna element 232 over the protective substrate 206 (¶ 45) to facilitate wireless RF communications (¶ 62). Cheah placing the antenna element close to the active device minimize RF loss through shorter routing (¶ 24).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further form antenna element over Yamano’s protective substrate 201 to facilitate wireless communication and to minimize signal loss as taught by Cheah.
In re claim 5, Cheah discloses (e.g. FIGs. 1-3) wherein the antenna element 232 is formed over the protective substrate 206 (FIG. 2G) before bonding the protective substrate 206 to the shielding conductive structures 134 and the signal conductive structures 132 (FIG. 3).
In re claim 7, Yamano discloses (e.g. FIGs. 11 & 44) further comprising:
introducing a polymer material between the protective substrate 201 and the carrier substrate 101 (FIG. 44E, D1 is a build-up resin which can be a polyimide resin, ¶ 173); and
curing the polymer material to form the second protective layer D1 (¶ 136-137,288-289).
In re claim 8, Yamano discloses (e.g. FIGs. 11 & 32) further comprising forming a redistribution structure 103A,100P over the carrier substrate 101 before the shielding conductive structures PS2 and the signal conductive structures PS2 are formed.
In re claim 9, in an alternative interpretation, Yamano discloses (e.g. FIG. 5L-5P) the carrier substrate 401, and further comprising:
removing the carrier substrate 401 (FIG. 5N); and
forming a plurality of solder bumps 413 over the redistribution structure 405,408 (FIG. 5P), wherein the redistribution structure 405,408 is between the second protective layer D1 and the solder bumps 413.
In re claim 10, Yamano discloses (e.g. FIGs. 44A-44E) further comprising disposing an additional semiconductor die (another one of 110 of right side package, see FIG. 44B) over the carrier substrate 101 before the second protective layer D1 is formed (FIG. 44E), wherein the additional semiconductor die (other 110 of the right side package) is outside of an area (area of left side package) surrounded by the shielding conductive structures PS2 (of left side package).
Furthermore, Cheah teaches (FIGs. 1-3) an additional semiconductor die 110 outside an area surrounded by the shielding conductive structure 134.
In re claim 11, Yamano discloses (FIG. 32) wherein the shielding element 200P comprises a conductive plate, a conductive mesh, or a combination thereof (metal shield layer 200P is considered a “conductive plate”, ¶ 303-304).
In re claim 17, as best understood, Yamano discloses (e.g. FIGs. 11, 32, 44 & 45) a method for forming a chip package, comprising:
forming a plurality of shielding conductive structures PS2 (FIG. 11, e.g. between 100 and 200 of the left side package shown in FIG. 44B) and a plurality of signal conductive structures (PS2 between 100 and 200 of another package, e.g. right side package in FIG. 44B) over a redistribution structure 100A, wherein the shielding conductive structures (PS2 of left side package show in FIG. 44B) surround a region in a top view (region of left side package defined between PS2);
disposing a first semiconductor die 110 (under left 200, see FIG. 44G & 45) and a second semiconductor die 110 (under right 200) over the redistribution structure 100A, wherein the shielding conductive structures (PS2 of left side package in FIG. 44B) are closer to the first semiconductor die 110 (of left side package in FIG. 44B) than the signal conductive structures (PS2 of right side package in FIG. 44B), the first semiconductor die 110 (under left 200) is in the region surrounded by the shielding conductive structures (PS2 of left side package in FIG. 44B), and the second semiconductor die 110 (under right 200 of right side package) is outside the region (of left side package) surrounded by the shielding conductive structures (PS2 of left side package in FIG. 44B);
forming a shielding element (including 205B,203B,202b,and 200P of left side package, see FIG. 32, ¶ 304, wherein L1 is formed to have the structure of L4 as shown in FIG. 11), a first protective layer (layer surrounding 203B and 205B), a first conductive bump AD2, and a second conductive bump AD2 over a protective substrate 201;
bonding the protective substrate 201 to the shielding conductive structures PS2 and the signal conductive structures PS2 (FIG. 44B) after the first protective layer, the first conductive bump AD2, and the second conductive bump AD2 are formed (that are formed as part of 200), such that the shielding element (including 205B,203B,202b,200P, see FIG. 32) has a bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) including a peripheral portion 205B in physical contact with the first conductive bump (left side AD2 in physical contact with bottom of portion 205B) and the second conductive bump (right side AD2 in physical contact with bottom of portion 205B), wherein the bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) of the shielding element (including 205B,203B,202b,200P of left side package in FIG. 44B) at least partially vertically overlaps the first semiconductor die 110 (of left side package) and the shielding conductive structures PS2 (bottom of 205B,200P overlaps 110,PS2 of left side package in FIG. 44B) without vertically overlapping the signal conductive structures (PS2 of right side package in FIG. 44B do not overlap with shielding element 205B+203B+202b+200P of left side package), and “a vertical distance between the peripheral portion of the bottom surface of the shielding element (bottom of 205B) that is in physical contact with the first conductive bump (left AD2) and the second conductive bump (right AD2) and the first semiconductor die 110 is substantially equal to a vertical distance between a central portion of the bottom surface of the shielding element (bottom of center of 200P) that is in physical contact with the first protective layer and the first semiconductor die 110” (see Examiner’s first annotated drawing of FIG. 32 above, where d1 and d2 are considered “substantially equal” similar to applicant’s disclosure as depicted in annotated FIG. 11 on page 4 above, as best understood); and
forming a second protective layer D1 in physical contact with the shielding conductive structures PS2 (of left side package in FIG. 44E), the signal conductive structures PS2 (of right side package in FIG. 44E), the first semiconductor die 110 (of the left side package), the first conductive bump AD2, and the second conductive bump AD2 after the protective substrate 201 is bonded to the shielding conductive structures PS2 (of left side package in FIG. 44E) and the signal conductive structures PS2 (of right side package in FIG. 44E) (see ¶ 339).
In an alternative interpretation, the “vertical distances” (as best understood) can correspond to the distances show in Examiner’s second annotated drawing of FIG. 32 above. Distances d1 and d2 are defined at different angles such that the magnitude of the distances are “substantially equal”.
Furthermore, Cheah discloses (e.g. FIGs. 1-3) a method for forming a chip package comprising a first semiconductor die 114 and a second semiconductor die 110, and forming shielding conductive structures 134,144 and a shielding element 128 around the first semiconductor die 114 disposed a shielded region (¶ 47), wherein the shielding element 128 vertically overlaps the shielding conductive structure 134,144 and the first semiconductor die 114 in the shielded region without vertically overlapping the signal structure structures 132,142 and the second semiconductor die 110 that are disposed away further from the shield first semiconductor die 114 outside the shielded region. Cheah discloses such arrangement shields the first semiconductor die 114 and reduce EMI from reaching the second semiconductor processor die 110 disposed outside the shielded region.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yamano’s chip package having a shielded semiconductor die, by arranging another semiconductor die and additional signal conductive structures outside the shielded region to incorporate different dies having different functions in the same package to improve package density and reduce signal delay while reducing EMI effect as taught by Cheah. As such, the shielding element (including 205B,203B,202b,and 200P, see FIG. 32 of Yamano) vertically overlaps the first semiconductor die 110 and shielding conductive structures PS2 without vertically overlapping signal conductive structures for additional processor die located outside the shielded region.
Yamano discloses the first conductive bump AD2 and the second conductive bump AD2 formed on the protective substrate 201 (FIG. 11). Yamano does not explicitly disclose the first conductive bump and the second conductive bump each comprises a first portion extending through the first protective layer and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process.
However, Chiang discloses a method of forming a chip package (FIG. 4) comprising conductive bumps 240 formed on the upper wiring substrate 220, wherein the conductive bumps 240 each comprises a first portion extending through the first protective layer (lowermost dielectric layer of 220) and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process. By forming the conductive bumps 240 recessed into the dielectric layer of the wiring substrate 220, the contact surface area between the conductive bumps and the wiring substrate 220 can be increased to improve bonding strength as is known in the art.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yamano’s conductive bumps AD2 (FIG. 11) to have a portion recess into the first protective layer as taught by Chiang to improve bonding strength as is known in the art.
In re claim 31, Yamano discloses (see FIG. 32) further comprising forming an additional shielding element 100P over a circuit board (a lower level circuit board below bumps 111, see FIG. 7), wherein the additional shielding element (i.e. the portion below the left 200, see FIG. 44G) vertically overlaps the first semiconductor die 110 (under left 200) without vertically overlapping the second semiconductor die (under right 200). I.e. the select portion of the shielding element 100P that is under one of the semiconductor die 110 is not under an adjacent second semiconductor die.
Furthermore, Cheah teaches (FIGs. 1-3) an additional semiconductor die 110 outside an area surrounded by the shielding conductive structure 134.
In re claim 32, Yamano discloses (e.g. FIG. 11) wherein, in a cross-section view, a maximum width of the second portion (AD2 below 204B) is greater than a maximum width of each of the shielding conductive structures PS2.
In re claim 33, Yamano discloses (e.g. FIG. 11) forming the signal and shielding conductive structures may additional include forming 105A on carrier 101. As such, after the shielding conductive structures 105A+PS2 (of left side package in FIG. 44B) and the signal conductive structures 105A+PS2 (of right side package in FIG. 44B) are formed over the carrier substrate 101 (at least after forming 105A on 101; further, post can be formed on wiring substrate 100A, ¶ 217), the semiconductor die 110 is disposed over the carrier substrate 101 such that the semiconductor die 110 at least partially overlaps the shielding conductive structures 105A+PS2 in a lateral direction.
In re claim 35, as best understood, Yamano (e.g. FIG. 32) wherein the first protective layer (layer surrounding 203B and 205B) has a contact surface in physical contact with the central portion 200P of the bottom surface of the shielding element (including 205B,203B,200P), and an entirety of the bottom surface of the shielding element (including 205B,203B,200P) overlies the contact surface of the first protective layer (layer surrounding 203B and 205B). As best understood, the entire bottom surface of the shielding element including 205B,203B,200P overlies or is located at a height above at least some part of the first protective layer. As best understood, “overlies” does not require complete overlap in plan view.
Claims 12 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Yamano, Cheah, and Chiang as applied to claims 1 and 17 above, and further in view of Lee et al. US 2018/0374798 (Lee).
In re claims 12 and 18, Yamano discloses the shielding conductive structures PS2 surrounding the semiconductor die 110. Yamano does not explicitly disclose two of the shielding conductive structures PS2 are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die.
Lee disclose a method of forming a chip package (FIG. 1) comprising shielding conductive structures 131 surrounding a semiconductor die 120A, wherein two of the shielding conductive structures 131 are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die 120A (¶ 40, wavelength of EMI is about 1 kHz to 100GHz, where 1kHz~3 x 108 mm; and the pitch of the shielding conductive structures is about 10 microns -10 mm which is much less than half of the EMI wavelength). Lee discloses the pitch, and hence the distance between the shielding conductive structures are selected to ensure efficient EMI shielding (¶ 40-41).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yamano’s shielding conductive structures PS2 such that the pitch and therefore the distance between them is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die (e.g. 10 microns -10 mm for EMI 1 kHz to 100GHz) to ensure efficient and optimum EMI shielding as taught by Lee. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Claims 13-14, 25-26, and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamano in view of Cheah, Chiang, and Lee et al. US 2018/0374798 A1 (Lee).
In re claim 13, Yamano discloses (e.g. FIGs. 11, 32 & 44) a method for forming a chip package, comprising:
forming a plurality of shielding conductive structures PS2 (FIG. 11, e.g. between 100 and 200 of the left side package shown in FIG. 44B) and a plurality of signal conductive structures (PS2 between 100 and 200 of another package, e.g. right side package in FIG. 44B) over a redistribution structure 100A;
disposing a semiconductor die 110 over the redistribution structure 100A such that the shielding conductive structures (PS2 of left side package show in FIG. 44B) surround the semiconductor die 110, wherein the shielding conductive structures (PS2 of left side package in FIG. 44B) are closer to the semiconductor die 110 (of left side package in FIG. 44B) than the signal conductive structures (PS2 of right side package in FIG. 44B);
forming a shielding element (including 205B,203B,202b,and 200P of left side package, see FIG. 32, ¶ 304, wherein L1 is formed to have the structure of L4 as shown in FIG. 11) over a protective substrate 201;
forming a first protective layer (layer surrounding 203B and 205B) over the shielding element 205B,202b,203B,200P;
forming a plurality of conductive bump AD2 (FIG. 11) over the first protective layer;
forming an adhesive element 109 (or the underfill around EL4, see FIG. 32) over the semiconductor die 110;
bonding the protective substrate 201 to the shielding conductive structures PS2 and the signal conductive structures PS2 (FIG. 44B) after the first protective layer and the conductive bumps are formed (that are formed as part of 200), such that the shielding element (including 205B,203B,202b,200P, see FIG. 32) has a bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) including a peripheral portion 205B in physical contact with at least two of the conductive bumps (bumps AD2 in physical contact with bottom of portion 205B), wherein the bottom surface (including bottom of 205B and bottom of 200P in FIG. 32) of the shielding element (including 205B,203B,202b,200P of left side package in FIG. 44B) at least partially vertically overlaps with the semiconductor die 110 and the shielding conductive structures PS2 (bottom of 205B,200P overlaps 110,PS2 of left side package in FIG. 44B) without vertically overlapping the signal conductive structures (PS2 of right side package in FIG. 44B do not overlap with shielding element 205B+203B+202b+200P of left side package) , and “a vertical distance between the peripheral portion of the bottom surface of the shielding element (bottom of 205B) that is in physical contact with the first conductive bump (left AD2) and the second conductive bump (right AD2) and the semiconductor die 110 is substantially equal to a vertical distance between a central portion of the bottom surface of the shielding element (bottom of center of 200P) that is in physical contact with the first protective layer and the semiconductor die 110” (see Examiner’s first annotated drawing of FIG. 32 above, where d1 and d2 are considered “substantially equal” similar to applicant’s disclosure as depicted in annotated FIG. 11 on page 4 above, as best understood); and
forming a second protective layer D1 (FIG. 11) in physical contact with the shielding conductive structures PS2 (of left side package in FIG. 44E), the signal conductive structures PS2 (of right side package in FIG. 44E), the semiconductor die 110, and the conductive bumps AD2 after the protective substrate 201 is bonded to the shielding conductive structures PS2 (of left side package in FIG. 44E) and the signal conductive structures PS2 (of right side package in FIG. 44E) (see ¶ 339).
In an alternative interpretation, the “vertical distances” (as best understood) can correspond to the distances show in Examiner’s second annotated drawing of FIG. 32 above. Distances d1 and d2 are defined at different angles such that the magnitude of the distances are “substantially equal”.
Furthermore, Cheah discloses (e.g. FIGs. 1-3) a method for forming a chip package comprising forming shielding conductive structures 134,144 and a shielding element 128 around a semiconductor die 114 disposed a shielded region (¶ 47), wherein the shielding element 128 vertically overlaps the shielding conductive structure 134,144 and the semiconductor die 114 in the shielded region without vertically overlapping the signal structure structures 132,142 that are disposed away further from the shield semiconductor die 114 outside the shielded region. Cheah discloses such arrangement shields the semiconductor die 114 and reduce EMI from reaching the processor die 110 disposed outside the shielded region.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Yamano’s chip package having a shielded semiconductor die, by arranging another semiconductor die and additional signal conductive structures outside the shielded region to incorporate different dies having different functions in the same package to improve package density and reduce signal delay while reducing EMI effect as taught by Cheah. As such, the shielding element (including 205B,203B,202b,and 200P, see FIG. 32 of Yamano) vertically overlaps the semiconductor die 110 and shielding conductive structures PS2 without vertically overlapping signal conductive structures for additional processor die located outside the shielded region.
Yamano discloses the conductive bumps AD2 are formed on the protective substrate 201 (FIG. 11). Yamano does not explicitly disclose the conductive bump each comprises a first portion extending through the first protective layer and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process.
However, Chiang discloses a method of forming a chip package (FIG. 4) comprising conductive bumps 240 formed on the upper wiring substrate 220, wherein the conductive bumps 240 each comprises a first portion extending through the first protective layer (lowermost dielectric layer of 220) and a second portion protruding from the first protective layer, and the first portion and the second portion are formed simultaneously in a same process. By forming the conductive bumps 240 recessed into the dielectric layer of the wiring substrate 220, the contact surface area between the conductive bumps and the wiring substrate 220 can be increased to improve bonding strength as is known in the art.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yamano’s conductive bumps AD2 (FIG. 11) to have a portion recess into the first protective layer as taught by Chiang to improve bonding strength as is known in the art.
Yamano discloses the shielding conductive structures PS2 surrounding the semiconductor die 110. Yamano does not explicitly disclose two of the shielding conductive structures PS2 are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die.
Lee disclose a method of forming a chip package (FIG. 1) comprising shielding conductive structures 131 surrounding a semiconductor die 120A, wherein two of the shielding conductive structures 131 are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die 120A (¶ 40, wavelength of EMI is about 1 kHz to 100GHz, where 1kHz~3 x 108 mm; and the pitch of the conductive structures is about 10 microns -10 mm which is much less than half of the EMI wavelength). Lee discloses the pitch, and hence the distance between the shielding conductive structures are selected to ensure efficient EMI shielding (¶ 40-41).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yamano’s conductive structures PS2 such that the pitch and therefore the distance between them is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die (e.g. 10 microns -10 mm for EMI 1 kHz to 100GHz) to ensure efficient and optimum EMI shielding as taught by Lee. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 14, Lee discloses (e.g. FIG. 1) wherein each of the shielding conductive structures 131 has a width in a range from about 5 μm to about ten times the distance (diameter of 131 is 5-50 microns, ¶ 38). Distance between 131 is pitch less than diameter. Give that pitch is about 100 microns to 10 mm, the distance can be 50 microns to 9995 microns. As such, the width/diameter of 131 being 5-50 microns is in a range from about 5 μm to about ten times the distance.
In re claim 25, Yamano discloses (see FIGs. 11,32) wherein the second protective layer D1 is in physical contact with the adhesive element 109 (or EL4 underfill).
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In re claim 26, Yamano discloses (see FIG. 11) wherein a portion of the second protective layer D1, a portion of the adhesive element 109, and a portion of the conductive bumps AD2 are at a same height level. See FIG. 11 annotated above, showing a height level at which the second protective layer A1, the adhesive element 109, and the conductive bumps AD2 exist in the same vertical plane.
In re claim 29, Yamano discloses (e.g. FIG. 32) wherein in a cross-section view, a length of the semiconductor die 110 is greater than a length of the adhesive element (underfill around EL4).
Response to Arguments
Applicant's arguments filed 7/9/2026 have been fully considered but they are not persuasive.
Regarding Yamano, Applicant argues bottom surfaces of 205B and 200P are not located at the same vertical distance relative to the semiconductor die (Remark, pages 14-15).
This is not persuasive. The claims do not require the bottom surface of the shielding element to be coplanar at the peripheral portion and the central portion. Rather, the claimed “vertical distance”, as best understood, refers to distances between the different portions of the bottom surface of the shielding element and the semiconductor die. The semiconductor die and the peripheral portion of the bottom surface do not overlap in plan view. Therefore, as best understood, the “vertical distance” can be defined at an angle as shown in annotated drawing of Applicant’s FIG. 11 shown below.
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As such, Yamano similarly teaches d1 and d2, see Examiner’s first annotated drawing of FIG. 32 below, that are considered “substantially equal” similar to applicant’s disclosure.
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Alternatively, the “vertical distances” (as best understood) can correspond to the distances show in Examiner’s second annotated drawing of FIG. 32 below. Distances d1 and d2 are defined at different angles such that the magnitude of the distances are “substantially equal”.
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Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights