Prosecution Insights
Last updated: April 19, 2026
Application No. 17/690,685

ANTI-FERROELECTRIC TUNNEL JUNCTION WITH ASYMMETRICAL METAL ELECTRODES

Non-Final OA §103
Filed
Mar 09, 2022
Examiner
MCCOY, THOMAS WILSON
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
3 (Non-Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
10 granted / 10 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
44 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
55.2%
+15.2% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§103
Attorney’s Docket Number: TSMCP1381US Filing Date: 03/09/2022 Claimed Provisional Date: 7/08/2021 Inventors: Chen et al. Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the amendments filed on 12/15/2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Acknowledgement The Amendment filed on 12/15/2025, responding to the Office action mailed 9/11/2025, has been entered. Applicant amended claims 8, 13-15, 21, 31, cancelled claims 26-28, and added claims 36-38. The present Office action is made with all the suggested amendments being fully considered. Response to Amendments Applicant’s amendments to the claims have overcome the respective claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103- as previously formulated in the Non-Final Office action mailed on 9/04/2025. Accordingly, the claim rejections of 35 U.S.C. 102 and 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 8, 13-15, 17, 21-25, and 29-38. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 31-35 are rejected under 35 U.S.C. 103 as being unpatentable over O’Brien (US 20190115353 A1) in view of Schenk (US 20220172791 A1) further in view of Inumiya (US 20140070290 A1). Regarding claim 31, O’Brien (see, e.g., figs. 1 and 2B) shows most aspects of the instant invention, including an integrated chip comprising: A substrate (e.g., metal interconnect 192); A memory structure (e.g., FTJ 110) disposed over the substrate (e.g., metal interconnect 192) and comprising: A bottom electrode (e.g., metal electrode 160) disposed over the substrate (e.g., metal interconnect 192); A non-polar layer (e.g., buffer layer 150) disposed over the bottom electrode (e.g., metal electrode 160) A ferroelectric layer (e.g., ferroelectric tunneling layer 140) arranged over the first non-polar layer (e.g., buffer layer 150); and A top electrode (e.g., metal electrode 130) disposed over the ferroelectric layer (e.g., ferroelectric tunneling layer 140) O’Brien (see, e.g., figs. 1 and 2B), however, fails to teach an intermediate electrode disposed over the non-polar layer, while it also fails to teach the ferroelectric layer disposed over the intermediate electrode, the ferroelectric layer having a first thickness and a second region having a second thickness that is less than the first thickness. Schenk (see, e.g., fig. 5A), in a similar device to O’Brien, teaches an intermediate electrode (e.g., intermediate electrode 510) disposed between a non-polar layer (e.g., dielectric layer 408) and a polarizable layer (e.g., polarizable layer 404). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the intermediate electrode of Schenk over the non-polar layer (and underneath the ferroelectric layer) of O’Brien, in order to allow O’Brien to modify and fine-tune the performance of the memory structure by adjusting its schematic band diagram (see, e.g., paragraph 42 of Schenk). O’Brien in view of Schenk, however, fails to teach the wherein the ferroelectric layer has a first thickness measured along a first outermost sidewall, a second thickness measured along a lateral center of the ferroelectric layer, and a third thickness measured laterally between the first outermost sidewall and the lateral center of the ferroelectric layer, the third thickness being larger than either of the first thickness and the second thickness. Inumiya (see, e.g., fig. 23B), in a similar device to O’Brien in view of Schenk, teaches wherein a ferroelectric layer (e.g., ferroelectric film 18) has a first thickness (see, e.g., annotated fig. 1 below) measured along a first outermost sidewall (see, e.g., annotated fig. 1 below), a second thickness (see, e.g., annotated fig. 1 below) measured along a lateral center of the ferroelectric layer (e.g., ferroelectric film 18), and a third thickness (see, e.g., annotated fig. 1 below) measured laterally between the first outermost sidewall (see, e.g., annotated fig. 1 below) and the lateral center of the ferroelectric layer (e.g., ferroelectric film 18), the third thickness (see, e.g., annotated fig. 1 below) being larger than either of the first thickness (see, e.g., annotated fig. 1 below) and the second thickness (see, e.g., annotated fig. 1 below). PNG media_image1.png 225 297 media_image1.png Greyscale Annotated Fig. 1 Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the varying thickness configuration of Inumiya in the ferroelectric layer of O’Brien in view of Schenk, in order to provide a different inversion threshold voltage profile in different portions of the layer, improving control of the multivalued operation (see paragraphs 259 and 261 of Inumiya). Regarding claim 32, Schenk (see, e.g., fig. 5A), teaches the non-polar layer (e.g., dielectric layer 408) continuously extends between a bottommost surface physically contacting the bottom electrode (e.g., bottom electrode 402) and a topmost surface physically contacting an intermediate electrode (e.g., intermediate electrode 510). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the physical contact configuration of Schenk in the stack setup of O’Brien in view of Schenk further in view of Inumiya, to achieve the expected result of preventing direct flow of electrical current between them, and providing a part of a threshold switch structure (see, e.g., paragraph 45 of Schenk). Regarding claim 33, Schenk (see, e.g., fig. 5A) teaches the intermediate electrode (e.g., intermediate electrode 510) continuously extends between a bottommost surface physically contacting the non-polar layer (e.g., dielectric layer 408) and a topmost surface physically contacting a polarizable layer (e.g., polarizable layer 404). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the physical contact configuration of Schenk in the stack setup of O’Brien in view of Schenk further in view of Inumiya, in order to allow O’Brien to modify and fine-tune the performance of the memory structure by adjusting its schematic band diagram (see, e.g., paragraph 42 of Schenk), and contacting a dielectric layer for the sake of electrical isolation as needed. Regarding claim 34, Inumiya (see, e.g., fig. 2B) teaches the ferroelectric layer (e.g., ferroelectric film 18) comprises a protrusion portion extending outward. Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the protrusion portion of Inumiya in the ferroelectric layer of O’Brien in view of Schenk further in view of Inumiya, in order to provide a larger thickness portion in the central area of the device, providing those aforementioned different inversion threshold characteristics. Note that this modification results in the ferroelectric layer protruding in the direction of the top electrode, and hence facing away from the bottom electrode. Regarding claim 35, Inumiya (see, e.g., fig. 23B) teaches the protrusion portion has a semicircle profile from a cross-sectional view (e.g., note semicircle profile of ferroelectric film 18 in fig. 23B). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the semicircle profile in the protrusion portion of Inumiya in the modified ferroelectric layer of O’Brien in view of Schenk further in view of Inumiya, in order to achieve the expected result of providing a consistent and predictable thickness variance profile throughout the protrusion portion. Allowable Subject Matter Claims 8, 13-15, 17, 21-25, 29-30, and 36-38 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 8, O’Brien (US 20190115353 A1) shows most aspects of the integrated chip. However, O’Brien fails to disclose or suggest wherein the ferroelectric layer has a cross-sectional profile comprising a flat lower surface and a plurality of segments that fluctuate back-and-forth between smaller and larger thicknesses throughout a width of the ferroelectric layer. Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record. Regarding claim 21, O’Brien (US 20190115353 A1) in view of Schenk (US 20220172791 A1) teaches most aspects of the integrated chip. However, O’Brien in view of Schenk fails to disclose or suggest wherein the ferroelectric layer contacts the top electrode along a curved interface and along a flat interface; and wherein the flat interface is entirely below and laterally outside of the curved interface. Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS WILSON MCCOY whose telephone number is (571)272-0282. The examiner can normally be reached 9:30-6:30 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS WILSON MCCOY/Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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Prosecution Timeline

Mar 09, 2022
Application Filed
Mar 18, 2025
Non-Final Rejection — §103
Jun 24, 2025
Response Filed
Sep 09, 2025
Non-Final Rejection — §103
Dec 15, 2025
Response Filed
Mar 06, 2026
Non-Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 5m
Median Time to Grant
High
PTA Risk
Based on 10 resolved cases by this examiner. Grant probability derived from career allow rate.

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