DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant's amendments filed February 2, 2026. Claims 1-2, 4-5, 8, 13, 21, and 24-25 have been amended. No claims have been added. No claims have been canceled. Currently, claims 1-2, 4-14, and 21-27 are pending.
Applicant’s amendments to claims 2, 21, and 24 overcome the objections outlined in the previous Office Action. The claim objections have been withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8, and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-14, and 21-27 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20160073502 A1) herein after “Lee” in view of Yang et al. (US 20100120212 A1) herein after “Yang” and Kim (US 20100200901 A1).
Regarding claim 1, Figs. 18-19 of Lee disclose a high-density capacitor (Figs. 18-19, capacitor structure, ¶ [0093]), comprising:
a bottom electrode (Fig. 18, conductive patterns CP, ¶ [0061]) comprising a first electrically conducting material;
a top electrode (Fig. 18, common electrode 140, ¶ [0058]) comprising a second electrically conducting material and forming a first three-dimensional structure (Fig. 18, “the common electrode 140 may include horizontal portions, which are provided on top and bottom surfaces of the intermediate and upper supporting layers 110 and 120, and vertical connecting portions, which are provided in the openings OP and physically and electrically connect the horizontal portions of the common electrode 140 to each other”, ¶ [0068]), wherein the first three-dimensional structure comprises a first set of vertical portions (see Annotation 1, Figs. 18-19 of Lee, “First Vertical Portions”), a second set of vertical portions (see Annotation 1, Figs. 18-19 of Lee, “Second Vertical Portions”), and a plurality of horizontal portions (see Annotation 1, Figs. 18-19 of Lee, “Horizontal Portions”),
wherein the horizontal portions (HP) are interleaved within the first set of vertical portions (FVP) along a second horizontal direction (shown in Fig. 18), wherein the horizontal portions (HP) are interleaved within the second set of vertical portions (SVP) along the second horizontal direction (shown in Fig. 19),
wherein the second set of vertical portions (SVP) and the plurality of horizontal portions (HP) form a connected volume (Fig. 18, “The common electrode 140 may be provided to enclose the supporting structure and the conductive patterns CP”, ¶ [0068]),
wherein the first electrically conducting material (CP) forms a second three- dimensional structure, and
wherein the second three-dimensional structures comprises four vertical walls (see Annotation 1, Figs. 18-19 of Lee, “Vertical Walls”) and one horizontal bottom wall (see Annotation 1, Figs. 18-19 of Lee, “Horizontal Bottom Wall”);
a dielectric layer (Fig. 18, capacitor dielectric layer 130, ¶ [0071]) disposed between (Fig. 18, “the conductive patterns CP may be electrically isolated from the common electrode 140 by the capacitor dielectric layer 130”, ¶ [0071]) the top electrode (140) and the bottom electrode (CP) and conformally covering surfaces of the first three-dimensional structure (shown in Fig. 18),
wherein the dielectric layer (130) separates the first set of vertical portions (FVP) from the horizontal portions (HP) in the second horizontal direction (shown in Fig. 18) and separates the first set of vertical portions (FVP) from the second set of vertical portions (SVP) in the first horizontal direction (shown in Fig. 19), and
wherein the bottom electrode (CP) envelopes the first set of vertical portions (FVP) of the top electrode (140).
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Annotation 1, Figs. 18-19 of Lee
Lee fails to disclose wherein the first set of vertical portions are also aligned along a first horizontal direction such that the first set of vertical portions are in a grid pattern in plan view;
a plurality of support structures aligned with the first horizontal direction, and separated from one another along the second horizontal direction by a distance corresponding to a size of the second three-dimensional structure, wherein an outer side surface of no more than two of the four vertical walls, in plan view, abut the plurality of support structures.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose the first set of vertical portions (Fig. 12C, portions of upper electrode layer 162 between the storage node electrodes 160) are also aligned along a first horizontal direction (Fig. 12A, y-direction) such that the first set of vertical portions are in a grid pattern in plan view (The upper electrode layer 162 is formed in the spaces between the storage node electrodes 160, as shown in Fig. 12C. The spaces between the storage nodes form a grid pattern in plan view, as shown in Fig. 12A).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to substitute the structure of Lee for the grid pattern as disclosed by Yang. The claimed grid pattern was known in the prior art and one skilled in the art could have combined the structure of Lee with the grid pattern of Yang as claimed with no change in their respective functions, and the combination would have yielded the predictable result of creating a stable memory structure. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Yang fails to disclose a plurality of support structures aligned with the first horizontal direction, and separated from one another along the second horizontal direction by a distance corresponding to a size of the second three-dimensional structure, wherein an outer side surface of no more than two of the four vertical walls, in plan view, abut the plurality of support structures.
In the similar field of endeavor of semiconductor memory devices, Fig. 2 of Kim discloses a plurality of support structures (Fig. 2, plurality of supports 70, ¶ [0035]) aligned with the first horizontal direction (y-direction), and separated from one another along the second horizontal direction (x-direction) by a distance corresponding to a size of the second three-dimensional structure (Fig. 2, capacitor lower electrode 50, ¶ [0034]), wherein an outer side surface of no more than two of the four vertical walls, in plan view, abut the plurality of support structures (Fig. 2, “A pair of support contact surfaces 50S on outside walls of each of the capacitor lower electrodes 50 may respectively contact the pair of adjacent supports 70”, ¶ [0036]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the support structure as disclosed by Kim, to reduce leaning and undesirable bridge effects (see Kim, ¶ [0039]).
Regarding claim 2, Lee, Yang and Kim together disclose the high-density capacitor of claim 1 as applied above, but Lee and Kim fail to disclose wherein the horizontal portions of the top electrode are formed under respective support structures.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose the horizontal portions (Fig. 12C, portions of 162 along the II line) of the top electrode (Figs. 12A-12C, upper electrode layer 162, ¶ [0049]) are formed under respective support structures (Figs. 12A-12C, support patterns 131, ¶ [0030]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Regarding claim 4, Lee, Yang and Kim together disclose the high-density capacitor of claim 1 as applied above, but Lee and Yang fail to disclose each outer side surface is spaced apart by the other vertical walls of the four vertical walls.
In the similar field of endeavor of semiconductor memory devices, Fig. 2 of Kim discloses each outer side surface (Fig. 2, support contact surfaces 50S, ¶ [0036]) is spaced apart by the other vertical walls of the four vertical walls.
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the electrode structure as disclosed by Kim, to reduce leaning and undesirable bridge effects (see Kim, ¶ [0039]).
Regarding claim 5, Lee, Yang and Kim together disclose the high-density capacitor of claim 4 as applied above, and Figs. 18-19 of Lee further disclose wherein the bottom electrode (CP) further comprises an electrically conducting structure (Fig. 18, conductive plates 107, ¶ [0079]) that connects the second three-dimensional structure of the bottom electrode (CP) via one or more conductive structures (“Each of the conductive plates 107 may be electrically connected to the conductive patterns CP”, ¶ [0082]).
Regarding claim 6, Lee, Yang and Kim together disclose the high-density capacitor of claim 1 as applied above, and Figs. 18-19 of Lee further disclose wherein the high-density capacitor comprises a capacitance that is proportional to a volume of the high-density capacitor and proportional to a total area that separates the top electrode (140) from the bottom electrode (CP) (Figs. 18-19 of Lee show that the capacitor structure contains vertical and horizontal walls in the same way as Figs. 12C-12D of the instant application, implying that the total area and capacitance of Lee’s capacitor structure increases in proportion with the overall volume in the same way as the high-density capacitor in the instant application.)
Regarding claim 7, Lee, Yang and Kim together disclose the high-density capacitor of claim 1 as applied above, and Figs. 18-19 of Lee further disclose wherein the dielectric layer (130) further comprises a high-k dielectric material (“The capacitor dielectric layer 130 may be formed of or include at least one of oxides (e.g., a silicon oxide layer), nitrides (e.g., a silicon nitride layer), oxynitrides (e.g., a silicon oxynitride layer), or high-k materials”, ¶ [0072]).
Regarding claim 8, Figs. 18-19 of Lee disclose a high-density capacitor (Figs. 18-19, capacitor structure, ¶ [0093]), comprising:
a bottom electrode (CP) comprising a first electrically conducting material formed as a plurality of three-dimensional structures separated from one another in a horizontal plane, each three-dimensional structure comprising four vertical walls (VW) and one horizontal bottom wall (HBW);
a top electrode (140) comprising a second electrically conducting material surrounding the bottom electrode (CP) in the horizontal plane; and
a dielectric material (130) separating the top electrode (140) from the bottom electrode (CP), the dielectric layer (130) conformally disposed over side surfaces of the top electrode (140) and a bottom surface of the top electrode (140), wherein the dielectric material (130) separates the top electrode (140) from the bottom electrode (CP).
Lee fails to disclose a plurality of electrically insulating support structures, wherein each electrically insulating support structure in the plurality of electrically insulating support structures are aligned with a first horizontal direction and separated from one another along a second horizontal direction by a distance corresponding to a size of each three-dimensional structure; and
wherein an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose a plurality of electrically insulating support structures (131), wherein each electrically insulating support structure in the plurality of electrically insulating supports structures are aligned with a first horizontal direction (y-direction) and separated from one another along a second horizontal direction (Fig. 1, “The support patterns 131 may extend parallel to the Y-axis and may be separated from one another, i.e., spaced apart, in the X-axis direction”, ¶ [0030]) by a distance corresponding to a size of each three-dimensional structure (Fig. 12A, storage node electrodes 160, ¶ [0029]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Yang fails to disclose wherein an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures.
In the similar field of endeavor of semiconductor memory devices, Fig. 2 of Kim discloses an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures (Fig. 2, “A pair of support contact surfaces 50S on outside walls of each of the capacitor lower electrodes 50 may respectively contact the pair of adjacent supports 70”, ¶ [0036]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the support structure as disclosed by Kim, to reduce leaning and undesirable bridge effects (see Kim, ¶ [0039]).
Regarding claim 9, Lee, Yang and Kim together disclose the high-density capacitor of claim 8 as applied above, but Lee fails to disclose wherein the support structures are separated from one another along the second horizontal direction by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose wherein the support structures (131) are separated from one another along the second horizontal direction (Fig. 1, “The support patterns 131 may extend parallel to the Y-axis and may be separated from one another, i.e., spaced apart, in the X-axis direction”, ¶ [0030]) by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode (160) (shown in Fig. 12A).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee for the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Regarding claim 10, Lee, Yang and Kim together disclose the high-density capacitor of claim 8 as applied above, but Lee fails to disclose wherein the plurality of support structures divide the top electrode into a plurality of vertical portions extending in a vertical direction and a plurality of horizontal portions,
wherein the horizontal portions are interleaved within the vertical portions and extend in the first horizontal direction, and
wherein the horizontal portions of the top electrode are formed under respective support structures.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose wherein the plurality of support structures (131) divide the top electrode (162) into a plurality of vertical portions (Fig. 12C, portions of upper electrode layer 162 between the storage node electrodes 160) extending in a vertical direction and a plurality of horizontal portions (Fig. 12C, portions of 162 along the II line),
wherein the horizontal portions (Fig. 12C, portions of 162 along the II line) are interleaved within the vertical portions and extend in the first horizontal direction (y-direction), and
wherein the horizontal portions (Fig. 12C, portions of 162 along the II line) of the top electrode (162) are formed under respective support structures (131).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee for the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Regarding claim 11, Lee, Yang and Kim together disclose the high-density capacitor of claim 10 as applied above, and Figs. 18-19 of Lee further disclose wherein each of the plurality of three-dimensional structures (see Annotation 1, Figs. 18-19 of Lee) of the bottom electrode (CP) envelopes a respective vertical portion of the top electrode (140) (In Figs. 18-19 of Lee, the conductive patterns CP surround the vertical portions of the common electrode 140 in the same way that Figs. 12C-12D of the instant application show the bottom electrode 114 surrounding the vertical portions of the top electrode 120).
Regarding claim 12, Lee, Yang and Kim together disclose the high-density capacitor of claim 10 as applied above, and Figs. 18-19 of Lee further disclose wherein the plurality of vertical portions (FVP, SVP) of the top electrode (140) comprises:
a first plurality of vertical portions (FVP) that are enveloped by respective three-dimensional structures of the bottom electrode (CP) (In Figs. 18-19 of Lee, the conductive patterns CP surround the vertical portions of the common electrode 140 in the same way that Figs. 12C-12D of the instant application show the bottom electrode 114 surrounding the vertical portions of the top electrode 120); and
a second plurality of vertical portions (SVP) that are located between adjacent vertical portions of the first plurality of vertical portions (FVP).
Regarding claim 13, Lee, Yang and Kim together disclose the high-density capacitor of claim 8 as applied above, and Figs. 18-19 of Lee further disclose wherein the bottom electrode (CP) further comprises an electrically conducting structure (107) that connects all of the three-dimensional structures of the bottom electrode (CP) via one or more conductive structures (“Each of the conductive plates 107 may be electrically connected to the conductive patterns CP”, ¶ [0082]).
Regarding claim 14, Lee, Yang and Kim together disclose the high-density capacitor of claim 8 as applied above, and Figs. 18-19 of Lee further disclose wherein the high-density capacitor comprises a capacitance that is proportional to a volume of the high-density capacitor and proportional to a total area that separates the top electrode from the bottom electrode (Figs. 18-19 of Lee show that the capacitor structure contains vertical and horizontal walls in the same way as Figs. 12C-12D of the instant application, implying that the total area and capacitance of Lee’s capacitor structure increases in proportion with the overall volume and total area in the same way as the high-density capacitor in the instant application.)
Regarding claim 21, Figs. 18-19 of Lee disclose a high-density capacitor (Figs. 18-19, capacitor structure, ¶ [0093]), comprising:
a bottom electrode (CP) comprising a first electrically conducting material formed as a plurality of three-dimensional structures separated from one another in a horizontal plane, wherein each three-dimensional structure comprises four vertical walls (VW) and one horizontal bottom wall (HBW);
a top electrode (140) comprising a second electrically conducting material, the top electrode (140) forming a first three-dimensional structure that includes a plurality of vertical portions and a plurality of horizontal portions (HP), wherein each of the plurality of horizontal portions (HP) are interleaved within the vertical portions and extend in a first horizontal direction (shown in Fig. 19); and
a dielectric layer (130) separating the top electrode (140) from the bottom electrode (CP), the dielectric layer (130) conformally disposed over side surfaces of the top electrode (140) and a bottom surface of the top electrode (140), wherein the dielectric layer (130) separates the top electrode (140) from the bottom electrode (CP).
Lee fails to disclose a plurality of electrically insulating support structures, wherein each electrically insulating support structure is aligned with the first horizontal direction,
the plurality of horizontal portions of the top electrode are formed under respective electrically insulating support structures, and the each of electrically insulating support structures are separated from one another along a second horizontal direction by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode,
wherein an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures and the each outer side surface is spaced apart by the other vertical walls of the four vertical walls.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose a plurality of electrically insulating support structures (131), wherein each electrically insulating support structure is aligned with the first horizontal direction (y-direction), the plurality of horizontal portions (Fig. 12C, portions of 162 along the II line) of the top electrode (162) are formed under respective electrically insulating support structures (131), and the each of electrically insulating support structures (131) are separated from one another along a second horizontal direction by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode (160) (Fig. 1, “The support patterns 131 may extend parallel to the Y-axis and may be separated from one another, i.e., spaced apart, in the X-axis direction”, ¶ [0030]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee for the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Yang fails to disclose wherein an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures and the each outer side surface is spaced apart by the other vertical walls of the four vertical walls.
In the similar field of endeavor of semiconductor memory devices, Fig. 2 of Kim discloses an outer side surface of no more than two of the four vertical walls, in plan view, contact the plurality of electrically insulating support structures (70) and the each outer side surface is spaced apart by the other vertical walls of the four vertical walls (Fig. 2, “A pair of support contact surfaces 50S on outside walls of each of the capacitor lower electrodes 50 may respectively contact the pair of adjacent supports 70”, ¶ [0036]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee with the support structure as disclosed by Kim, to reduce leaning and undesirable bridge effects (see Kim, ¶ [0039]).
Regarding claim 22, Lee, Yang and Kim together disclose the high-density capacitor of claim 21 as applied above, and Figs. 18-19 of Lee further disclose wherein the plurality of vertical portions of the top electrode (140) comprises:
a first plurality of vertical portions (FVP) that are enveloped by respective three-dimensional structures of the bottom electrode (CP); and
a second plurality of vertical portions (SVP) that are located between adjacent vertical portions of the first plurality of vertical portions (FVP).
Regarding claim 23, Lee, Yang and Kim together disclose the high-density capacitor of claim 21 as applied above, and Figs. 18-19 of Lee further disclose wherein the dielectric layer (130) further comprises a high-k dielectric material (“The capacitor dielectric layer 130 may be formed of or include at least one of oxides (e.g., a silicon oxide layer), nitrides (e.g., a silicon nitride layer), oxynitrides (e.g., a silicon oxynitride layer), or high-k materials”, ¶ [0072]).
Regarding claim 24, Lee, Yang and Kim together disclose the high-density capacitor of claim 21 as applied above, and Figs. 18-19 of Lee further disclose wherein the bottom electrode (CP) further comprises an electrically conducting structure (Fig. 18, conductive plates 107, ¶ [0079]) that connects the second three-dimensional structures of the bottom electrode (CP) via one or more conductive structures (“Each of the conductive plates 107 may be electrically connected to the conductive patterns CP”, ¶ [0082]).
Regarding claim 25, Lee, Yang and Kim together disclose the high-density capacitor of claim 21 as applied above, and Figs. 18-19 of Lee further disclose wherein the plurality of three-dimensional structures (see Annotation 1, Figs. 18-19 of Lee) of the bottom electrode (CP) envelop a respective vertical portion of the top electrode (140) (In Figs. 18-19 of Lee, the conductive patterns CP surround the vertical portions of the common electrode 140 in the same way that Figs. 12C-12D of the instant application show the bottom electrode 114 surrounding the vertical portions of the top electrode 120).
Regarding claim 26, Lee, Yang and Kim together disclose the high-density capacitor of claim 21 as applied above, and Figs. 18-19 of Lee further disclose wherein the high-density capacitor comprises a capacitance that is proportional to a volume of the high-density capacitor and proportional to a total area that separates the top electrode from the bottom electrode (Figs. 18-19 of Lee show that the capacitor structure contains vertical and horizontal walls in the same way as Figs. 12C-12D of the instant application, implying that the total area and capacitance of Lee’s capacitor structure increases in proportion with the overall volume and total area in the same way as the high-density capacitor in the instant application.)
Regarding claim 27, Lee, Yang and Kim together disclose the high-density capacitor of claim 2 as applied above, but Lee fails to disclose wherein the support structures are separated from one another along the second horizontal direction by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode.
In the similar field of endeavor of semiconductor memory devices, Figs. 12A-12C of Yang disclose wherein the support structures (131) are separated from one another along the second horizontal direction by a distance corresponding to a separation between adjacent three-dimensional structures of the bottom electrode (160) (Fig. 1, “The support patterns 131 may extend parallel to the Y-axis and may be separated from one another, i.e., spaced apart, in the X-axis direction”, ¶ [0030]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the structure of Lee for the support structure as disclosed by Yang, to simplify production (see Yang, ¶ [0007]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.A.N./Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893