DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,7,8 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200273700A1) in view of Ji et al. (US20150380407A1) and in further view of Chang et al. (US20200020544A1).
Regarding claim 1, Figs. 3C-3Q of Cheng teaches a method for forming a semiconductor device structure, comprising:
forming a gate dielectric layer 152 (para.0038) over a substrate 102 (para.0060);
forming a cap layer 153 (para.0042) over the gate dielectric layer 152, wherein the cap layer 153 contains oxygen;
annealing the cap layer 153 and the gate dielectric layer 152;
removing the cap layer 153 (para.0046) after annealing the cap layer 153 and the gate dielectric layer 152;
forming a work function metal layer 155 (para.0049) over the gate dielectric layer 152 after the cap layer 153 is removed;
Cheng does not teach forming a glue layer over the work function metal layer, wherein the glue layer is thinner than the gate dielectric layer;
forming a gate electrode over the glue layer, wherein the gate electrode comprises fluorine and a metal material;
forming an etch stop layer over the gate dielectric layer, the work function metal layer, the glue layer, and the gate electrode, wherein the etch stop layer is connected to a first top surface of the gate dielectric layer, a second top surface of the work function metal layer, a third top surface of the glue layer, and a fourth top surface of the gate electrode; and
after forming the etch stop layer, annealing the gate electrode and the etch stop layer, wherein the fluorine diffuses from the gate electrode into the gate dielectric layer.
Fig.1 of Ji teaches a method for fabricating a semiconductor device includes: forming an etch stop layer 107P (para.0020) over the gate dielectric layer 105P; and forming a first barrier layer 110P (para.0030, wherein the first barrier layer acts as a glue layer) over the work function metal layer 109P (para.0020), wherein the glue layer 110P is thinner than the gate dielectric layer 105P (para.0020).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the first barrier layer 110P of Ji in the teachings of Cheng in order to in order to provide adhesion and improve bond strength.
However, Cheng, as modified by Ji, does not expressly disclose forming a gate electrode 1208 (para.0058) over the glue layer 504, wherein the gate electrode comprises fluorine and a metal material; after forming the etch stop layer, annealing the gate electrode and the etch stop layer, wherein the fluorine diffuses from the gate electrode into the gate dielectric layer.
Fig.1C of Chang teaches a method for forming a semiconductor device structure that includes a gate electrode layer 150 (para.0040) which includes fluorine. The method includes annealing the gate electrode layer 150 and the gate dielectric layer 140 (para.0040) so that fluorine from the gate electrode layer 150 diffuses into the gate dielectric layer 140.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the gate electrode, that includes fluorine, of Chang in the teachings of Cheng, as modified by Ji, because after annealing the gate electrode layer 150 and the gate dielectric layer 140, the fluorine F from the gate electrode layer 150 diffuses into the gate dielectric layer 140 and thus improve the stability, the dielectric property, and the reliability of the gate dielectric layer (Chang, [para.0040-0041]).
Regarding claim 2, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 1, further comprising:
forming a dielectric layer 116 (para.0019) over the substrate 101 (para.0019) before forming the gate dielectric layer 105P (para.0020) over the substrate 101, wherein the dielectric layer 116 has a trench 117P (para.0020), and the gate dielectric layer 105P is formed in the trench 117P.
Regarding claim 7, Ji teaches the method for forming the semiconductor device structure as claimed in claim 1, but does not explicitly teach wherein the fluorine further diffuses from the gate electrode into the work function metal layer after annealing the gate electrode.
However, Chang further teaches, in Fig.2E, wherein work function metal layer is between the gate electrode and the gate dielectric layer.
Therefore, as Chang teaches where fluorine F (Chang, para.0040) further diffuses from the gate electrode 150 (Chang, para.0040) into the gate dielectric layer, when the fluorine diffuses from the gate electrode to the gate dielectric layer, the fluorine will inherently have to diffuse through the work function metal layer to reach the gate dielectric layer from the gate electrode.
Regarding claim 8, the combination of Cheng and Ji does not teach wherein the fluorine further diffuses from the gate electrode into the glue layer after annealing the gate electrode.
However, as Ji teaches the presence of the glue layer between the gate electrode and the gate dielectric layer, when the method of Chang of diffusing fluorine from the gate electrode to the gate dielectric layer is applied in the methods of Cheng and Ji, the fluorine will diffuse from the gate electrode into the glue layer after annealing the gate electrode.
Regarding claim 31, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 2, further comprising:
forming a gate dielectric film 105P (para.0020) over the substrate 101 (para.0019) before the dielectric layer 116 (para.0019) is formed over the substrate 101;
wherein the dielectric layer 116 is formed over the substrate 101 and surrounds the gate dielectric film 105P.
Ji does not teach forming a poly gate electrode over the gate dielectric film and the poly gate electrode, and the poly gate electrode is made of polysilicon; and
removing the gate dielectric film and the poly gate electrode to form the trench in the dielectric layer.
Figs.3D and 3E of Cheng teach dummy gate structures 120 and 130 which include a dummy gate dielectric layer 108 and a dummy gate electrode layer 109 on the dummy gate dielectric layer 108; wherein the dummy gate electrode layer 109 is made of poly-silicon; and wherein the dummy gate electrode layers 109 and the dummy gate dielectric layers 108 are removed to form trench 126.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have Ji’s gate electrode be a poly gate electrode as taught by Cheng because polysilicon can withstand high temperatures as compared to metal.
Claims 3-6 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200273700A1) in view of Ji et al. (US20150380407A1) and Chang et al. (US20200020544A1) and in further view of Wei et al. (US20190096681A1).
Regarding claim 3, the combination of Cheng, Ji and Chang does not teach wherein the etch stop layer is further formed over and connected to a fifth top surface of the dielectric layer, and the method further comprises forming a protective layer over the etch stop layer.
Fig.9 of Wei teaches a formation of gate structure which includes second ILD 110 which may include an etch stop layer (ESL) and a principal dielectric layer; wherein the etch stop layer may be deposited over the first ILD 72 and gate spacers 68, and the principal dielectric layer is deposited over the etch stop layer. (para.0041).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have etch stop layer over deposited over first ILD 72 and gate dielectric layer 82 and to have the principal dielectric layer deposited over the etch stop layer, as taught by Wei, in order to provide more protection.
Regarding claim 4, the combination of Cheng, Ji, Chang and Wei teaches removing portions of the dielectric layer 144 (Cheng, para.0061, wherein contact holes are formed in the ILD layer 144), the etch stop layer 142 (Cheng, para.0061), and the protective layer to form a through hole passing through the dielectric layer 144, the etch stop layer 142, and the protective layer;
depositing a conductive layer over the protective layer and in the through hole (Cheng, para.0062, where the contact holes are filled with a conductive material using a deposition process); and removing the protective layer and the conductive layer outside of the through hole (Cheng, para.0062, where excess portion of the conductive material over the ILD layer 144 is removed in a planarization process, such as a CMP process, to form the via contacts).
Regarding claim 5, Fig.10 of Wei teaches the method for forming the semiconductor device structure as claimed in claim 4, wherein the depositing of the conductive layer 116 (para.0042) over the protective layer 110 (para.0042) and in the through hole (para.0042, openings) comprises the annealing of the gate electrode 106 (para.0046).
Regarding claim 6, Fig.10 of Wei teaches the method for forming the semiconductor device structure as claimed in claim 5, wherein the depositing of the conductive layer 116 (para.0042) over the protective layer 110 (para.0042) and in the through hole (para.0042, openings) and the diffusion of the fluorine from the gate electrode 106 (para.0046) into the gate dielectric layer 82 (para.0043) are performed simultaneously.
Regarding claim 34, Fig.1 of Ji teaches the method for forming the semiconductor device structure as claimed in claim 3, wherein the first top surface of the gate dielectric layer 105P (para.0020), the second top surface of the work function metal layer 108P (para.0020), the third top surface of the glue layer 110P (para.0030), the fourth top surface of the gate electrode 111P (para.0020), and the fifth top surface of the dielectric layer 116 (para.0019) are substantially level with each other.
Claims 21,25,35 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. (US20200273700A1) in view of Chang et al. (US20200020544A1).
Regarding claim 21, Figs.3C-3Q of Cheng teaches a method for forming a semiconductor device structure, comprising:
forming a source/drain structure 124 (para.0060) over a substrate 102 (para.0060);
forming a gate dielectric layer 152 (para.0038) over the substrate 102;
forming a cap layer 153 (para.0041) over the gate dielectric layer 152;
annealing the gate dielectric layer 152 and the cap layer 153;
removing an entirety of the cap layer 153 (para.0046) over the gate dielectric layer 152 after annealing the gate dielectric layer 152 and the cap layer 153;
forming a gate electrode 159 (para.0057) over the gate dielectric layer 152, and
forming a contact plug (para.0061, wherein via contacts to source and drain structures are formed) over and connected to the source/drain structure 124 and spaced apart from the gate electrode 159, wherein the forming of the contact plug comprises annealing the gate electrode 159.
Cheng does not teach wherein the gate electrode comprises fluorine and a metal material; and wherein the fluorine diffuses from the gate electrode into the gate dielectric layer during the forming of the contact plug, and a first fluorine concentration of the gate electrode is greater than a second fluorine concentration of the gate dielectric layer after the contact plug is formed.
Fig.1C of Chang teaches a method for forming a semiconductor device structure that includes a gate electrode layer 150 (para.0040) which includes fluorine. The method includes annealing the gate electrode layer 150 and the gate dielectric layer 140 (para.0040) so that fluorine from the gate electrode layer 150 diffuses into the gate dielectric layer 140 during the forming of the contact plug, and a first fluorine concentration of the gate electrode 150 is greater than a second fluorine concentration of the gate dielectric layer 140 after the contact plug is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode to the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Chang's gate electrode, which includes fluorine, in the teachings of Cheng because the fluorine F from the gate electrode layer 150 diffuses into the isolation layer 120 through the gate dielectric layer 140. It also diffuses into the fin portions 112 and 114. The fluorine F bonds to the dangling bonds of the silicon of the fin portions 112 and 114 and thus, the stability and the reliability of the fin portions 112 and 114 are improved. (CHANG, [para.0083]).
Regarding claim 25, Cheng further teaches the method for forming the semiconductor device structure as claimed in claim 21, wherein the gate dielectric layer 152 (para.0039) becomes dense after the gate dielectric layer 152 and the cap layer 153 (para.0042) are annealed.
Regarding claim 35, Cheng further teaches the method for forming the semiconductor device structure as claimed in claim 21, further comprising:
after forming the gate electrode 159 (para.0057) and before forming the contact plug (para.0061, via contacts), forming a dielectric spacer liner layer 110 (para.0027) over and connected to the source/drain structure 124 (para.0061), wherein the dielectric spacer liner layer 110 has a through hole 122 (para.0028), and the contact plug (para.0061, via contacts) is formed in the through hole 122.
Regarding claim 37, Cheng further teaches the method for forming the semiconductor device structure as claimed in claim 21, wherein the cap layer 153 (para.0042) contains oxygen.
Claims 26-29,36 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US20150380407A1) in view of Cheng et al. (US20200273700A1) and in further view of Chang et al. (US20200020544A1).
Regarding claim 26, Fig.1 of Ji teaches a method for forming a semiconductor device structure, comprising:
forming a gate dielectric layer 105P (para.0020) over a substrate 101 (para.0018);
forming a cap layer 106P (para.0020) over the gate dielectric layer 105P;
annealing the cap layer 106P and the gate dielectric layer 105P;
forming a glue layer 110P (para.0030, wherein the first barrier layer acts as a glue layer) over the gate dielectric layer 105P, wherein the glue layer 110P is thinner than the gate dielectric layer 105P, and the glue layer 110P (para.0030) is made of nitride;
forming a gate electrode 111P (para.0020) over the glue layer 110P.
Ji does not teach completely removing the cap layer after annealing the cap layer and the gate dielectric layer; and
forming a contact plug over the substrate and spaced apart from the gate electrode, wherein the forming of the contact plug comprises annealing the gate electrode.
Fig.3K of Cheng teaches a method that includes depositing a first capping layer on the gate dielectric layer and later removing the first capping layer; wherein first capping layer 153 is removed by a wet etching process to expose the crystalline high-k gate dielectric layer 152′ (para.0046).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the first capping layer, as taught by Cheng, in order to expose the crystalline high-k gate dielectric layer so that a second PDA process 166 is performed on the crystalline high-k gate dielectric layer to enhance crystallization of the crystalline high-k gate dielectric layer (Cheng, [para.0046]).
However, Ji, as modified by Cheng, does not expressly disclose wherein the gate electrode comprises fluorine and a metal material; the fluorine diffuses from the gate electrode through the glue layer into the gate dielectric layer, and a first fluorine concentration of the glue layer before forming the contact plug is less than a second fluorine concentration of the glue layer after forming the contact plug.
Fig.1C of Chang teaches a method for forming a semiconductor device structure that includes a gate electrode layer 150 (para.0040) which includes fluorine. The method includes annealing the gate electrode layer 150 and the gate dielectric layer 140 (para.0040) so that fluorine from the gate electrode layer 150 diffuses into the gate dielectric layer 140 during the forming of the contact plug, and a first fluorine concentration of the gate electrode 150 is greater than a second fluorine concentration of the gate dielectric layer 140 after the contact plug is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode to the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Chang's gate electrode, which includes fluorine, in the teachings of Ji because the fluorine F from the gate electrode layer 150 diffuses into the isolation layer 120 through the gate dielectric layer 140. It also diffuses into the fin portions 112 and 114. The fluorine F bonds to the dangling bonds of the silicon of the fin portions 112 and 114 and thus, the stability and the reliability of the fin portions 112 and 114 are improved. (CHANG, [para.0083]).
Regarding claim 27, the combination of Ji and Cheng teaches the method for forming the semiconductor device structure as claimed in claim 26, further comprising:
forming an interfacial layer 116 (para.0019) over the substrate 101 (para.0018) before the gate dielectric layer 105P (para.0020) is formed, wherein the gate dielectric layer 105P is formed over the interfacial layer 116.
Ji and Cheng do not teach wherein the fluorine further diffuses from the gate electrode through the glue layer and the gate dielectric layer into the interfacial layer after the gate electrode is annealed.
However, as Ji teaches the presence of the glue layer between the gate electrode and the gate dielectric layer, when the method of Chang of diffusing fluorine from the gate electrode to the gate dielectric layer is applied in the methods of Ji and Cheng, the fluorine will diffuse from the gate electrode into the glue layer after annealing the gate electrode.
Regarding claim 28, the combination of Ji, Cheng and Chang further teaches the method for forming the semiconductor device structure as claimed in claim 27, wherein a third fluorine concentration of the gate electrode is greater than the second fluorine concentration of the glue layer after the contact plug is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode into the glue layer.
Regarding claim 29, Chang further teaches the method for forming the semiconductor device structure as claimed in claim 28, wherein the second fluorine concentration of the glue layer is greater than a fourth fluorine concentration of the gate dielectric layer after the contact plug is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing into the gate dielectric layer from the glue layer.
Regarding claim 36, Cheng further teaches the method for forming the semiconductor device structure as claimed in claim 26, further comprising:
after forming the gate electrode 159 (para.0057) and before forming the contact plug (para.0061, via contacts), forming a metal silicide structure (para.0062, where silicide regions are formed at the respective source and drain structures 124 and 134) over the substrate 102 (para.0060), wherein the contact plug (para.0061, via contacts) is over and connected to the metal silicide structure.
Regarding claim 38, Cheng further teaches the method for forming the semiconductor device structure as claimed in claim 26, wherein the cap layer 153 (para.0041) is a nitride material that contains oxygen.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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