DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/05/2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1,2,7,8 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al (US20150380407A1) in view of CHANG et al. (US20200020544A1) and in further view of Ren et al. (US20050285208A1).
Regarding claim 1, Figs.1 and 2L of Ji teaches a method for forming a semiconductor device structure, comprising:
forming a gate dielectric layer 105P (para.0020) over a substrate 101 (para.0018);
forming a work function metal layer 108P (para.0020) over the gate dielectric layer 105P;
forming a glue layer over 110P (para.0030) the work function metal layer 108P, wherein the glue layer 110P is thinner than the gate dielectric layer 105P;
forming a gate electrode 111P (para.0020) over the glue layer 110P,
forming an etch stop layer 31 (para.0065) over the gate dielectric layer 105P, the work function metal layer 108P, the glue layer 110P, and the gate electrode 111P, wherein the etch stop layer 31 is connected to a first top surface of the gate dielectric layer 105P, a second top surface of the work function metal layer 108P, a third top surface of the glue layer 110P, and a fourth top surface of the gate electrode 111P; and
Ji does not teach wherein the gate electrode comprises fluorine and a metal material; after forming the etch stop layer, annealing the gate electrode and the etch stop layer, wherein the fluorine diffuses from the gate electrode into the gate dielectric layer.
CHANG teaches, in Fig.1C, wherein the gate electrode layer 150 includes fluorine F; the gate electrode layer 150 and the gate dielectric layer 140 (para.0040) are annealed so that the fluorine F from the gate electrode layer 150 diffuses into the gate dielectric layer 140 (Paragraph 0040).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include CHANG’s gate electrode, which includes fluorine, in the teachings of Ji because the fluorine bonds to the dangling bonds of the silicon of the gate dielectric layer. Therefore, the stability, the dielectric property, and the reliability of the gate dielectric layer are improved. (CHANG, [para.0093]).
Ren teaches, in Fig.2e, wherein a dielectric capping layer is formed on top of gate electrode and the gate electrode is annealed after forming the dielectric capping layer. (para.0059).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to anneal the gate electrode after forming the etch stop layer of Ji, as taught by Ren, because the dielectric capping layer acts to protect the top surface of metallic layer from being oxidized during subsequent processing. (Ren, [para.0063]).
Regarding claim 2, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 1, further comprising:
forming a dielectric layer 116 (para.0019) over the substrate 101 (para.0019) before forming the gate dielectric layer 105P (para.0020) over the substrate 101, wherein the dielectric layer 116 has a trench 117P (para.0020), and the gate dielectric layer 105P is formed in the trench 117P.
Regarding claim 7, Ji teaches the method for forming the semiconductor device structure as claimed in claim 1, but does not explicitly teach wherein the fluorine F further diffuses from the gate electrode into the work function metal layer after annealing the gate electrode.
However, Chang does further teach in Fig. 2E wherein a work function metal layer is between the gate electrode and the gate dielectric layer.
Therefore, as Chang teaches where the fluorine F (CHANG, para.0040) further diffuses from the gate electrode 150 (CHANG, para.0040) into the gate dielectric layer., when the fluorine diffuses from the gate electrode to the gate dielectric layer, the fluorine will inherently have to diffuse through the work function layer to reach the gate dielectric layer from the gate electrode.
Regarding claim 8, the Combination of Ji and CHANG teaches the method for forming the semiconductor device structure as claimed in claim 1.
Ji does not teach wherein the fluorine F further diffuses from the gate electrode into the glue layer after annealing the gate electrode.
However, as Ji teaches the presence of the glue layer between the gate electrode and the gate dielectric layer, when the method of Chang of diffusing fluorine from the gate electrode to the gate dielectric layer is applied the method of Ji, the fluorine will diffuse from the gate electrode into the glue layer after annealing the gate electrode.
Regarding claim 31, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 2, further comprising:
forming a gate dielectric film 45P (Fig.4C, para.0020) over the substrate 41 (Fig.4C, para.0083) before the dielectric layer 51 (para.0091) is formed over the substrate 41; wherein the dielectric layer 51 is formed over the substrate 41 and surrounds the gate dielectric film 45P and the gate electrode 59P.
Ji does not disclose where the gate electrode is a poly gate electrode.
CHANG teaches, in paragraph 0080, wherein the gate electrode layer 150 is made of polysilicon.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the gate electrode of Ji be a poly gate electrode as taught by Chang because polysilicon can withstand high temperatures as compared to metal (CHANG, [para.0050]).
Ji does not teach forming a poly gate electrode over the gate dielectric film; and
removing the gate dielectric film and the poly gate electrode to form the trench in the dielectric layer.
CHANG teaches, in Figs.1F-2, portions of the gate electrode layer 150, the gate dielectric layers 140, and the semiconductor oxynitride layer 130, which are not under the mask layer M of FIGS. 1E and 1E-1, are removed. After the removal process, a trench is formed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove the gate electrode layer and the gate dielectric layer in order to form trenches because the trenches are used as a location where isolation structures are formed (CHANG, [para.0050]).
Claims 3-6 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al (US20150380407A1) in view of CHANG et al. (US20200020544A1) and Ren et al. (US20050285208A1) and in further view of Wei et al. (US20190096681A1).
Regarding claim 3, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 2, wherein the etch stop layer 31 (para.0065) is further formed over and connected to a fifth top surface of the dielectric layer 116 (para.0019), and the method further comprises comprising:
forming an etch stop layer 31 over the dielectric layer 116, the gate dielectric layer 105P (para.0020), the work function metal layer 108P (para.0020), the glue layer 110P (para.0030), and the gate electrode 111P (para.0020) before annealing the gate electrode 111P;
Ji does not teach forming a protective layer over the etch stop layer.
Wei teaches in Fig.9, para.0041, wherein the principal dielectric layer is deposited over the etch stop layer. The etch stop layer and principal dielectric layer of the second ILD 110 can be or include the same or similar materials.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to deposit the principal dielectric layer over the etch stop layer as taught by Wei in order to provide more protection.
Regarding claim 4, Ji further teaches the method for forming the semiconductor device structure as claimed in claim 3, further comprising:
Ji does not teach removing portions of the dielectric layer, the etch stop layer, and the protective layer to form a through hole passing through the dielectric layer, the etch stop layer, and the protective layer;
depositing a conductive layer over the protective layer and in the through hole; and removing the protective layer and the conductive layer outside of the through hole.
Wei teaches, in Fig.10, para.0042, wherein openings are formed through the second ILD 110 and the first ILD 72 and a conductive material 116 is formed on the liner 112 in the openings.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Wei’s conductive material in the teachings of Ji in order to form source/drain contacts.
Regarding claim 5, Fig.10 of Wei teaches the method for forming the semiconductor device structure as claimed in claim 4, wherein the depositing of the conductive layer 116 (para.0042) over the protective layer 110 (para.0042) and in the through hole (para.0042, openings) comprises the annealing of the gate electrode 106 (para.0046).
Regarding claim 6, Fig.10 of Wei teaches the further teaches the method for forming the semiconductor device structure as claimed in claim 5, wherein the depositing of the conductive layer 116 (para.0042) over the protective layer 110 (para.0042) and in the through hole (para.0042, openings) and the diffusion of the fluorine from the gate electrode 106 (para.0046) into the gate dielectric layer 82 (para.0043) are performed simultaneously.
Regarding claim 34, Fig.1 of Ji teaches the method for forming the semiconductor device structure as claimed in claim 3, wherein the first top surface of the gate dielectric layer 105P (para.0020), the second top surface of the work function metal layer 108P (para.0020), the third top surface of the glue layer 110P (para.0030), the fourth top surface of the gate electrode 111P (para.0020), and the fifth top surface of the dielectric layer 116 (para.0019) are substantially level with each other.
Claims 21,25,32 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US20190096681A1) in view of HUANG et al. (US20190273149A1) and in further view of CHANG et al. (US20200020544A1).
Regarding claim 21, Figs.2-10 of Wei teaches a method for forming a semiconductor device structure, comprising: forming a source/drain structure 70 (para.0020) over a substrate 60 (para.0019);
forming a gate dielectric layer 82 (para.0027) over the substrate 60;
forming a cap layer 84 (para.0030) over the gate dielectric layer 82;
removing the cap layer 84;
forming a gate electrode 106 (para.0036) over the gate dielectric layer 82,
forming a contact plug 116 (para.0042) over and connected to the source/drain structure 70 and spaced apart from the gate electrode 106,
Wei does not teach annealing the gate dielectric layer and the cap layer; and wherein the gate electrode comprises fluorine and a metal material; wherein the forming of the contact plug comprises annealing the gate electrode; wherein the fluorine diffuses from the gate electrode into the gate dielectric layer during the forming of the contact plug, and a first fluorine concentration of the gate electrode is greater than a second fluorine concentration of the gate dielectric layer after the contact plug is formed.
HUANG teaches, in Fig. 4B, para.0032, wherein a first thermal process may be performed to anneal the first capping layer 404 and gate dielectric layer 302. The first thermal process can improve the quality of the gate dielectric layer 302.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to anneal both the capping layer 404 and gate dielectric layer 302, as taught by HUANG, in order to improve the quality of the gate dielectric layer.
However, Wei, as modified by HUANG, does not expressly disclose wherein the fluorine diffuses from the gate electrode into the gate dielectric layer during the forming of the contact plug, and a first fluorine concentration of the gate electrode is greater than a second fluorine concentration of the gate dielectric layer after the contact plug is formed.
CHANG teaches, in Fig.1C, (para.0040), wherein the gate electrode layer 150 includes fluorine F; the gate electrode layer 150 and the gate dielectric layer 140 are annealed so that the fluorine F from the gate electrode layer 150 diffuses into the gate dielectric layer 140, wherein the fluorine diffuses from the gate electrode 150 (para.0040) into the gate dielectric layer 140 (para.0040) during the forming of the contact plug, and a first fluorine concentration of the gate electrode 150 is greater than a second fluorine concentration of the gate dielectric layer 140 after the contact plug is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode to the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include CHANG’s gate electrode, which includes fluorine, in the teachings of Wei because the fluorine F from the gate electrode layer 150 diffuses into the isolation layer 120 through the gate dielectric layer 140. It also diffuses into the fin portions 112 and 114. The fluorine F bonds to the dangling bonds of the silicon of the fin portions 112 and 114 and thus, the stability and the reliability of the fin portions 112 and 114 are improved. (CHANG, [para.0083]).
Regarding claim 25, Wei further teaches the method for forming the semiconductor device structure as claimed in claim 21, wherein the gate dielectric layer 82 (para.0034) becomes dense after the gate dielectric layer 82 and the cap layer 84 (para.0030) are annealed.
Regarding claim 32, Fig.1F of CHANG teaches the method for forming the semiconductor device structure as claimed in claim 21, further comprising:
forming a gate dielectric film 140 (para.0040) over the substrate 110 (para.0028) before the gate dielectric layer 140 is formed over the substrate 110;
forming a poly gate electrode 150 (para.0049) over the gate dielectric film 140, wherein the poly gate electrode 150 is made of polysilicon;
forming a dielectric layer 130 (para.0032) over the substrate 110 and surrounding the gate dielectric film 140 and the poly gate electrode 150; and
removing the gate dielectric film 140 (para.0075) and the poly gate electrode 150 (para.0058) to form a trench 122 (para.0050) in the dielectric layer 130, wherein the gate dielectric layer 140 is formed in the trench 122.
Regarding claim 35, Fig.10 of Wei further teaches the method for forming the semiconductor device structure as claimed in claim 21, further comprising:
after forming the gate electrode 106 (para.0037) and before forming the contact plug 116 (para.0042), forming a dielectric spacer liner layer 72 (para.0042) over and connected to the source/drain structure 70 (para.0042), wherein the dielectric spacer liner layer 72 has a through hole (para.0042, openings), and the contact plug 116 is formed in the through hole (para.0042, openings).
Claims 26,27,28,29,33 and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US20150380407A1) in view of CHANG et al. (US20200020544A1) and in further view of Wei et al. (US20190096681A1).
Regarding claim 26, Figs.1 and 2L of Ji teaches a method for forming a semiconductor device structure, comprising: forming a gate dielectric layer 105P (para.0020) over a substrate 101 (para.0018);
forming a glue layer 110P (para.0030) over the gate dielectric layer 105P, wherein the glue layer 110P is thinner than the gate dielectric layer 105P, and the glue layer 110P (barrier layer is made of titanium nitride (TiN)) is made of nitride;
forming a gate electrode 111P (para.0020) over the glue layer 110P,
Ji does not teach wherein the gate electrode comprises fluorine and a metal material.
CHANG teaches, in Fig.1C, (para.0038), wherein the gate electrode layer 150 includes fluorine F; the gate electrode layer 150 and the gate dielectric layer 140 are annealed so that the fluorine F from the gate electrode layer 150 diffuses into the gate dielectric layer 140, the fluorine diffuses from the gate electrode 150 through the glue layer into the gate dielectric layer 140, and a first fluorine concentration of the glue layer before forming the contact plug is less than a second fluorine concentration of the glue layer after forming the contact plug. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode to the gate dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include CHANG’s gate electrode, which includes fluorine, in the teachings of Ji because the fluorine bonds to the dangling bonds of the silicon of the gate dielectric layer. Therefore, the stability, the dielectric property, and the reliability of the gate dielectric layer are improved. (CHANG, [para.0093]).
However, Ji, as modified by CHANG, does not expressly disclose forming a contact plug over the substrate and spaced apart from the gate electrode, wherein the forming of the contact plug comprises annealing the gate electrode.
Wei teaches, in Fig.10, para.0042, wherein openings are formed through the second ILD 110 and the first ILD 72 and a conductive material 116 is formed on the liner 112 in the openings.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include Wei’s conductive material in the teachings of Ji in order to form source/drain contacts.
Regarding claim 27, combination of Ji and CHANG further teaches the method for forming the semiconductor device structure as claimed in claim 26, further comprising:
forming an interfacial layer 116 (para.0019) over the substrate 101 (para.0019) before the gate dielectric layer 105P (para.0020) is formed, wherein the gate dielectric layer 105P is formed over the interfacial layer 116, and the fluorine further diffuses from the gate electrode 150 (CHANG, para.0040) through the glue layer and the gate dielectric layer 140 (CHANG, para.0040) into the interfacial layer after the gate electrode 150 is annealed.
Regarding claim 28, Combination of CHANG and Wei further teaches the method for forming the semiconductor device structure as claimed in claim 27, wherein a first third fluorine concentration of the gate electrode 150 (CHANG, para.0040) is greater than the second fluorine concentration of the glue layer 104 (Wei, para.0036) after the contact plug 116 (para.0042) is formed. It is well known that fluorine diffuses from a region of higher concentration to a region of lower concentration. In this case, fluorine is diffusing from the gate electrode to the gate dielectric layer 116 (para.0042).
Regarding claim 29, Wei further teaches the method for forming the semiconductor device structure as claimed in claim 28, wherein the second fluorine concentration of the glue layer 104 (Wei, para.0036) is greater than a fourth third fluorine concentration of the gate dielectric layer 82 (Wei, para.0044) after the contact plug 116 (para.0042) is formed.
Regarding claim 33, Fig.1F of CHANG teaches the method for forming the semiconductor device structure as claimed in claim 26, further comprising:
forming a gate dielectric film 140 (para.0040) over the substrate 110 (para.0028) before the gate dielectric layer 110 (para.0028) is formed over the substrate 110;
forming a poly gate electrode 150 (para.0049) over the gate dielectric film 140, wherein the poly gate electrode 150 (para.0058) is made of polysilicon;
forming a dielectric layer 130 (para.0032) over the substrate 110 and surrounding the gate dielectric film 140 and the poly gate electrode 150; and
removing the gate dielectric film 140 (para.0075) and the poly gate electrode 150 to form a trench 122 (para.0050) in the dielectric layer 130, wherein the gate dielectric layer 140 is formed in the trench 122.
Regarding claim 36, Wei teaches the method for forming the semiconductor device structure as claimed in claim 26, further comprising:
after forming the gate electrode 106 (para.0036) and before forming the contact plug 116 (para.0042), forming a metal silicide structure 114 (para.0042) over the substrate 60 (para.0014), wherein the contact plug 116 is over and connected to the metal silicide structure 114.
Conclusion
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/ERIC K ASHBAHIAN/Primary Examiner, Art Unit 2891