DETAILED ACTION
This Office action is in response to the Request for Continued Examination (RCE) and Amendment filed on 29 December 2025. Claims 1-20 are pending in the application
Related U.S. Application Data
This application is a continuation-in-part of U.S. patent application Ser. No. 16/537,564, filed on Aug. 10, 2019, now abandoned; which is a continuation-in-part of U.S. patent application Ser. No. 15/460,230, filed on Mar. 16, 2017, now U.S. Pat. No. 10,497,713; which is a continuation-in-part of U.S. patent application Ser. No. 14/821,683, filed on Aug. 7, 2015, now U.S. Pat. No. 9,613,844; which is a continuation-in-part of U.S. patent application Ser. No. 13/492,395, filed on Jun. 8, 2012, now U.S. Pat. No. 9,136,153; which is a continuation of U.S. patent application Ser. No. 13/273,712, filed Oct. 14, 2011, now U.S. Pat. No. 8,273,610; which is a continuation-in-part of U.S. patent application Ser. No. 13/016,313, filed on Jan. 28, 2011, now U.S. Pat. No. 8,362,482; which is a continuation-in-part of U.S. patent application Ser. No. 12/970,602, filed on Dec. 16, 2010, now U.S. Pat. No. 9,711,407; which is a continuation-in-part of U.S. patent application Ser. No. 12/949,617, filed on Nov. 18, 2010, now U.S. Pat. No. 8,754,533, which is a continuation-in-part of U.S. patent application 12/900,379, filed on October 07, 2010, now U.S. Patent 8,395,191.
This application is also a continuation-in-part of U.S. patent application Ser. No. 17/542,492, filed on Dec. 5, 2021, now U.S. Patent 11,482,440; which is a continuation-in-part of U.S. patent application Ser. No. 17/233,503, filed on Apr. 18, 2021, now U.S. Pat. No. 11,217,472; which is a continuation-in-part of U.S. patent application Ser. No.16/537,564, filed on Aug. 10, 2019, now abandoned.
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 29 December 2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained through the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Or-Bach et al., US 2011/0108888, of record, either taken alone, or in combination with Huang et al., US 6,033,963, newly cited.
With respect to claim 1, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0759];
third transistors M8-M10 disposed atop of said second transistors M1 and M2, wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material. Or-Bach et al. disclose that tungsten can be used as a metal for a gate electrode, see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082], which exhibits high temperature resistance and can withstand high temperatures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that tungsten could be used as the gate material for the third transistors.
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a tungsten based metal gate. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 2, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 3, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0329]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors each comprise a polysilicon channel.
With respect to claim 4, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 5, Or-Bach et al. disclose that the transistors in the disclosed memory devices can be processed using a same lithography step, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 6, Or-Bach et al. disclose that the memory control (peripheral) circuits, can be formed in a monocrystalline substrate, see, for example, paragraphs [0539]-[0540]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the memory control circuits comprise a plurality of said first single crystal transistors.
With respect to claim 7, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 8, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0759];
third transistors M8-M10 disposed atop of said second transistors M1 and M2, wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material. wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material (Or-Bach et al. disclose that aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082], therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the transistors in the memory device shown in Fig. 53E could have metal gate electrodes.); and
at least one eight bit NAND gate, wherein said at least one eight bit NAND gate comprises a plurality of said first single crystal transistors. Or-Bach et al. disclose a 3D compact 3D CMOS 8 Input NAND cell can be constructed, as illustrated in Figs. 63A-63G, see paragraphs [0762]-[0763]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the memory device of Fig. 53 could be constructed to include at least one eight bit NAND gate, wherein said at least one eight bit NAND gate comprises a plurality of said first single crystal transistors.
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement
gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a metal based metal gate. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 9, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 10, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0329]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors each comprise a polysilicon channel.
With respect to claim 11, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 12, Or-Bach et al. shows in Fig. 53E that at least one of the second transistors is self-aligned to at least one of the third transistors and disclose that the transistors in the disclosed memory devices can be processed using a same lithography step, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 13, Or-Bach et al. disclose that tungsten has a high temperature resistance, can be used as a high resistance multiple-level interconnect to connect together transistors, and can withstand high temperature processing, see paragraphs [0607], [0726], and [0730]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first metal layer and the second metal layer can comprise tungsten.
With respect to claim 14, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 15, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0759];
a first metal layer 5320, see paragraph [0760];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0759];
a second level comprising second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0759];
a third level comprising third transistors M8-M10 disposed atop of said second level;
a via 6308 disposed at least through sard third level
wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material (Or-Bach et al. disclose that aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0314], [0413], [0428], [0442], [0458], [0472], [0489], [0501], [0557], [0571], [0631], [0644], and [1082], therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the transistors in the memory device shown in Fig. 53E could have metal gate electrodes.);
wherein said second transistors are aligned to said first single crystal transistors, as shown in Fig. 53E, with less than a 40 nm error, see paragraph [0306] (Or-Bach et al. disclose that transistors have less than a 40 nm alignment error.)
wherein said via comprises tungsten (Or-Bach et al. disclose that tungsten has a high temperature resistance, can be used as a high resistance multiple-level interconnect to connect together transistors, and can withstand high temperature processing, see paragraphs [0607], [0726], and [0730]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the via could comprise tungsten.)
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement
gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). The semiconductor device of Or-Bach clearly has a tungsten based metal gate. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 16, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 17, Or-Bach et al. shows in Fig. 53E that at least one of the second transistors is self-aligned to at least one of the third transistors and disclose that the transistors in the disclosed memory devices can be processed using a same lithography step, see paragraphs [0427], [0441], [0457], [0471], [0488], [0523], [0556], and [0570].
With respect to claim 18, in paragraph [0759], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 19, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 20, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0329]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors could be junction-less transistors and each junction-less transistor can comprise a polysilicon channel.
Claims 1-4, 6-11, 13-16, and 17-20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Or-Bach et al., US 2010/0289064, newly cited, either taken alone, or in combination with Huang et al., US 6,033,963, also newly cited.
With respect to claim 1, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0489];
a first metal layer 5320, see paragraph [0490];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0489];
second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0489];
third transistors M8-M10 disposed atop of said second transistors M1 and M2, wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material. Or-Bach et al. disclose that tungsten can be used as a metal for a gate electrode, see paragraphs [0245], [0376], and [0481], which exhibits high temperature resistance and can withstand high temperatures. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that tungsten could be used as the gate material for the third transistors.
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement
gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In light of the teachings of Or-Bach et al. in paragraphs [0245], [0376], and [0481], it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the third transistors in the known of Or-Bach could have a tungsten based metal gate, since tungsten exhibits high temperature resistance and can withstand high temperatures. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 2, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type, see paragraph [0124]. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 3, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0260]. Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors each comprise a polysilicon channel.
With respect to claim 4, in paragraph [0489], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 6, Or-Bach et al. disclose that the memory control (peripheral) circuits can be formed in a monocrystalline substrate, see, for example, paragraphs [0327] and [0335]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the memory control circuits comprise a plurality of said first single crystal transistors.
With respect to claim 7, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 8, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0489];
a first metal layer 5320, see paragraph [0490];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0489];
second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0489];
third transistors M8-M10 disposed atop of said second transistors M1 and M2, wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material. wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material (Or-Bach et al. disclose that aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0245], [0376], and [0481], therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the transistors in the memory device shown in Fig. 53E could have metal gate electrodes.); and
at least one eight bit NAND gate, wherein said at least one eight bit NAND gate comprises a plurality of said first single crystal transistors. Or-Bach et al. disclose a 3D compact 3D CMOS 8 Input NAND cell can be constructed, as illustrated in Figs. 63A-63G, see paragraphs [0492]-[0493]. Therefore, It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the memory device of Fig. 53 could be constructed to include at least one eight bit NAND gate, wherein said at least one eight bit NAND gate comprises a plurality of said first single crystal transistors.
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement
gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In light of the teachings of Or-Bach et al. in paragraphs [0245], [0376], and [0481], it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the third transistors in the known of Or-Bach could have a tungsten based metal gate, since tungsten exhibits high temperature resistance and can withstand high temperatures. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 9, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type, see paragraph [0124]. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 10, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0260]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors each comprise a polysilicon channel.
With respect to claim 11, in paragraph [0489], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 13, Or-Bach et al. disclose that tungsten has a high temperature resistance, can be used as a high resistance multiple-level interconnect to connect together transistors, and can withstand high temperature processing, see paragraphs [0214], [0351], and [0352], [0456], and [0460]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the first metal layer and the second metal layer can comprise tungsten.
With respect to claim 14, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 15, Or-Bach et al. disclose a 3D semiconductor device, shown in Fig. 53E, the device comprising:
a first level comprising a first single crystal layer and first single crystal transistors M5 and M6, see paragraph [0489];
a first metal layer 5320, see paragraph [0490];
a second metal layer 5342 disposed atop said first metal layer 5320, see paragraph [0489];
a second level comprising second transistors M1 and M2 disposed atop of said second metal layer 5342, see paragraph [0489];
a third level comprising third transistors M8-M10 disposed atop of said second level;
a via 6308 disposed at least through sard third level
wherein at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a metal based gate material (Or-Bach et al. disclose that aluminum or tungsten can be used as a metal for a gate electrode, see paragraphs [0245], [0376], and [0481], therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the transistors in the memory device shown in Fig. 53E could have metal gate electrodes.);
wherein said second transistors are aligned to said first single crystal transistors, as shown in Fig. 53E, with less than a 40 nm error, see paragraph [0237] (Or-Bach et al. disclose that transistors have less than a 40 nm alignment error.)
wherein said via comprises tungsten (Or-Bach et al. disclose that tungsten has a high temperature resistance, can be used as a high resistance multiple-level interconnect to connect together transistors, and can withstand high temperature processing, see paragraphs [00214], [0227], [0231], [0351], [0352], and [0456]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the via could comprise tungsten.)
Admittedly, Or-Bach et al. do not expressly disclose that the one replacement
gate is processed to replace a non-metal gate material with a tungsten-based gate material. Firstly, the present claim is a product-by-process claim, since it recites the process limitation “at least one of said third transistors comprises at least one replacement gate, being processed to replace a non-metal gate material with a tungsten based gate material”. Product-by-process claims are not limited to the manipulations of the recited processing steps, only the structure implied by the steps. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production, if the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 111 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). In light of the teachings of Or-Bach et al. in paragraphs [0245], [0376], and [0481], it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the third transistors in the known of Or-Bach could have a tungsten based metal gate, since tungsten exhibits high temperature resistance and can withstand high temperatures. Once the examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir. 1983)
Secondly, in the same field of endeavor, Huang et al. disclose a process for replacing a non-metal gate material (22, polysilicon) with a tungsten-based gate material, see Figs. 1-12. The replacement gate process of Huang et al. provides considerable improvement over the prior art, since source and drain regions are formed prior to forming the metal gate, eliminating the need for high temperature processing after metal gate formation which could cause metal migration. In light of the teaching of Huang et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to replace a non-metal gate material with a tungsten-based gate material in the third transistors in the known 3D semiconductor device of Or-Bach et al.
With respect to claim 9, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type. In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 16, Or-Bach et al. disclose in the memory of Fig. 53E that the second transistors comprise a source, a channel, and a drain, Or-Bach et al. further disclose that the transistors used in the disclosed 3D memory devices can be junction-less transistors, see, for example, Figs. 54A-54C, with source, channel, and drain having a similar doping type, see paragraph [0124]. . In light of the disclosure of Or-Bach et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a junction-less transistor could have been used in the memory of Fig. 53E for the second transistor, thereby the source, channel, and drain of the second transistors would have a similar doping type.
With respect to claim 18, in paragraph [0489], Or-Bach et al. disclose that Figs. 53A-53E disclose a process flow for constructing a compact 3D CMOS Content Addressable Memory, which would comprise an array of memory cells, wherein at least one of said memory cells comprise at least one of said second transistors, and wherein at least one of another of said memory cells comprise at least one of said third transistors.
With respect to claim 19, Or-Bach et al. disclose a third metal layer 5324 disposed above said second metal layer 5342, wherein said second metal layer 5342 is thicker by at least 50 % than said third metal layer 5324, as shown in Fig. 53E.
With respect to claim 20, Or-Bach et al. disclose that the channel of a junction-less transistor can be constructed of polysilicon, see paragraph [0260]. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the second transistors could be junction-less transistors and each junction-less transistor can comprise a polysilicon channel.
Response to Arguments
Applicant's arguments filed 29 December 2025 have been fully considered but they are not persuasive. Independent claims 1, 8, and 15 have been amended to delete “wherein a distance from at least one of said third transistors to at least one of said first transistors is less than 2 microns”. Applicant has argued that the deletion of this claim limitation from independent claims 1, 8, and 15 makes the effective filing date of the instant application 07 October 2010. However, the references applied above, Or-Bach et al., US 2011/0108888, and Or-Bach et al., US 2010/0289064, are effective as references against the instant application under 35 USC 102(e), since both references are ”by another”, since the inventive entity of each reference is different from the inventive entity of the instant application. The instant application names Zvi Or-Bach, Brian Cronquist, and Deepak C. Sekar as inventors, whereas the above-identified references name J. L. de Jong and Israel Beinglass as well as Zvi Or-Bach, Brian Cronquist, and Deepak C. Sekar as inventors. For these reasons, Applicant’s pending claims are not deemed patentable over Or-Bach et al., US 2011/0108888, and Or-Bach et al., US 2010/0289064.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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MARY A. WILCZEWSKI
Primary Examiner
Art Unit 2898
/MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898