DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on September 17, 2025 has been entered.
Status of claims
Claims 1, 11, 16 are amended.
Claims 2-8, 12-15, 17, 20 previously presented.
Claims 21-22 are new.
Claims 9 and 10 are cancelled.
Claims 18 and 19 are withdrawn
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 21 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 21. Claim 21 recites the limitation "the first source electrode", “the second source electrode” and “the third drain electrode” in the claim language. There is insufficient antecedent basis for this limitation in the claim.
For the purpose of examination and compact prosecution, examiner shall interpret "the first source electrode", “the second source electrode” and “the third drain electrode” to be the first source, the second source, and the third drain respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 8, 11-13, 16, 17, 20-22 are rejected under 35 U.S.C. 103 as being unpatentable over Worley (U.S. Patent 6,016,268), Matsuzawa (U.S. 2007/0133337), and Chen et al (U.S. 2017/0125425).
Regarding claim 1. Worley discloses a memory cell (FIG. 2a), comprising:
a read bit line (FIG. 2a, item 8, item Br) and a read word line (FIG. 2a, item 7, item Wr);
a write bit line (FIG. 2a, item 9, item Bw) and a write word line (FIG. 2a, item 4, item Ww);
a source line (FIG. 2a, item 5, item 5);
a write access transistor (FIG. 2a, item Q1) comprising first source (FIG. 2a, item Q1 source attached to item 9), a first drain (FIG. 2a, item Q1 drain attached to item 10), and a first gate (FIG. 2a, item Q1 Gate), wherein the first gate (FIG. 2a, item Q1 Gate connected to item 4) is electrically connected to the write word line (FIG. 2a, item 4, item Ww) and the first source (FIG. 2a, item Q1 source attached to item 9) is electrically connected to the write bit line (FIG. 2a, item 9, item Bw);
a first oxide definition region (FIG. 5, item First Oxide Definition Region) associated with the write access transistor (FIG. 5, item Q1, write access transistor Q1);
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a storage transistor (FIG. 2a, item Q2) comprising a second source (FIG. 2a, item Q2 source), a second drain (FIG. 2a, item Q2 drain), and a second gate (FIG. 2a, item Q2 Gate), wherein the second gate (FIG. 2a, item Q2 Gate connected to item 10) is electrically connected to the first drain (FIG. 2a, item Q1 drain attached to item 10) and the second source (FIG. 2a, item Q2 source connected to item 5) is electrically connected to the source line (FIG. 2a, item 5);
a read access transistor (FIG. 2a, item Q3) comprising a third source (FIG. 2a, item Q3 source), a third drain (FIG. 2a, item Q3 drain), and a third gate (FIG. 2a, item Q3 Gate), wherein the third source (FIG. 2a, item Q3 source) is electrically connected to the second drain (FIG. 2a, item Q2 drain), the third gate (FIG. 2a, item Q3 Gate connect to item 7) is electrically connected to the read word line (FIG. 2a, item 7, item Wr) and the third drain (FIG. 2a, item Q3 drain connected to item 8) is electrically connected to the read bit line (FIG. 2a, item 8, item Br);
a second oxide definition region (FIG. 5, item second Oxide Definition Region) associated with the storage transistor (FIG. 5, item Q2, storage transistor Q2) and the read access transistor (FIG. 5, item Q3, read access transistor Q3), wherein the second oxide definition region (FIG. 5, item second Oxide Definition Region) is parallel (FIG. 5 shows the second Oxide Definition Region is parallel to the first oxide definition region) to the first oxide definition region (FIG. 5, item first Oxide Definition Region) in plan view (FIG. 5)
a capacitive element (FIG. 2a, item 12) having a first terminal (FIG. 2a, item 10), and a second terminal (FIG. 2a, item 13), wherein the first terminal (FIG. 2a, item 10) is electrically connected to the first drain (FIG. 2a, item Q1 drain attached to item 10) and the second gate (FIG. 2a, item Q2 Gate), and
a continuous region (FIG. 5, item 10) formed over the first oxide definition region (FIG. 5, item first Oxide Definition Region) and the second oxide definition region (FIG. 5, item second Oxide Definition Region) such that the continuous region (FIG. 5, item 10) is substantially perpendicular (FIG. 5, shows item 10 is substantially perpendicular to the first oxide region and the second oxide region) to the first oxide definition region (FIG. 5, item first Oxide Definition Region) and the second oxide definition region (FIG. 5, item second Oxide Definition Region), wherein the capacitive element (FIG. 5, item 700) is formed (FIG. 5 shows item 700 is formed on the first oxide definition region with item Q1) on the continuous region (FIG. 5, item 10) and the first oxide definition region (FIG. 5, item First Oxide Definition Region).
Worley further discloses in NFET write select transistor 3 can save some area by not requiring a Vdd body node line 13 ([Col 2, lines 61-67]).
Since Worley teaches Memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory as disclosed to modify Worley with the teachings of the preferred embodiment as disclosed by Worley. The use of an NFET write select transistor can save some area by not requiring a Vdd body node line 13 in Worley provides for saving area (Worley, [Col 2, lines 61-67]).
Worley fails to explicitly discloses and wherein the second terminal is electrically connected to a ground line, and the continuous region is polysilicon region.
However, Matsuzawa teaches a capacitive element (FIG. 1, item C; [abstract], i.e. an electric charge storing region storing electric charge in accordance with data to be written are formed) having a first terminal (FIG. 1, item S), and a second terminal (FIG. 1, item ground), wherein the first terminal (FIG. 1, item S) is electrically connected to the first drain (FIG. 1, item Q1 drain attached to item S) and the second gate (FIG. 1, item Q3 Gate), and wherein the second terminal (FIG. 1, item S) is electrically connected to a ground line (FIG. 1, item ground).
Since Worley and Matsuzawa teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley with the teachings of wherein the second terminal is electrically connected to a ground line as disclosed by Matsuzawa. The use of an electric charge storing region storing electric charge in accordance with data to be written are formed in Matsuzawa provides for reducing the power required for holding data (Matsuzawa, [0008]).
Worley and Matsuzawa fails to explicitly disclose the continuous region are continuous polysilicon region.
Chen et al teaches a continuous region is a continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Since Worley, Matsuzawa and Chen et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell to modify Worley and Matsuzawa with the teachings of a continuous region is a continuous polysilicon region as disclosed by Chen et al. The use of the floating gate or the select gate may include a conductive material, such as polysilicon in Chen et al provides for integrate with other logic circuits with a minimal number of manufacturing operations in order to save cost (Chen et al, [0015]).
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2244.07
Regarding claim 2. Worley, Matsuzawa, and Chen et al discloses all the limitations of the memory cell of claim 1 above.
Worley further disclose wherein the capacitive element (FIG. 5, item 700) is formed in a region that overlaps at least partially with a shallow trench isolation structure (FIG. 5, first oxide definition region).
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Regarding claim 3. Worley and Matsuzawa discloses all the limitations of the memory cell of claim 1 above.
Worley further disclose wherein the capacitor is configured to maintain a voltage difference between the first terminal and the second terminal during a hold operation ([Col 2, lines 22-25], i.e. include storage capacitor construction techniques to extend refresh times and improve multi-state readability of the 3 transistor dynamic memory cell.).
Regarding claim 8. Worley and Matsuzawa discloses all the limitations of the memory cell of claim 1 above.
Worley further disclose wherein the capacitive element comprises an alternating multi-layer structure including silicon oxide and silicon nitride (Col 5, lines 45-47, i.e. oxide can be used as the capacitor dielectric. It should be noted that any suitable dielectric can be used including nitride, ONO, NO, etc.).
Regarding claim 11. Worley discloses a memory cell, comprising: a first oxide definition region (FIG. 5, first oxide definition region) formed on a substrate (FIG. 6B, item 815);
a second oxide definition region (FIG. 5, second oxide definition region) formed on the substrate (FIG. 6B, item 815);
a first continuous region (FIG. 5, item 12) formed over the first oxide definition region (FIG. 5, first oxide definition region);
a second continuous region (FIG. 5, item 10) formed over the first oxide definition region (FIG. 5, first oxide definition region) and the second oxide definition region (FIG. 5, second oxide definition region) such that the continuous region (FIG. 5, item 10) is substantially perpendicular (FIG. 5, shows item 10 is substantially perpendicular to the first oxide region and the second oxide region) to the first oxide definition region (FIG. 5, item first Oxide Definition Region) and the second oxide definition region (FIG. 5, item second Oxide Definition Region);
a third continuous region (FIG. 5, item 815) formed over the second oxide definition region (FIG. 5, second oxide definition region); and
a capacitive element (FIG. 5, item 700) formed on the first oxide definition region (FIG. 5, first oxide definition region) and the second continuous region (FIG. 5, item 10),
wherein a first portion (FIG. 5, item 12 over item Q1) of the first continuous region (FIG. 5, item 12) is configured to overlap (FIG. 5, item 12 overlaps the first oxide region to for the gate for Q1) the first oxide definition region (FIG. 5, first oxide region) to thereby form a first gate (FIG. 2a, item Q1 gate) of a write access transistor (FIG. 2a, item Q1),
wherein a second portion (FIG. 5, item 2 over item Q2) of the second continuous region (FIG. 5, item 10) is configured to overlap (FIG. 5, item 2 connected to item 10 overlaps the second oxide region to for the gate for Q2) the second oxide definition region (FIG. 5, second oxide definition region) to form a second gate (FIG. 2a, item Q2 gate) of a storage transistor (FIG. 2a, item Q2), and
Wherein the capacitive element (FIG. 2a, item 12) having a first terminal (FIG. 2a, item 10), and a second terminal (FIG. 2a, item 13), wherein the first terminal (FIG. 2a, item 10) is electrically connected to the second gate (FIG. 2a, item Q2 Gate)
wherein a third portion (FIG. 2a, item 7 over item Q3) of the third continuous region (FIG. 5, item 7) is configured to overlap (FIG. 5, item 7 overlaps the second oxide region to for the gate for Q3) the second oxide definition region (FIG. 5, second oxide definition region) to form a third gate (FIG. 2a, item Q3 gate) of a read access transistor (FIG. 2a, item Q3).
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Worley further discloses in NFET write select transistor 3 can save some area by not requiring a Vdd body node line 13 ([Col 2, lines 61-67]).
Since Worley teaches Memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory as disclosed to modify Worley with the teachings of the preferred embodiment as disclosed by Worley. The use of an NFET write select transistor can save some area by not requiring a Vdd body node line 13 in Worley provides for saving area (Worley, [Col 2, lines 61-67]).
Worley fails to explicitly discloses and wherein the second terminal is electrically connected to a ground line, and the continuous region are continuous polysilicon region.
However, Matsuzawa teaches a capacitive element (FIG. 1, item C; [abstract], i.e. an electric charge storing region storing electric charge in accordance with data to be written are formed) having a first terminal (FIG. 1, item S), and a second terminal (FIG. 1, item ground), wherein the first terminal (FIG. 1, item S) is electrically connected to the first drain (FIG. 1, item Q1 drain attached to item S) and the second gate (FIG. 1, item Q3 Gate), and wherein the second terminal (FIG. 1, item S) is electrically connected to a ground line (FIG. 1, item ground).
Since Worley and Matsuzawa teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley with the teachings of wherein the second terminal is electrically connected to a ground line as disclosed by Matsuzawa. The use of an electric charge storing region storing electric charge in accordance with data to be written are formed in Matsuzawa provides for reducing the power required for holding data (Matsuzawa, [0008]).
Worley and Matsuzawa fails to explicitly disclose the continuous region are continuous polysilicon region.
Chen et al teaches the continuous region are continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Since Worley, Matsuzawa and Chen et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell to modify Worley and Matsuzawa with the teachings of the continuous region are continuous polysilicon region as disclosed by Chen et al. The use of the floating gate or the select gate may include a conductive material, such as polysilicon in Chen et al provides for integrate with other logic circuits with a minimal number of manufacturing operations in order to save cost (Chen et al, [0015]).
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2244.07
Regarding claim 12. Worley, Matsuzawa, and Chen et al discloses all the limits of the memory cell of claim 11 above.
Worley further discloses further comprising:
a read bit line (FIG. 2a, item 8, item Br) and a read word line (FIG. 2a, item 7, item Wr);
a write bit line (FIG. 2a, item 9, item Bw) and a write word line (FIG. 2a, item 4, item Ww);
a source line (FIG. 2a, item 5, item 5);
a first contact (FIG. 5, item first contact) formed at a first end (FIG. 5, end of first oxide definition region that has first contact) of the first oxide definition region (FIG. 5, first oxide region) that is electrically coupled with a first source electrode (FIG. 2a, item Q1 source attached to item 9) of the write access transistor (FIG. 2a, item Q1), wherein the first contact (FIG. 5, item first contact) is electrically connected to the write bit line (FIG. 2a, item 9, item Bw) such that the first source electrode (FIG. 2a, item Q1 source attached to item 9) of the write access transistor (FIG. 2a, item Q1) is electrically connected to the write bit line (FIG. 2a, item 9, item Bw);
a second contact (FIG. 5, item second contact) formed at a first end (FIG. 5, first end of item 12 connected to item 4), item of the first continuous region (FIG. 5, item 12) and electrically connected to the write word line (FIG. 2a, item 4, item Ww) such that the first gate (FIG. 2a, item Q1 gate) of the write access transistor (FIG. 2a, item Q1) is electrically connected to the write word line (FIG. 2a, item 4, item Ww);
a third contact (FIG. 5, item third contact connected to item 5; FIG. 2a, item Q2 source connected to item 5) formed at a first end (FIG. 5, a first end of the second oxide definition region connected to item 5) of the second oxide definition region (FIG. 5, second oxide definition region) that is electrically coupled with a second source electrode (FIG. 2a, item Q2 source connected to 5) of the storage transistor (FIG. 2a, item Q2), wherein the third contact (FIG. 5, item third contact) is electrically connected (FIG. 5, a third contact connected to item 5) to the source line (FIG. 2a, item 5, item 5) such that the second source electrode(FIG. 2a, item Q2 source connected to 5) of the storage transistor (FIG. 2a, item Q2) is connected to the source line (FIG. 2a, item 5, item 5);
a fourth contact (FIG. 5, item fourth contact) formed at a first end (FIG. 5, a first end of item 7 connected to item Wr) of the third continuous region (FIG. 5, item 7) and electrically connected to the read word line (FIG. 2a, item 7, item Wr) such that the third gate (FIG. 2a, item Q3 gate) of the read access transistor (FIG. 2a, item Q3) is electrically connected to the read word line (FIG. 2a, item 7, item Wr); and
a fifth contact (FIG. 5, item fifth contact) formed at a second end (FIG. 5, a second end of the second oxide definition region connected to Q3 drain) of the second oxide definition region (FIG. 5, second oxide definition region) that is electrically coupled with a third drain electrode (FIG. 2a, item Q3 drain) of the read access transistor (FIG. 2a, item Q3), wherein the fifth contact (FIG. 5, item fifth contact) is electrically connected to the read bit line (FIG. 2a, item 8, item Br) such that the third drain electrode (FIG. 2a, item Q3 drain) of the read access transistor (FIG. 2a, item Q3) is electrically connected to the read bit line (FIG. 2a, item 8, item Br);
wherein the first oxide definition region (FIG. 5, first oxide definition region) and the second continuous region (FIG. 5, item 10) are configured such that a first drain (FIG. 2a, item Q1 drain attached to item 10) of the write access transistor (FIG. 2a, item Q1) is electrically connected to the second gate (FIG. 2a, item Q2 gate attached to item 10) of the storage transistor (FIG. 2a, item Q2), and wherein the second oxide definition region (FIG. 5, second oxide definition region) is configured such that a second drain (FIG. 2a, item Q2 drain attached to Q3) of the storage transistor (FIG. 2a, item Q2) is electrically connected to a third source (FIG. 2a, item Q3 source attached to Q2) of the read access transistor (FIG. 2a, item Q3).
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Chen et al discloses the continuous region are continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Regarding claim 13. Worley, Matsuzawa, and Chen discloses all the limits of the memory cell of claim 11 above.
Worley further discloses wherein the first oxide definition region and the second oxide definition region each have a common width (FIG. 5 discloses common width of first and second oxide e definition region).
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Regarding claim 16. Worley discloses a method of fabricating a memory cell, comprising:
forming a first oxide definition region (FIG. 5, first oxide definition region) on a substrate (FIG. 6B, item 815);
forming a second oxide definition region (FIG. 5, second oxide definition region) on the substrate (FIG. 6B, item 815) such that the first oxide definition region (FIG. 5, item first Oxide Definition Region) is parallel (FIG. 5 shows the first Oxide Definition Region is parallel to the second oxide definition region) to the second oxide definition region (FIG. 5, item second Oxide Definition Region) in plan view (FIG. 5);
forming a first continuous region (FIG. 5, item 12) over the first oxide definition region (FIG. 5, first oxide definition region);
forming a second continuous region (FIG. 5, item 10) over and electrically connected to the first oxide definition region (FIG. 5, first oxide definition region), and overlapping the second oxide definition region (FIG. 5, second oxide definition region), wherein the second continuous region (FIG. 5, item 10) is substantially perpendicular (FIG. 5, shows item 10 is substantially perpendicular to the first oxide region and the second oxide region) to the first oxide definition region (FIG. 5, item first Oxide Definition Region) and the second oxide definition region (FIG. 5, item second Oxide Definition Region);
forming a third continuous region (FIG. 5, item 7) over the second oxide definition region (FIG. 5, second oxide definition region); and
forming a capacitive element (FIG. 5, item 700) on one of the first oxide definition region (FIG. 5, first oxide definition region), and the second continuous region (FIG. 5, item 10),
wherein forming the first continuous region (FIG. 5, item 12) further comprises configuring a first portion (FIG. 5, item 12 over item Q1) of the first continuous region (FIG. 5, item 12) to overlap (FIG. 5, item 12 overlaps the first oxide region for the gate for Q1) with the first oxide definition region (FIG. 5, first oxide definition region) to thereby form a first gate (FIG. 2a, item Q1 gate) of a write access transistor (FIG. 2a, item Q1),
wherein forming the second continuous region (FIG. 5, item 10) further comprises configuring a second portion (FIG. 5, item 10 over item Q2) of the second continuous region (FIG. 5, item 10) to overlap (FIG. 5, item 10 overlaps the second oxide region for the gate for Q2) with the second oxide definition region (FIG. 5, second oxide definition region) to thereby form a second gate (FIG. 2a, item Q2 gate) of a storage transistor (FIG. 2a, item Q1 gate), and
Wherein forming the capacitive element (FIG. 2a, item 12) comprises forming a first terminal (FIG. 2a, item 10), and a second terminal (FIG. 2a, item 13) of the capacitive element (FIG. 2a, item 12), wherein the first terminal (FIG. 2a, item 10) is electrically connected to the second gate (FIG. 2a, item Q2 Gate)
wherein forming the third continuous region (FIG. 2a, item 7) further comprises configuring a third portion (FIG. 2a, item 7 over item Q3) of the third continuous polysilicon region (FIG. 2a, item 7) to overlap with the second oxide definition region to thereby form a third gate (FIG. 2a, item Q3 gate) of a read access transistor (FIG. 2a, item Q3).
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Worley further discloses in NFET write select transistor 3 can save some area by not requiring a Vdd body node line 13 ([Col 2, lines 61-67]).
Since Worley teaches Memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory as disclosed to modify Worley with the teachings of the preferred embodiment as disclosed by Worley. The use of an NFET write select transistor can save some area by not requiring a Vdd body node line 13 in Worley provides for saving area (Worley, [Col 2, lines 61-67]).
Worley fails to explicitly discloses and wherein the second terminal is electrically connected to a ground line and the continuous region are continuous polysilicon region.
However, Matsuzawa teaches a capacitive element (FIG. 1, item C; [abstract], i.e. an electric charge storing region storing electric charge in accordance with data to be written are formed) having a first terminal (FIG. 1, item S), and a second terminal (FIG. 1, item ground), wherein the first terminal (FIG. 1, item S) is electrically connected to the first drain (FIG. 1, item Q1 drain attached to item S) and the second gate (FIG. 1, item Q3 Gate), and wherein the second terminal (FIG. 1, item S) is electrically connected to a ground line (FIG. 1, item ground).
Since Worley and Matsuzawa teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley with the teachings of wherein the second terminal is electrically connected to a ground line as disclosed by Matsuzawa. The use of an electric charge storing region storing electric charge in accordance with data to be written are formed in Matsuzawa provides for reducing the power required for holding data (Matsuzawa, [0008]).
Worley and Matsuzawa fails to explicitly disclose the continuous region are continuous polysilicon region.
Chen et al teaches the continuous region are continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Since Worley, Matsuzawa and Chen et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley and Matsuzawa with the teachings of the continuous region are continuous polysilicon region as disclosed by Chen et al. The use of the floating gate or the select gate may include a conductive material, such as polysilicon in Chen et al provides for integrate with other logic circuits with a minimal number of manufacturing operations in order to save cost (Chen et al, [0015]).
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2244.07
Regarding claim 17. Worley, Matsuzawa and Chen et al discloses all the limits of the memory cell of claim 16 above.
Worley further discloses further comprising:
forming a read bit line (FIG. 2a, item 8, item Br) and a read word line (FIG. 2a and 5, item 7, item Wr);
forming a write bit line (FIG. 2a, item 9, item Bw) and a write word line (FIG. 2a and 5, item 4, item Ww);
forming a source line (FIG. 2a and 5, item 5);
forming a first contact (FIG. 2a and 5, item Q1 source) at a first end (FIG. 5, end of first oxide definition region that has first contact; FIG. 5 and 2a, item Q1 source) of the first oxide definition region (FIG. 5, first oxide definition region) to thereby form a first source (FIG. 2a, item Q1 source attached to item 9) of the write access transistor (FIG. 2a and 5, item Q1);
electrically connecting the first contact (FIG. 2a and 5, item first contact) to the write bit line (FIG. 2a, item 9, item Bw) such that the first source (FIG. 2a and 5, item Q1 source attached to item 9) is electrically connected to the write bit line (FIG. 2a, item 9, item Bw);
forming a second contact (FIG. 2a and 5, item second contact, Q1 gate contact) at a first end (FIG. 5, first end of item 12 connected to item 4) of the first continuous region (FIG. 5, item 12);
electrically connecting the second contact (FIG. 2a and 5, item second contact, Q1 gate contact) to the write word line (FIG. 2a, item 4, item Ww) such that the first gate (FIG. 2a, item Q1 gate) is electrically connected (FIG. 2a, item Q1 gate attached item 4, item) to the write word line (FIG. 2a, item 4, item Ww);
forming a third contact (FIG. 5, item third contact connected to item 5; FIG. 2a, item Q2 source connected to item 5) at a first end of the second oxide definition region (FIG. 5, second oxide definition region) to thereby form a second source (FIG. 2a, item Q2 source connected to item 5) of the storage transistor (FIG. 2a, item Q2); electrically connecting the third contact (FIG. 5, item third contact connected to item 5; FIG. 2a, item Q2 source connected to item 5) to the source line (FIG. 2a, item 5) such that the second source (FIG. 2a, item Q2 source connected to item 5) is connected to the source line (FIG. 2a and 5, item 5);
forming a fourth contact (FIG. 5, item fourth contact) at a first end (FIG. 5, a first end of item 7 connected to item Wr) of the third continuous region (FIG. 5, item 7); electrically connecting the fourth contact to the read word line (FIG. 2a, item 7, item Wr) such that the third gate (FIG. 2a, item Q3 gate attached to item 7) is electrically connected to the read word line (FIG. 2a, item 7, item Wr);
forming a fifth contact (FIG. 2a, item Q3 drain) at a second end of the second oxide definition region (FIG. 5, second oxide definition region) to thereby form a third drain (FIG. 2a, item Q3 drain) of the read access transistor (FIG. 2a, item Q3); and
electrically connecting the fifth contact (FIG. 5, item fifth contact) to the read bit line (FIG. 2a, item 8, item Br) such that the third drain (FIG. 2a and 5, item Q3 drain attached to item 8) is electrically connected to the read bit line (FIG. 2a and 5, item 8, item Br), wherein the first oxide definition region (FIG. 2a and 5, first oxide definition region) and the second continuous region (FIG. 5, item 10) are configured such that a first drain (FIG. 2a and 5, item Q1 drain attached to item 10) of the write access transistor (FIG. 2a and 5, item Q1) is electrically connected to the second gate (FIG. 2a and 5, item Q2 gate), and wherein the second oxide definition region (FIG. 5, second oxide definition region) is configured such that a second drain (FIG. 2a and 5, item Q2 drain) of the storage transistor (FIG. 2a, item Q2) is electrically connected to a third source (FIG. 2a and 5, item Q3 source) of the read access transistor (FIG. 2a and 5, item Q3).
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Worley and Matsuzawa fails to explicitly disclose the continuous region are continuous polysilicon region.
Chen et al discloses the continuous region are continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Since Worley, Matsuzawa and Chen et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley and Matsuzawa with the teachings of the continuous region are continuous polysilicon region as disclosed by Chen et al. The use of the floating gate or the select gate may include a conductive material, such as polysilicon in Chen et al provides for integrate with other logic circuits with a minimal number of manufacturing operations in order to save cost (Chen et al, [0015]).
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). "Reading a list and selecting a known compound to meet known requirements is no more ingenious than selecting the last piece to put in the last opening in a jig-saw puzzle." 325 U.S. at 335, 65 USPQ at 301.). See MPEP 2244.07
Regarding claim 21. Worley, Matsuzawa, and Chen discloses all the limits of the memory cell of claim 1 above.
Worley further disclose further comprising:
a first contact (FIG. 2a and 5, item Q1 source) formed at a first end (FIG. 5, end of first oxide definition region that has first contact; FIG. 5 and 2a, item Q1 source) of the first oxide definition region (FIG. 5, first oxide definition region) that is electrically coupled with the first source electrode (FIG. 2a and 5, item Q1 source attached to item 9) of the write access transistor (FIG. 2a and 5, item Q1), wherein the first contact (FIG. 2a and 5, item Q1 source) is electrically connected to the write bit line (FIG. 2a, item 9, item Bw);
a third contact (FIG. 5, item third contact connected to item 5; FIG. 2a, item Q2 source connected to item 5) formed at a first end of the second oxide definition region (FIG. 5, second oxide definition region) that is electrically coupled with the second source electrode (FIG. 2a, item Q2 source connected to item 5) of the storage transistor (FIG. 2a, item Q2), wherein the third contact (FIG. 5, item third contact connected to item 5; FIG. 2a, item Q2 source connected to item 5) is electrically connected to the source line (FIG. 2a and 5, item 5); and
a fifth contact (FIG. 5, item fifth contact) formed at a second end of the second oxide definition region that is electrically coupled with the third drain electrode (FIG. 2a, item Q3 drain) of the read access transistor (FIG. 2a, item Q3), wherein the fifth contact (FIG. 5, item fifth contact) is electrically connected to the read bit line (FIG. 2a and 5, item 8, item Br);
wherein the first oxide definition region (FIG. 2a and 5, first oxide definition region) and the second continuous region (FIG. 5, item 10) are configured such that the first drain (FIG. 2a and 5, item Q1 drain attached to item 10) of the write access transistor (FIG. 2a and 5, item Q1) is electrically connected to the second gate (FIG. 2a and 5, item Q2 gate) of the storage transistor (FIG. 2a, item Q2), and
wherein the second oxide definition region (FIG. 5, second oxide definition region) is configured such that the second drain (FIG. 2a and 5, item Q2 drain) of the storage transistor r(FIG. 2a, item Q2) is electrically connected to the third source (FIG. 2a and 5, item Q3 source) of the read access transistor (FIG. 2a and 5, item Q3).
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Worley and Matsuzawa fails to explicitly disclose the continuous region are continuous polysilicon region.
Chen et al discloses the continuous region are continuous polysilicon region ([0017], i.e. The floating gate 120 or the select gate 130 may include a conductive material, such as polysilicon).
Since Worley, Matsuzawa and Chen et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley and Matsuzawa with the teachings of the continuous region are continuous polysilicon region as disclosed by Chen et al. The use of the floating gate or the select gate may include a conductive material, such as polysilicon in Chen et al provides for integrate with other logic circuits with a minimal number of manufacturing operations in order to save cost (Chen et al, [0015]).
The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945). See MPEP 2244.07
Regarding claim 22. Worley, Matsuzawa, and Chen discloses all the limits of the memory cell of claim 1 above.
Worley further discloses wherein the first oxide definition region and the second oxide definition region each have a common width (FIG. 5 discloses common width of first and second oxide definition region).
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Claims 4-7 are rejected under 35 U.S.C. 103 as being unpatentable over Worley (U.S. Patent 6,016,268), Matsuzawa (U.S. 2007/0133337), and Chen et al (U.S. 2017/0125425) as applied to claim 1 above, and further in view of Then et al (U.S. 2023/0050491).
Regarding claim 4. Worley, Matsuzawa, and Chen et al discloses all the limitations of the memory cell of claim 1 above.
Worley further discloses wherein the capacitive element (col 6, lines 35-50) comprises a dielectric element (FIG. 6, item 814) sandwiched between a first conductor (FIG. 6, item 801) and a second conductor (FIG. 6, item 802).
Worley further discloses that any suitable dielectric can be used (Col 5, lines 46-47).
Worley, Matsuzawa, and Chen et al fails to explicitly disclose the capacitive element comprises a high-k dielectric.
However, Then et al teaches the capacitive element (FIG. 2, item 200) comprises a high-k dielectric element ([0035], i.e. Referring to FIG. 2, a MIM stack 200 includes a plurality of alternating conductive layers 208 (e.g., layers of titanium nitride, TiN, which can be referred to as electrode plates and high-k dielectric layers 210A, 210B, 210C, 210D, 210E).
Since Worley, Matsuzawa, Chen et al and Then et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed to modify Worley, Matsuzawa, and Chen et al with the teachings of the capacitive element comprises a high-k dielectric as disclosed by Then et al. The use of layers of titanium nitride, TiN, which can be referred to as electrode plates and high-k dielectric layers in Then et al provides for a capacitor divider with smaller voltages across higher dielectric constant layers, e.g., and can be self-adjusting (Then et al, [0035]).
Regarding claim 5. Worley, Matsuzawa, Chen et al, and Then et al discloses all the limitations of the memory cell of claim 4 above.
Then et al further discloses wherein the first conductor and the second conductor comprise one or more of TiN and TaN ([0035], i.e. Referring to FIG. 2, a MIM stack 200 includes a plurality of alternating conductive layers 208 (e.g., layers of titanium nitride, TiN, which can be referred to as electrode plates).
Regarding claim 6. Worley, Matsuzawa, Chen et al, and Then et al discloses all the limitations of the memory cell of claim 4 above.
Then et al further discloses wherein the high-k dielectric element ([0035], i.e. high-k dielectric layers 210A, 210B, 210C, 210D, 210E) comprises one or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina ([0048], i.e. the high-k dielectric layers described above are composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof).
Regarding claim 7. Worley, Matsuzawa, and Then et al discloses all the limitations of the memory cell of claim 4 above.
Then et al further discloses wherein the high-k dielectric element comprises a multilayer structure ([0035], i.e. high-k dielectric layers 210A, 210B, 210C, 210D, 210E) comprising two or more layers, respectively, of two or more of hafnium oxide, hafnium lanthanum oxide, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, zirconium oxide, titanium oxide, aluminum oxide, and hafnium dioxide-alumina ([0048], i.e. the high-k dielectric layers described above are composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Worley (U.S. Patent 6,016,268), Matsuzawa (U.S. 2007/0133337), and Chen et al (U.S. 2017/0125425) as applied to claim 11 above, and further in view of Liaw et al (U.S. 2013/0121087).
Regarding claim 14. Worley, Matsuzawa and Chen et al discloses all the limitations of the memory cell of claim 11.
Worley further discloses the first oxide definition region and the second oxide definition region.
Worley et al fails to explicitly disclose are each formed as fin structures such that the write access transistor, the storage transistor, and the read access transistor are formed as FinFET devices.
However, Liaw teaches each formed as fin structures ([0016]) such that the write access transistor, the storage transistor, and the read access transistor ([0015], i.e. transistors 126, 128, and 130 are NMOS transistors, although one skilled in the art will understand that transistors 126, 128, and 130 may be implemented as PMOS transistors. Transistor 126 has its gate coupled to write word line W_WL at node 132, its source coupled to node 116, and its drain coupled to write bit line W_BLB at node 134. Transistor 128 has its gate coupled to write word line W_WL at node 136, its source coupled to node 120, and its drain coupled to write bit line W_BL at node 138. Transistor 130 has its source coupled to pull down transistor 140, its drain coupled to read bit line R_BL at node 142, and its gate coupled to read word line R_WL at node 144. Transistor 140 has its source coupled to VSS) are formed as FinFET devices ([0016], i.e. As will be understood by one skilled in the art, the transistors of bit cell 102 may be MOSFETS, FinFETs, silicon-on-insulator ("SOI") transistors, SOI FinFETs, and combinations thereof.)
Since Both Worley and Liaw teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed in Worley with the transistors 126, 128, and 130 are NMOS transistors, although one skilled in the art will understand that transistors 126, 128, and 130 may be implemented as PMOS transistors. Transistor 126 has its gate coupled to write word line W_WL at node 132, its source coupled to node 116, and its drain coupled to write bit line W_BLB at node 134. Transistor 128 has its gate coupled to write word line W_WL at node 136, its source coupled to node 120, and its drain coupled to write bit line W_BL at node 138. Transistor 130 has its source coupled to pull down transistor 140, its drain coupled to read bit line R_BL at node 142, and its gate coupled to read word line R_WL at node 144. Transistor 140 has its source coupled to VSS as disclosed by Liaw. The use of FinFETs, silicon-on-insulator ("SOI") transistors, SOI FinFETs in Liaw provides for devices that form the write port of the bit cell are implemented with higher threshold voltages than the read port to provide improved cell stability and the lower threshold voltages in the devices that form the read port advantageously provide higher drive current for improved read speed (Liaw, [0016]).
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Worley (U.S. Patent 6,016,268), Matsuzawa (U.S. 2007/0133337), and Chen et al (U.S. 2017/0125425) as applied to claim 11 above, and further in view of Then et al (U.S. 2023/0050491).
Regarding claim 15. Worley, Matsuzawa and Chen et al discloses all the limitations of the memory cell of claim 11 above.
Worley further discloses wherein the capacitive element (col 6, lines 35-50) comprises a dielectric element (FIG. 6, item 814) sandwiched between a first conductor (FIG. 6, item 801) and a second conductor (FIG. 6, item 802).
Worley further discloses that any suitable dielectric can be used (Col 5, lines 46-47).
Worley fails to explicitly disclose the capacitive element comprises a high-k dielectric.
However, Then et al teaches the capacitive element (FIG. 2, item 200) comprises a high-k dielectric element ([0035], i.e. Referring to FIG. 2, a MIM stack 200 includes a plurality of alternating conductive layers 208 (e.g., layers of titanium nitride, TiN, which can be referred to as electrode plates and high-k dielectric layers 210A, 210B, 210C, 210D, 210E).
Since Both Worley and Then et al teach memory, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed in Worley with the capacitive element comprises a high-k dielectric as disclosed by Then et al. The use of layers of titanium nitride, TiN, which can be referred to as electrode plates and high-k dielectric layers in Then et al provides for a capacitor divider with smaller voltages across higher dielectric constant layers, e.g., and can be self-adjusting (Then et al, [0035]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Worley (U.S. Patent 6,016,268), Matsuzawa (U.S. 2007/0133337), and Chen et al (U.S. 2017/0125425) as applied to claim 16 above, and further in view of Liaw et al (U.S. 2013/0121087).
Regarding claim 20. Worley, Matsuzawa and Chen et al discloses all the limitations of the memory cell of claim 16.
Worley further discloses the first oxide definition region and the second oxide definition region.
Worley et al fails to explicitly disclose are each formed as fin structures such that the write access transistor, the storage transistor, and the read access transistor are formed as FinFET devices.
However, Liaw teaches each formed as fin structures ([0016]) such that the write access transistor, the storage transistor, and the read access transistor ([0015], i.e. transistors 126, 128, and 130 are NMOS transistors, although one skilled in the art will understand that transistors 126, 128, and 130 may be implemented as PMOS transistors. Transistor 126 has its gate coupled to write word line W_WL at node 132, its source coupled to node 116, and its drain coupled to write bit line W_BLB at node 134. Transistor 128 has its gate coupled to write word line W_WL at node 136, its source coupled to node 120, and its drain coupled to write bit line W_BL at node 138. Transistor 130 has its source coupled to pull down transistor 140, its drain coupled to read bit line R_BL at node 142, and its gate coupled to read word line R_WL at node 144. Transistor 140 has its source coupled to VSS) are formed as FinFET devices ([0016], i.e. As will be understood by one skilled in the art, the transistors of bit cell 102 may be MOSFETS, FinFETs, silicon-on-insulator ("SOI") transistors, SOI FinFETs, and combinations thereof.)
Since Both Worley and Liaw teach memory devices, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the memory cell as disclosed in Worley with the transistors 126, 128, and 130 are NMOS transistors, although one skilled in the art will understand that transistors 126, 128, and 130 may be implemented as PMOS transistors. Transistor 126 has its gate coupled to write word line W_WL at node 132, its source coupled to node 116, and its drain coupled to write bit line W_BLB at node 134. Transistor 128 has its gate coupled to write word line W_WL at node 136, its source coupled to node 120, and its drain coupled to write bit line W_BL at node 138. Transistor 130 has its source coupled to pull down transistor 140, its drain coupled to read bit line R_BL at node 142, and its gate coupled to read word line R_WL at node 144. Transistor 140 has its source coupled to VSS as disclosed by Liaw. The use of FinFETs, silicon-on-insulator ("SOI") transistors, SOI FinFETs in Liaw provides for devices that form the write port of the bit cell are implemented with higher threshold voltages than the read port to provide improved cell stability and the lower threshold voltages in the devices that form the read port advantageously provide higher drive current for improved read speed (Liaw, [0016]).
Response to Arguments
Applicant's arguments filed September 4, 2025 have been fully considered but they are not persuasive.
On pages 12-13 of applicant’s remarks, applicant appears to argue that Worly and Matsuzawa fail to provide any teaching or suggestion regarding the configuration of the first oxide definition region, the second oxide definition region, the continuous polysilicon region in plan view and/or the configuration of these elements in relation to the capacitive element as recited in amended independent claim 1.
Examiner respectfully disagrees as Worley, Matsuzawa and Chen et al discloses applicant’s amended claim 1 limitation as cited in the rejection above and shown in the annotated figure of Worly above.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 13 of applicant’s remarks, applicant appears to argue that Then et al fail to disclose the limitations of claim 4, because Then et al does not teach the limitations of claim 1.
Examiner respectfully disagrees for the reasons stated above.
On pages 14-16 of applicant’s remarks, applicant appears to present substantially the same arguments as for claim 1 above. The Examiner respectfully disagrees for the reasons sated above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shinohara (U.S. 5,089,992) discloses a semiconductor memory device and a data path using the same.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SCOTT E BAUMAN whose telephone number is (469)295-9045. The examiner can normally be reached M-F, 9-5 CST.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815