DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Remarks
The 09/05/2025 amendments of claims 14, 16, 19, 21, 23, and 25 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Remarks pages 1-5, filed 09/05/2025, with respect to the rejection(s) of claim(s) 14-16, 19, 21-27, 29-31 and 37-38 under 35 U.S.C 103 have been fully considered and are persuasive in light of the newly introduced amendments. However, upon further consideration, it appears that previously cited art reference Lin et al, US 20210335782 A1 (Lin ‘782) teaches the newly added amendments.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 16, 19 and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al, US 20210335782 A1 (Lin ‘782) in view of Chen et al, US 20190097013 A1 (Chen ‘013).
Regarding claim 14; Lin ‘782 teaches a method for forming a semiconductor structure comprising: receiving a substrate (10) having a first region (R2) and a second region (R1); forming a first dielectric layer (GOX) in the first region (R2) and a second dielectric layer (IL) in the second region (R1), wherein a thickness of the second dielectric layer (IL) is less than a thickness of the first dielectric layer (GOX); forming a first sacrificial gate (SK1) structure in the first region (R2) and a second sacrificial gate structure (SK1) in the second region (R1) wherein a width of the first sacrificial gate (SK2) structure is greater than a width of the second sacrificial gate structure (SK1); forming a dielectric structure (40a) over the substrate (10) and surrounding the first sacrificial gate (SK2) structure and the second sacrificial structure (SK1); and removing the first sacrificial gate (SK2) structure to form a first gate trench (T2), and removing the second sacrificial gate structure (SK1) to form a second gate trench (T1) in the second region (R1); and a plurality of pillars (40a) in the first gate trench (T2) in the first region (R2), and forming a first metal gate structure (MG2) in the first gate trench (T2) and a second metal gate structure (MG1) in the second gate trench (T1), wherein the first metal gate structure (MG1) surrounds the pillars (40a) (the gate structure (MG1) will surround the pillars (40a) due to how they repeat in the structure of the device), and the pillars (40a) are disposed within a boundary (Boundary of Metal Gate Structure – see annotated Fig (3K) of Lin ‘782 shared below) of the first metal gate structure (MG2).
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Lin ‘782 does not teach the second dielectric layer is in contact with a sidewall of the first dielectric layer. However, Chen ‘013 teaches the second dielectric layer (902) is in contact with a sidewall of the first dielectric layer (806). Lin ‘782 and Chen ‘013 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lin ‘782 by introducing the second dielectric layer being in contact with the sidewall of the first dielectric layer as disclosed in Chen ‘013 to improve the protection of the device substrate during the several steps needed to process the device minimizing potential damage to the substrate.
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Regarding claim 16; Lin ‘782 in view of Chen ‘013 teach all the limitations of claim 14.
Further, Lin ‘782 teaches further, comprising forming a first source/drain (22) in the first region (R2) at opposite sides of the first sacrificial gate structure (SK2), wherein all the pillars (40a) are offset from the first source/drain (22) (Offset – see annotated Fig (3K) of Lin ‘782 shared in this OA).
Regarding claim 19; Lin ‘782 in view of Chen ‘013 teach all the limitations of claim 14.
Further, Lin ‘782 teaches the pillars (40a) are formed within a boundary of the first metal gate structure (MG2) (Boundary of Metal Gate Structure – see annotated Fig (3k) of Lin ‘782 shared in this OA).
Regarding claim 37; Lin ‘782 in view of Chen ‘013 teach all the limitations of claim 14.
Further, Lin ‘782 teaches wherein the pillars (40a) are periodically or randomly arranged.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lin et al, US 20210335782 A1 (Lin ‘782) in view of Chen et al, US 20190097013 A1 (Chen ‘013) in further view of Chen et al, US 20210265344 A1 (Chen ‘344).
Regarding claim 15; Lin ‘782 in view of Chen ‘013 teaches all the limitations of claim 14.
Further, Lin ‘782 teaches wherein the forming of the first dielectric layer (GOX) and the second dielectric layer (IL) further comprises forming the first dielectric layer in the first region (R2); forming a first mask layer (HM) in the second region (R1), removing the first mask layer; forming a second mask layer (PR1) in the first region (R2); and forming the second dielectric layer (IL) in the second region (R1).
Lin ‘782 in view of Chen ‘013 teaches all the above claimed subject matter.
However, Lin ‘782 in view of Chen ‘013 does not teach a tilted step is formed at a boundary between the first dielectric layer and the second dielectric layer.
Chen ‘344 teaches a tilted step (204s) formed at a boundary between the first dielectric layer (202) and the second dielectric layer (120) (Figs (3) and (4) – Chen ‘344). Lin ‘782 in view of Chen ‘013 and Chen ‘344 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lin ‘782 in view of Chen ‘013 by etching the supporting material layers with a slanted sidewall as disclosed in Chen ‘344 to facilitate better etching of layers without residue being left behind.
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Claims 21-27, 29-31 and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al, US 20210335782 A1 (Lin ‘782) in view of Chen et al, US 20210265344 A1 (Chen ‘344)
Regarding claim 21; Lin ‘782 teaches a method for forming a semiconductor structure comprising: forming a first dielectric layer (GOX) and a second dielectric layer (IL) over a substrate (10); forming a first sacrificial gate structure (SK2) and a plurality of openings in the first sacrificial gate structure (SK2), and a second sacrificial gate structure (SK1); wherein the plurality of openings (openings between the gate structures) are formed within a boundary of the first sacrificial gate structure (Boundary of Metal Gate Structure – see annotated Fig (3k) of Lin ‘782 shared in this OA); forming a protecting layer (P1) over the second sacrificial gate structure (SK1); removing portions of the first dielectric layer (IL) exposed through the protecting layer (P1) (see Figs (3C) and (3D)); forming a dielectric structure (40a) over the substrate (10) and surrounding the first sacrificial gate structure (SK2) and the second sacrificial gate structure (SK1), wherein the plurality of openings are filled with the dielectric structure (40a); removing a portion of the dielectric structure (paragraph [0026] discusses the use of processes such CMP to remove the top portion of the dielectric layer (40a)) to expose top surfaces of the first sacrificial gate structure (SK2) and the second sacrificial gate structure (SK1), wherein portions of the dielectric structure remaining in the plurality of openings form a plurality of dielectric pillars (40a) surrounded by the first sacrificial gate structure (SK2); removing the first sacrificial gate structure (SK2) to form a first gate trench (T2), and removing the second sacrificial gate structure (SK1) to form a second gate trench (T1); and forming a first metal gate structure (MG2) in the first gate trench and a second metal gate structure (MG1) in the second gate trench (T1), wherein the first metal gate structure (MG2) surrounds the dielectric pillars (40a). (Figs (3I) and (3J)
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Lin ‘782 does not teach wherein sidewalls of the second dielectric layer are in contact with the protecting layer. However, Chen ‘344 teaches wherein sidewalls of the second dielectric layer (120) are in contact with the protecting layer (2002). Lin ‘782 and Chen ‘344 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Lin ‘782 by using the protective layer in contact with sides of the second dielectric layer as disclosed in Chen ‘344 to improve its protection while processing and patterning the different layers in the other active area of the die lowering the chances of damaging the second dielectric layer and thus making the production process of the device more efficient and reliable.
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Regarding claim 22; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein a thickness of the second dielectric layer (IL) is less than a thickness of the first dielectric layer (GOX).
Regarding claim 23; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches the removing of the portions of the first dielectric layer (GOX1) exposed through the protecting layer (PR2) further deepens the openings (Opening – see figures (3C) and (3D) of Lin’782).
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Regarding claim 24; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein a width of the first sacrificial gate (SK2) structure is greater than a width of the second sacrificial gate structure (SK1).
Regarding claim 25; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches further comprising: forming a first spacer (S2) over sidewalls of the first sacrificial gate structure (SK2) and a second spacer (S1) over sidewalls of the second sacrificial gate structure (SK1), wherein a bottom of the first spacer (S2) is in contact with the first dielectric layer (GOX2).
Regarding claim 26; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein the forming of the first sacrificial gate structure (SK2), the second sacrificial gate structure (SK1) and the plurality of openings further comprises: forming a high-k dielectric layer (HK) over the first dielectric layer (GOX) and the second dielectric layer (IL); forming a sacrificial layer over the high-k dielectric layer (PR1); and removing portions of the sacrificial layer (PR1) and portions of the high-k dielectric layer to form the first sacrificial gate structure (SK2), the second sacrificial gate structure (SK1), and the plurality of openings in the first sacrificial gate structure (SK2), wherein portions of the first dielectric layer (OGX) are exposed through the first sacrificial gate structure (SK2) and bottoms of the plurality of openings, and portions of the second dielectric layer (IL) are exposed through the second sacrificial gate structure (SK1).
Regarding claim 27; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 26.
Further, Lin ‘782 teaches removing the portions of the second dielectric layer (IL) exposed through the second sacrificial gate structure (SK1).
Regarding claim 29; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein the forming of the first metal gate (MG2) structure and second metal gate structure (MG1) further comprising: forming a work function metal layer (paragraphs [0050] and [0051] indicate that the gate metal structure can contain a work function metal layer) in the first gate trench (T2) and the second gate trench (T1); forming a gap-filling metal layer ((MG1) and (MG2)) to fill the first gate trench (T2) and the second gate trench (T1); and removing superfluous work function metal layer and gap-filling metal layer to form the first metal gate structure (MG2) and the second metal gate structure (MG1), wherein a width of the gap-filling metal layer of the first metal gate structure (MG2) is greater than a width of the gap-filling metal layer of the second metal gate (MG1) structure.
Regarding claim 30; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 29.
Further, Lin ‘782 teaches wherein the work function metal layer ((MG2) - paragraphs [0050] and [0051] indicate that the gate metal structure can contain a work function metal layer) of the first metal gate structure (MG2) is separated from the substrate by the high-k dielectric layer (HK) and the first dielectric layer (GOX).
Regarding claim 31; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein a sidewall of at least one of the plurality of dielectric pillars (40a) is in contact with the first dielectric layer (GOX).
Regarding claim 38; Lin ‘782 in view of Chen ‘344 teaches all the claimed limitations of claim 21.
Further, Lin ‘782 teaches wherein the openings (Fig (3A) shows openings in the sacrificial layer (PR1)) are periodically or randomly arranged.
Allowable Subject Matter
Claims 32-35 are allowable. The following is a statement of reasons for the indication of allowable subject matter which are highlighted in what follows:
Regarding claim 32; Lin ‘782 teaches a method for forming a semiconductor structure comprising: receiving a substrate having a first region defined by a first isolation structure and a second region defined by second isolation structure; forming a first dielectric layer over the substrate in the first region; forming a second dielectric layer over the substrate in the second region; forming a first sacrificial gate structure and a plurality of openings in the first sacrificial gate structure in the first region, a second sacrificial gate structure in the second region; forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial gate structure, and a plurality of dielectric pillars filling the plurality of openings; and replacing the first sacrificial gate structure with a first metal gate structure and replacing the second sacrificial gate structure with a second metal gate structure, wherein the first metal gate structure surrounds the dielectric pillars.
However, Lin ‘782 in view of Chen ‘344 alone or in combination with other available art does not teach: wherein the forming of the first dielectric layer further comprises: forming a first patterned mask in the second region; performing a first operation to form a first sub-dielectric layer in the first region; performing a second operation to form a second sub-dielectric layer in the first region and the second region; forming a second patterned mask in the first region, wherein the second sub-dielectric layer in the first region is covered by the second patterned mask; and removing the first patterned mask and a portion of the second sub-dielectric layer from the second region, wherein the first sub-dielectric layer and the second sub- dielectric layer in the first region form the first dielectric layer.
Claims 33-35 are allowable for their dependence on allowable base claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
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/MOATAZ KHALIFA/Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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