DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 35 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/13/2026 has been entered
Remarks
The 03/13/2026 amendments of claims 14, 19 and 21 have been noted and entered.
Response to Arguments
Applicant’s arguments, see Arguments pages 1-3, filed 03/13/2026, with respect to the rejection(s) of claim(s) 14-16, 19, 21-27, 29-35 and 37-38 under 35 U.S.C. 103 have been fully considered and are persuasive in light of the newly added amendments. However, upon further consideration, a new ground(s) of rejection is made in view of Chen et al, US 20190067282 A1 (Chen ‘282) and Chuang et al, US 20160005756 A1 (Chuang).
New Grounds of Rejection
New grounds of rejection, prior art references Chen et al, US 20190067282 A1 (Chen ‘282) and Chuang et al, US 20160005756 A1 (Chuang) appear below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14, 16, 19, 21-27, 29-31 and 37-38 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20190067282 A1 (Chen ‘282) in view of Lin et al, US 20210335782 A1 (Lin ‘782).
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Regarding claim 14; Chen ‘282 teaches a method for forming a semiconductor structure comprising:
receiving a substrate (Chen ‘282: Annotated Fig (5) shared in this OA: 106) having a first region (104) and a second region (102);
forming a first dielectric layer (110) in the first region (104) and a second dielectric layer (108) in the second region (102), wherein a thickness of the second dielectric layer (108) is less than a thickness of the first dielectric layer (110), and
the second dielectric layer (108) is in contact with a sidewall of the first dielectric layer (110) and exposes a top surface of the first dielectric layer (108, by examining Annotated Fig (5) we can see that the second dielectric layer 108 and the first dielectric layer 110 are in contact but that layer 110 does not cover layer 108 which is what the instant application refers to as “exposes a top surface of the first dielectric layer”);
forming a first sacrificial gate (Fig (12): 1202) structure in the first region (104) and a second sacrificial gate structure (1102) in the second region (102) wherein a width of the first sacrificial gate (1202) structure is greater than a width of the second sacrificial gate structure (1102);
forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial structure; and
removing the first sacrificial gate structure to form a first gate trench,
and removing the second sacrificial gate structure to form a second gate trench in the second region; and a plurality of pillars in the first gate trench in the first region, and
forming a first metal gate structure (Annotated Fig (1) shared in this OA: 22) in the first gate trench (First Gate Trench) and a second metal gate structure (118) in the second gate trench (Second Gate Trench),
wherein the first metal gate structure (22) surrounds the pillars (Pillars, the gate structure (22) will surround the pillars (Pillars) due to how they repeat in the structure of the device), and
the pillars (Pillars) are disposed within a boundary (Boundary of Metal Gate Structure) of the first metal gate structure (22).
PNG
media_image1.png
921
1053
media_image1.png
Greyscale
PNG
media_image2.png
455
665
media_image2.png
Greyscale
PNG
media_image3.png
1007
922
media_image3.png
Greyscale
Chen ‘282 does not teach forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial structure; and removing the first sacrificial gate structure to form a first gate trench, and removing the second sacrificial gate structure to form a second gate trench in the second region; and a plurality of pillars in the first gate trench in the first region.
However, Lin ‘782 teaches forming a dielectric structure (Lin ‘782: Annotated Fig (3K): 40a) over the substrate (10) and surrounding the first sacrificial gate (SK2) structure and the second sacrificial structure (SK1); and removing the first sacrificial gate (SK2) structure to form a first gate trench (T2), and removing the second sacrificial gate structure (SK1) to form a second gate trench (Fig (3J): T1) in the second region (R1); and a plurality of pillars (40a) in the first gate trench (T2) in the first region (R2)
Chen ‘282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by removing the sacrificial gate structures and constructing the gates as disclosed in Lin ‘782 to enable the control of current through the transistors leading to a more reliable device.
PNG
media_image4.png
872
1410
media_image4.png
Greyscale
PNG
media_image5.png
552
701
media_image5.png
Greyscale
Regarding claim 16; Chen ‘282 in view of Lin ‘782 teaches all the limitations of the method of claim 14.
Further, Chen ‘282 teaches further, comprising forming a first source/drain (Chen ‘282: Annotated Fig (2) shared in this OA: 129, while Fig (2) does not explicitly show a combination of the source/drain structures and the sacrificial gates which are shown in Fig (12) it is understood that the source/drain structures exist within the substrate 106 such as explained in paragraph [0031]: “Though not shown in the process figures, source/drain regions can be formed within the substrate 106 alongside the first sacrificial gate stack 1102. Examples of the source/drain regions can be referred to the source/drain regions of FIG. 1 and FIG. 2.” ) in the first region (104) at opposite sides of the first sacrificial gate structure (1202), wherein all the pillars (Pillars) are offset from the first source/drain (129, Offset).
Regarding claim 19; Chen ‘282 in view of Lin ‘782 teach all the limitations of the method of claim 14.
Further, Chen ‘282 teaches the pillars (Chen ‘282: Annotated Fig (1) shared in this OA: Pillars) are formed within a boundary of the first metal gate structure (22, Boundary of Metal Gate Structure).
Regarding claim 37; Chen ‘282 in view of Lin ‘782 teach all the limitations of the method of claim 14.
Further, Chen ‘282 teaches wherein the pillars (Chen ‘282: Annotated Fig (1) shared in this OA: Pillars) are periodically or randomly arranged.
Regarding claim 21; Chen ‘282 teaches a method for forming a semiconductor structure comprising:
forming a first dielectric layer (Chen ‘282: Annotated Fig (5) shared in this OA: 110) and a second dielectric layer (108) over a substrate (106);
forming a first sacrificial gate structure (Annotated Fig (12) shared in this OA: 1202) and a plurality of openings (Openings) in the first sacrificial gate structure (1202), and a second sacrificial gate structure (1102);
wherein the plurality of openings (openings, openings between the gate structures) are formed within a boundary of the first sacrificial gate structure (Boundary of Gate Structure), and
portions of a top surface of the first dielectric layer (110a) are exposed through bottoms of the plurality of openings (Openings);
forming a protecting layer (1204) over the second sacrificial gate structure (1102), wherein sidewalls of the second dielectric layer (108a) are in contact with the protective layer (1204);
removing portions of the first dielectric layer exposed through the protecting layer;
forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial gate structure,
wherein the plurality of openings are filled with the dielectric structure;
removing a portion of the dielectric structure to expose top surfaces of the first sacrificial gate structure and the second sacrificial gate structure,
wherein portions of the dielectric structure remaining in the plurality of openings form a plurality of dielectric pillars surrounded by the first sacrificial gate structure;
removing the first sacrificial gate structure to form a first gate trench, and
removing the second sacrificial gate structure to form a second gate trench; and
forming a first metal gate structure (Annotated Fig (1) shared in this OA: 22) in the first gate trench (First Gate Trench) and a second metal gate structure (118) in the second gate trench (Second Gate Trench),
wherein the first metal gate structure (22) surrounds the dielectric pillars (Pillars).
Chen ‘282 does not teach removing portions of the first dielectric layer exposed through the protecting layer; forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial gate structure, wherein the plurality of openings are filled with the dielectric structure; removing a portion of the dielectric structure to expose top surfaces of the first sacrificial gate structure and the second sacrificial gate structure, wherein portions of the dielectric structure remaining in the plurality of openings form a plurality of dielectric pillars surrounded by the first sacrificial gate structure; removing the first sacrificial gate structure to form a first gate trench, and removing the second sacrificial gate structure to form a second gate trench.
However, Lin ‘782 teaches removing portions of the first dielectric layer (Lin ‘782: Annotated Figs (3C) and (3D) shared in this OA) exposed through the protecting layer (P1); forming a dielectric structure (40a) over the substrate (10) and surrounding the first sacrificial gate structure (SK2) and the second sacrificial gate structure (SK1), wherein the plurality of openings are filled with the dielectric structure (40a); removing a portion of the dielectric structure (40a, [0047]: discusses the use of processes such CMP to remove the top portion of the dielectric layer 40 to form 40a) to expose top surfaces of the first sacrificial gate structure (SK2) and the second sacrificial gate structure (SK1), wherein portions of the dielectric structure remaining in the plurality of openings form a plurality of dielectric pillars (40a) surrounded by the first sacrificial gate structure (SK2); removing the first sacrificial gate structure (SK2) to form a first gate trench (T2), and removing the second sacrificial gate structure (SK1) to form a second gate trench (T1).
Chen ‘282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by removing the sacrificial gate structures as disclosed in Lin ‘782 to create space for constructing the final/functional gate structures as disclosed in Lin ‘782 to lead to a better performing device.
PNG
media_image6.png
720
813
media_image6.png
Greyscale
Regarding claim 22; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Further, Chen ‘282 teaches wherein a thickness of the second dielectric layer (Chen ‘282: Annotated Fig (5) shared in this OA: 108) is less than a thickness of the first dielectric layer (110).
Regarding claim 23; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Chen ‘282 does not teach the removing of the portions of the first dielectric layer exposed through the protecting layer further deepens the openings.
Lin ‘782 teaches the removing of the portions of the first dielectric layer (Lin ‘782: : Annotated Fig (3D) shared in this OA: GOX2) exposed through the protecting layer (PR2) further deepens the openings (Opening).
Chen ‘282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by further deepening the opening as disclosed in Lin ‘782 to create space for the final gate structure and its surrounding insulation layers to be constructed leading ot a better performing device.
Regarding claim 24; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Further, Chen ‘282 teaches wherein a width of the first sacrificial gate (Chen ‘282: Annotated Fig (12) shared in this OA: 1202) structure is greater than a width of the second sacrificial gate structure (1102).
Regarding claim 25; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Chen ‘282 does not teach further comprising: forming a first spacer over sidewalls of the first sacrificial gate structure and a second spacer over sidewalls of the second sacrificial gate structure, wherein a bottom of the first spacer is in contact with the first dielectric layer.
Further, Lin ‘782 teaches further comprising: forming a first spacer (Lin ‘782: Annotated Fig (3K): S2) over sidewalls of the first sacrificial gate structure (SK2) and a second spacer (S1) over sidewalls of the second sacrificial gate structure (SK1), wherein a bottom of the first spacer (S2) is in contact with the first dielectric layer (GOX2).
Regarding claim 26; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
While Chen ‘282 teaches the use of high-k dielectric layer in constructing the gates, it fails to teach the use of such a dielectric in the sacrificial gate structure. Thus, Chen ‘282 fails to teach wherein the forming of the first sacrificial gate structure, the second sacrificial gate structure and the plurality of openings further comprises: forming a high-k dielectric layer over the first dielectric layer and the second dielectric layer; forming a sacrificial layer over the high-k dielectric layer; and removing portions of the sacrificial layer and portions of the high-k dielectric layer to form the first sacrificial gate structure, the second sacrificial gate structure, and the plurality of openings in the first sacrificial gate structure, wherein portions of the first dielectric layer are exposed through the first sacrificial gate structure and bottoms of the plurality of openings, and portions of the second dielectric layer are exposed through the second sacrificial gate structure.
However, Lin ‘782 teaches wherein the forming of the first sacrificial gate structure (Lin ‘782: Annotated Fig (3K) shared in this OA: SK2), the second sacrificial gate structure (SK1) and the plurality of openings further comprises: forming a high-k dielectric layer (Annotated Fig (3C) shared in this OA: HK) over the first dielectric layer (GOX) and the second dielectric layer (IL); forming a sacrificial layer over the high-k dielectric layer (PR1); and removing portions of the sacrificial layer (PR1) and portions of the high-k dielectric layer (HK) to form the first sacrificial gate structure (Annotated Fig (3K) shared in this OA: SK2), the second sacrificial gate structure (SK1), and the plurality of openings in the first sacrificial gate structure (SK2), wherein portions of the first dielectric layer (Annotated Fig (3C) shared in this OA: OGX) are exposed through the first sacrificial gate structure (Annotated Fig (3K) shared in this OA: SK2) and bottoms of the plurality of openings, and portions of the second dielectric layer (Annotated Fig (3C) shared in this OA: IL) are exposed through the second sacrificial gate structure (Annotated Fig (3K) shared in this OA: SK1).
Chen’282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by using the high-k dielectric layer as disclosed in Lin ‘782 to improve the insulation of the gate electrode leading to a better performing and more reliable device.
Regarding claim 27; Chen ‘282 in view of Lin ‘teaches all the claimed limitations of the method of claim 26.
Further, Chen ‘282 teaches removing the portions of the second dielectric layer (Chen ‘282: Fig (13): 108a) exposed through the second sacrificial gate structure (1102).
Regarding claim 29; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Chen ‘282 does not teach wherein the forming of the first metal gate structure and second metal gate structure further comprising: forming a work function metal layer in the first gate trench and the second gate trench; forming a gap-filling metal layer to fill the first gate trench and the second gate trench; and removing superfluous work function metal layer and gap-filling metal layer to form the first metal gate structure and the second metal gate structure, wherein a width of the gap-filling metal layer of the first metal gate structure is greater than a width of the gap-filling metal layer of the second metal gate structure.
However, Lin ‘782 teaches wherein the forming of the first metal gate (Lin ‘782: Fig (3K): MG2) structure and second metal gate structure (MG1) further comprising: forming a work function metal layer ([0050]-[0051] indicate that the gate metal structure can contain a work function metal layer) in the first gate trench (Fig (3J): T2) and the second gate trench (T1); forming a gap-filling metal layer (Fig (3K): MG1, MG2) to fill the first gate trench (Fig (3J): T2) and the second gate trench (T1); and removing superfluous work function metal layer and gap-filling metal layer to form the first metal gate structure (Fig (3K): MG2) and the second metal gate structure (MG1), wherein a width of the gap-filling metal layer of the first metal gate structure (MG2) is greater than a width of the gap-filling metal layer of the second metal gate (MG1) structure.
Chen ‘282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by using the work function metals to construct the metal gates to improve the conductivity of the gates and thus lead to a better performing device.
Regarding claim 30; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 29.
Chen ‘282 does not teach wherein the work function metal layer of the first metal gate structure is separated from the substrate by the high-k dielectric layer and the first dielectric layer.
Further, Lin ‘782 teaches wherein the work function metal layer (Lin ‘782: Fig (3K): MG2), [0050]-[0051] indicate that the gate metal structure can contain a work function metal layer) of the first metal gate structure (MG2) is separated from the substrate by the high-k dielectric layer (HK) and the first dielectric layer (GOX).
Chen ‘282 and Lin ‘782 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 by using the dielectric layers between the substrate and the work function metals as disclosed in Lin ‘782 to improve the insulation of the gate electrode leading to a better performing and more reliable device.
Regarding claim 31; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Further, Chen ‘282 teaches wherein a sidewall of at least one of the plurality of dielectric pillars (Chen ‘282: Annotated Fig (1) shared in this OA: Pillars) is in contact with the first dielectric layer (110a).
Regarding claim 38; Chen ‘282 in view of Lin ‘782 teaches all the claimed limitations of the method of claim 21.
Further, Chen ‘282 teaches wherein the openings (Chen ‘282: Annotated Fig (12) shared in this OA: Openings) are periodically or randomly arranged.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al, US 20190067282 A1 (Chen ‘282) in view of Lin et al, US 20210335782 A1 (Lin ‘782) in further view of Chen et al, US 20210265344 A1 (Chen ‘344).
Regarding claim 15; Chen ‘282 in view of Lin ‘782 teaches all the limitations of claim 14.
Further, Chen ‘282 teaches wherein the forming of the first dielectric layer (Chen ‘282: Fig (5) shared in this OA: 110) and the second dielectric layer (108) further comprises forming the first dielectric layer (110) in the first region (104); forming a first mask layer (Fig (4): 402) in the second region (102), removing the first mask layer (402); forming a second mask layer (604) in the first region (104); and forming the second dielectric layer (108) in the second region (102), wherein a tilted step is formed at a boundary between the first dielectric layer and the second dielectric layer.
However, Chen ‘282 in view of Lin ‘782 does not teach wherein a tilted step is formed at a boundary between the first dielectric layer and the second dielectric layer.
Chen ‘344 teaches a tilted step (Chen ‘344: Fig (3): 204s) formed at a boundary between the first dielectric layer (202) and the second dielectric layer (Fig (4): 120).
Chen ‘282 in view of Lin ‘782 and Chen ‘344 are considered analogous art. Thus, it would have been obvious, prior to the effective filing date of the instant application, to a person having ordinary skill in the art, to modify Chen ‘282 in view of Lin ‘782 by etching the supporting material layers with a slanted sidewall as disclosed in Chen ‘344 to facilitate better etching of layers without residue being left behind.
PNG
media_image7.png
891
656
media_image7.png
Greyscale
Allowable Subject Matter
Claims 32-35 are allowable. The following is a statement of reasons for the indication of allowable subject matter which are highlighted in what follows:
Regarding claim 32; Lin ‘782 teaches a method for forming a semiconductor structure comprising: receiving a substrate having a first region defined by a first isolation structure and a second region defined by second isolation structure; forming a first dielectric layer over the substrate in the first region; forming a second dielectric layer over the substrate in the second region; forming a first sacrificial gate structure and a plurality of openings in the first sacrificial gate structure in the first region, a second sacrificial gate structure in the second region; forming a dielectric structure over the substrate and surrounding the first sacrificial gate structure and the second sacrificial gate structure, and a plurality of dielectric pillars filling the plurality of openings; and replacing the first sacrificial gate structure with a first metal gate structure and replacing the second sacrificial gate structure with a second metal gate structure, wherein the first metal gate structure surrounds the dielectric pillars.
However, Lin ‘782 alone or in combination with other available art does not teach: wherein the forming of the first dielectric layer further comprises: forming a first patterned mask in the second region; performing a first operation to form a first sub-dielectric layer in the first region; performing a second operation to form a second sub-dielectric layer in the first region and the second region; forming a second patterned mask in the first region, wherein the second sub-dielectric layer in the first region is covered by the second patterned mask; and removing the first patterned mask and a portion of the second sub-dielectric layer from the second region, wherein the first sub-dielectric layer and the second sub- dielectric layer in the first region form the first dielectric layer.
Claims 33-35 are allowable for their dependence on allowable base claims.
Conclusion
Prior art made of record but not relied upon is considered pertinent to applicant’s disclosure:
Mishra et al, US 20200119179 A1 (Mishra); discloses a first dielectric layer in contact with a second dielectric layer where the second dielectric layer exposes the first dielectric layer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Moataz Khalifa whose telephone number is (703)756-1770. The examiner can normally be reached Monday - Friday (8:30 am - 5:00).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/M.K./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights