Attorney’s Docket Number: TSMCP1418US
Filing Date: 03/17/2022
Inventors: Chen et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed on 11/06/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgements
The Amendment filed on 11/06/2025, responding to the Office action mailed 7/09/2025, has been entered. Applicant amended claims 16, 24-25, and 27-33, and cancelled claims 26 and 34, and added claims 36-37. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome the respective claim rejections under 35 U.S.C. 102 and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 7/09/2025. Accordingly, all previous claim rejections are hereby withdrawn. Accordingly, pending in this application are claims 16-25, 27-33, and 35-37. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-23, 33, 35, and 37 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng (US 20200066922 A1) in view of Lin (US 11756990 B2).
Regarding claim 16, Cheng (see, e.g., fig. 4) shows most aspects of the invention including a method for forming a capacitor, the method comprising:
Forming a plurality of electrodes (e.g., capacitor electrodes 106) and a plurality of capacitor dielectric layers (e.g., capacitor dielectric layers 108) over a semiconductor substrate (e.g., semiconductor substrate 104), wherein the plurality of electrodes (e.g., capacitor electrodes 106) comprises a first electrode (e.g., top electrode of electrode 106 stack, see figure below) overlying a second electrode (e.g., electrode 106 underneath top electrode, see figure below), and
Forming a first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) over the plurality of electrodes (e.g., capacitor electrodes 106), wherein the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) continuously extends from above the plurality of electrodes (e.g., capacitor electrodes 106) to contact an upper surface of the second electrode (e.g., contact point between plurality of vias 116 and second electrode, see annotated fig. 1 below).
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Annotated Fig. 1
Cheng (see, e.g., fig. 4), however, fails to show wherein the first contact structure comprises a first upper lateral surface over an upper surface of the first electrode, a second upper lateral surface below the upper surface of the first electrode, and a sidewall extending from the first upper lateral surface to the second upper lateral surface.
Lin (see, e.g., see, e.g., fig. 10), in a similar device to Cheng, teaches a first contact structure (e.g., contact 120a) comprises a first upper lateral surface (e.g., upper surface of contact 120a) over an upper surface of a first electrode (e.g., electrode 110a), a second upper lateral surface (e.g., bottom surface of contact 120) below the upper surface of the first electrode (e.g., electrode 110a, see annotated fig. 2), and a sidewall (e.g., side surface wall of contact 120a) extending from the first upper lateral surface (e.g., upper surface of contact 120a) to the second upper lateral surface (e.g., bottom surface of contact 120).
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Annotated Fig. 2
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact of Lin within the first contact structure of Cheng, in order to provide additional conductive support between the electrode configuration and via setup, improving the electrical connectivity within the device.
Regarding claim 17, Cheng (see, e.g., fig. 4) shows the forming (see, e.g., transition of figure 3 to figure 4) of the first sidewall spacer (e.g., spacer liner 412 + paragraph 31 “The spacer liners 412…may be or comprise…silicon oxide, some other dielectric material…”) along opposing sidewalls of the first electrode (e.g., top electrode of electrode 106 stack), wherein forming the first sidewall spacer (e.g., spacer liner 412) comprises depositing a spacer layer (see, e.g., transition of figure 3 to figure 4) over the semiconductor substrate (e.g., semiconductor substrate 104) and performing a patterning process on the spacer layer (see, e.g., paragraph 52 “In some embodiments, the spacer liner layer…are formed by conformal deposition and/or formed by CVD, PVD, ALD, some other deposition process, or any combination of the foregoing”), wherein the patterning process defines the upper surface of the second electrode (see, e.g., paragraph 47 “The patterning forms a plurality of trench electrodes 106t…” + paragraph 77 “…performing an etch into a substrate to form a trench; forming a lower capacitor electrode…forming an electrode layer overlying the dielectric layer…patterning the electrode layer…”).
Regarding claim 18, Cheng (see, e.g., fig. 4) shows forming a second sidewall spacer (e.g., etch stop layer 408 + paragraph 30 “…the etch stop layer 408 may, for example, be or comprise silicon nitride, silicon oxynitride, silicon oxide, some other dielectric material…”) along opposing sidewalls of the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) and opposing sidewalls (e.g., spacer liner 412 + paragraph 31 “The spacer liners 412…may be or comprise…silicon oxide, some other dielectric material…”) of the second electrode (e.g., electrode 106 underneath top electrode, see figure below, see figure above), wherein forming the second sidewall spacer comprises depositing a spacer layer (see, e.g., transition of figure 3 to figure 4) over the semiconductor substrate (e.g., semiconductor substrate 104) and performing a patterning process on the spacer layer (see, e.g., paragraph 55 “The etch stop layer 408 may be formed by conformal deposition and/or formed by CVD, PVD, ALD, some other deposition process, or any combination of the foregoing”), wherein the patterning process etches a third electrode (e.g., electrode 106 underneath aforementioned second electrode) under the second electrode (e.g., electrode 106 underneath top electrode) and defines an upper surface of the third electrode (see, e.g., paragraph 47 “The patterning forms a plurality of trench electrodes 106t…”).
Regarding claim 19, Cheng (see, e.g., fig. 4) shows the forming of a second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114) over the plurality of electrodes (e.g., capacitor electrodes 106), wherein the second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114) directly contacts the upper surface of the third electrode (e.g., contact point between plurality of vias 116 and third electrode, see annotated fig. 3 below).
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Annotated Fig. 3
Regarding claim 20, Cheng (see, e.g., fig. 4) shows forming a plurality of conductive vias (see, e.g., plurality of vias 116 referenced in annotated fig. 4 below) over the plurality of electrodes (e.g., capacitor electrodes 106), wherein a first subset (see “first subset” of conductive vias in annotated fig. 4 below) of the conductive vias directly contact the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) and a second subset (see “second subset” of conductive vias in figure below) of the conductive vias (see, e.g., plurality of vias 116 referenced in annotated fig. 4 below) directly contact the first electrode (see, e.g., contact point between second subset of conductive vias and top electrode 106 of electrode stack).
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Annotated Fig. 4
Regarding claim 21, Cheng (see, e.g., fig. 4) shows the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) is elongated in a first direction (e.g., horizontally through plurality of wires 114) and the second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114) is elongated in a second direction (e.g., vertically through conductive vias 116) substantially orthogonal to the first direction.
Regarding claim 22, Cheng (see, e.g., fig. 4) shows the height of the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114 contacting the second electrode) is less than a height of the second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114 contacting the third electrode)
Regarding claim 23, Cheng (see, e.g., fig. 4) teaches the forming of a dielectric capping layer (e.g., ILD layer 404) over the plurality of electrodes (e.g., capacitor electrodes 106), wherein the dielectric capping layer (e.g., ILD layer 404) vertically separates the first electrode (e.g., top electrode of electrode stack 106) from the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114)
Regarding claim 33, Cheng (see, e.g., fig. 4) shows most aspects of the instant invention including a method for forming an integrated circuit (IC) comprising:
Forming a plurality of electrodes (e.g., capacitor electrodes 106) and a plurality of capacitor dielectric layers (e.g., capacitor dielectric layers 108) over a substrate (e.g., semiconductor substrate 104), wherein the plurality of electrodes (e.g., capacitor electrodes 106) are interleaved (see interleaved stack of capacitor electrodes 106 + capacitor dielectric layers 106 in fig. 4) with the plurality of dielectric layers (e.g., capacitor dielectric layers 108), wherein the plurality of electrodes (e.g., capacitor electrodes 106) comprise a first electrode (e.g., top electrode of electrode 106 stack), a second electrode (e.g., electrode 106 underneath top/first electrode), and a third electrode (e.g., electrode 106 underneath second electrode, see annotated fig. 5 below), wherein the second electrode (e.g., electrode 106 underneath top/first electrode) is between (see, e.g., figure below) the first (e.g., top electrode of electrode 106 stack) and the third electrode (e.g., electrode 106 underneath second electrode)
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Annotated Fig. 5
Forming a first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) over the first electrode (e.g., top electrode of electrode 106 stack) and comprising a first lateral segment (e.g., portion of conductive via 116 extending out from the plurality of wires 114) contacting the second electrode (e.g., electrode 106 underneath top/first electrode)
Forming a second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114) over the first electrode (e.g., top electrode of electrode 106 stack) and comprising a second lateral segment (e.g., conductive via 116 portion contacting the third electrode) contacting the third electrode (e.g., electrode 106 underneath second electrode)
Cheng (see, e.g., fig. 4), however, fails to show wherein an upper surface of the second lateral segment is vertically below an upper surface of the first lateral segment.
Lin (see, e.g., see, e.g., fig. 10), in a similar device to Cheng, teaches a first contact structure (e.g., contact 120a) comprises a first upper lateral surface (e.g., upper surface of contact 120a) over an electrode (e.g., electrode 110a).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the contact of Lin within the second contact structure of Cheng, in order to provide additional conductive support between the electrode configuration and via setup, improving the electrical connectivity within the device. Note that if the second contact structure of Cheng comprises the contact of Lin, the upper surface of the contact would be configured over the third electrode, whereas the upper surface of the first lateral segment is disposed above the entire capacitor stack (see annotated fig. below).
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Annotated Fig. 6
Regarding claim 35, Cheng (see, e.g., fig. 4) shows forming a first spacer structure (e.g., IMD layer 406f around first contact structure + paragraph 59 “The first IMD layer 406f may, for example, be a different material than the ILD layer 404 and/or may be or comprise, for example, silicon dioxide, silicon nitride…”) around an outer perimeter of the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114), and forming a second spacer structure (e.g., IMD layer 406f around second contact structure) around an outer perimeter of the second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114).
Regarding claim 37, Cheng (see, e.g., fig. 4) shows depositing a dielectric layer (e.g., ILD 404 + IMD 406) over the plurality of electrodes (e.g., capacitor electrodes 106) and the plurality of capacitor dielectric layers (e.g., capacitor dielectric layers 108), and forming a plurality of conductive vias (see, e.g., annotated fig. 7 below) in the dielectric layer (e.g., ILD 404 + IMD 406), the plurality of conductive vias (see, e.g., annotated fig. 7 below) comprising a first conductive via (see, e.g., annotated fig. 7 below) contacting the first contact structure (e.g., left-side plurality of vias 116 + plurality of wires 114) and a second conductive via (see, e.g., annotated fig. 7 below) contacting the second contact structure (e.g., right-side plurality of vias 116 + plurality of wires 114), wherein an upper surface of the first conductive via (see, e.g., annotated fig. 7 below) is aligned with an upper surface of the second conductive via (see, e.g., annotated fig. 7 below).
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Annotated Fig. 7
Allowable Subject Matter
Claim 24 is allowed.
Claims 25, 27-32, and 36 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 24, Cheng (US 20200066922 A1) in view of Chang (US 20200176552 A1) teaches most aspects of the method for forming an integrated circuit.
However, Cheng in view of Chang fails to disclose or suggest performing a second etch on a third electrode in the plurality of electrodes to form outer sidewalls of the third electrode, wherein the first contact structure is formed before performing the second etch.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814