Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 9, 2026 has been entered.
Response to Amendment
Applicant’s Amendment filed February 9, 2026 has been fully considered and entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 4, 6, 8-13 and 21-25 are rejected under 35 U.S.C. 103(a) as being unpatentable over Stephens et al. (US 2014/0363120 A1) in view of Uhland et al. (US 2007/0254411 A1), further in view of Ishikawa et al. (US 2021/0373232 A1).
Regarding claims 1, 6, 11-13, 21, 22 and 25, Stephens discloses a semiconductor package (10 in Fig. 1) comprising:
a first die group (12-15), comprising a first die (15) and a second die (14) stacked together, wherein each of the first die and the second die includes an integrated circuit (39 in Fig. 2; paragraph 0022) formed on a semiconductor substrate (32), each die being characterized by:
a first surface that is a top surface of the integrated circuit;
a second surface that is a bottom surface of the semiconductor substrate, the first surface being opposite to the second surface;
a side surface at an edge and substantially perpendicular to the first surface and the second surface; and
a conductive region disposed at the side surface (paragraph 0021 discloses dies 12-15 including edge connectors and/or contacts used to provide electric connections within each die to the backplane die 11) and in a dielectric region (paragraph 0023 discloses each integrated circuit comprising dielectric layers) of the integrated circuit,
wherein the conductive region of the first die is electrically coupled to an interconnect structure disposed in the integrated circuit of the first die (paragraph 0021 discloses each die may be formed with through-silicon vias to provide vertical signal conductors for the die stack), and the conductive region of the second die is electrically coupled to an interconnect structure disposed in the integrated circuit of the second die;
wherein the first surface of the first die is bonded to the second surface of the second die (paragraph 0021 discloses the dies 12-15 may be implemented as a die stack rather than separated dies);
a base substrate structure (11) having a top surface that includes conductive regions including first and second conductive regions disposed in a dielectric region, the conductive regions coupled to an interconnect structure in the base substrate structure (paragraph 0021 discloses backplane 11 including dielectric layers formed to cover interconnect features, and dies 12-15 including edge connectors and/or contacts used to provide electric connections to the backplane die 11);
wherein the first die group is bonded sideways on the base substrate structure, with the side surfaces of the first and second dies bonded to the top surface of the base substrate structure, the first and second conductive regions bonded to the respective conductive regions of the base substrate structure (paragraph 0021 discloses electrically conductive devices such as solder balls used to connect the dies 12-15 with the backplane 11); and the first/top surfaces of the stacked dies being substantially perpendicular to the top surface of the base substrate structure (see Fig. 1);
whereby the first die is configured to provide: an electrical coupling to the second die through first surface (paragraph 0021 discloses each die may be formed with through-silicon vias to provide vertical signal conductors for the die stack); and an electrical coupling to the base substrate structure though the side surface.
Still regarding claims 1, 6, 11-13, 21, 22 and 25, Stephens further discloses an optical TSV structure (305 in Figs. 22-31) within the substrate (301). Stephens teaches the claimed invention except for a photonic die. Uhland discloses a semiconductor package (100 in Fig. 1; 1100 in Fig. 12), comprising a first die (1118) and a second die (1116) stacked and bonded together so as to provide electrical coupling from the first die to the second die, wherein the first die includes a photonic device (1118 must include a photonic device which couples with waveguide 1162) in the semiconductor substrate and comprising: an optical interface structure (end of 1162) for coupling to an optical fiber at a surface of the die (paragraph 0093 discloses waveguide 1162 coupling to external optical components; paragraph 0096 discloses positioning optical fibers that couple with 1118); and a waveguide section (1162) configured to facilitate transmission of an optical signal through the optical interface, wherein the waveguide section is exposed (see Fig. 12). Since both inventions relate to semiconductor devices, one having ordinary skill in the art at the time of the invention would have found it obvious to use a photonic device as disclosed by Uhland in the package of Stephens for the purpose of providing optical connection to an external device.
Still regarding claims 1, 6, 11-13, 21, 22 and 25, the proposed combination of Stephens and Uhland teaches the claimed invention except for the optical interface coupling to the optical fiber at a surface substantially perpendicular to the side surface. Ishikawa discloses a semiconductor substrate (1208 in Fig. 23) having an optical interface structure comprising a waveguide section (1207) for coupling to an optical fiber (1202) at a surface substantially perpendicular to the side surface of the substrate. Since all of the inventions relate to semiconductor devices, one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to couple an optical fiber at a surface substantially perpendicular to the side surface as disclosed by Mendoza in the device of the proposed combination of Stephens and Uhland for the purpose of allowing for coupling from a wider range of locations and angles, increasing the versatility of the device and reducing the size. Further, in the proposed combination, one having ordinary skill would find it obvious to perform coupling at either the “top” or “bottom” surface depending on the orientation of the device and the location of the photonic components in the substrate.
Regarding claims 3, 10 and 24, Uhland in view of the rejection above, further discloses the photonic device comprises cladding layers (1198) surrounding the waveguide section (1106) in Fig. 16.
Regarding claim 4, Stephens discloses the first die group further comprising a third die (13) stacked to the second and first die in Fig. 1.
Regarding claim 8, Uhland in view of the rejection above, further discloses the photonic device comprises one or more of a laser device and an optical sensor in paragraph 0081.id crystal moleculesand specifically stating the exposure voltage greater than a
Regarding claims 9 and 23, the proposed combination of Stephens, Uhland and Ishikawa teaches the claimed invention except for specifically stating the waveguide section comprising nitride. However, Uhland discloses the waveguide comprising the same material as the encapsulating layer 1111 (paragraph 0093), and also that the encapsulating layer 1111 can include nanoparticles such as aluminum nitride (paragraph 0099). As such, one having ordinary skill in the art at the time of the invention would have found it obvious for the waveguide section to comprise nitride, for the purpose of adjusting the thermal conductivity. Further, it would have been obvious to one having ordinary skill in the art at the time of the invention to have the waveguide section comprise nitride, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 2, 5, 7, 26 and 27 are rejected under 35 U.S.C. 103(a) as being unpatentable over Stephens et al. (US 2014/0363120 A1) in view of Uhland et al. (US 2007/0254411 A1), further in view of Ishikawa et al. (US 2021/0373232 A1) and further in view of Mendoza (US 11,493,714 B1).
Still regarding claims 2, 5, 7, 26 and 27, the proposed combination of Stephens, Uhland and Ishikawa teaches the claimed invention except for the metal pads on both sides are bonded and dielectric material at both sides are bonded. Mendoza discloses hybrid bonding between wafers wherein dielectric material and metal at the surface of both wafers are bonded together at an elevated temperature in column 8, line 66 to column 9, line 7. Since all of the inventions relate to semiconductor devices and in particular Uhland discloses the side surface including a conductive material and a dielectric material (Fig. 6), one of ordinary skill in the art before the effective filing date of the claimed invention would have found it obvious to bond metal pads and dielectric material on both sides as disclosed by Mendoza in the device of the proposed combination of Stephens, Uhland and Ishikawa for the purpose of forming a more secure and robust bond.
Response to Arguments
Applicant's arguments, filed February 9, 2025, with respect to claims have been considered but are moot in view of the new grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRIS H CHU whose telephone number is (571)272-8655. The examiner can normally be reached on Mon-Fri 9AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached on 571-272-239797. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Any inquiry of a general or clerical nature should be directed to the Technology Center 2800 receptionist at telephone number (571) 272-1562.
Chris H. Chu
/CHRIS H CHU/Primary Examiner, Art Unit 2874 March 18, 2026