DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the amendment filed on 12/11/25. Claims 1-15 and 21-25 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The rejection of claim(s) 1-15 and 21-25 under 35 U.S.C. 102(a)(1) as being anticipated by Fung (US PGPub 2021/0098631, hereinafter referred to as “Fung”) has been maintained for reasons of record.
Fung discloses the semiconductor device method as claimed. See figures 1-24, with emphasis on figures 22A-22C, and corresponding text, where Fung teaches, in claim 1, forming a channel structure (25) over a substrate (10);
forming a dielectric layer (102) (the dielectric layer is more than one layer) over the channel structure (25), wherein the dielectric layer (102) has a higher dielectric constant than silicon nitride; (figures 22A and 22B; [0043])
forming a gate stack (104) (in response to the forming of the gate stack) over the dielectric layer (102); and
forming a spacer element (55) over a sidewall of the gate stack (104), wherein the spacer element (55) covers a portion of the dielectric layer (102) (figures 22A-22C; [0050-0053]).
Fung teaches, in claim 2, further comprising: partially removing portions of the channel structure beside the spacer element to form a recess; and forming an epitaxial structure in the recess.
In figure 10 the spacer material 53 is deposited over the entire
surface including the channel structure 30 ([0029]). Next, the as shown in figures 12A-12C, the channel structure is partially removed ([0033]). Lastly, as shown in figures 13A-13C shows an epitaxial liner 70 formed within the recess of the channel structures ([0037]).
Fung teaches, in claim 3, further comprising: forming an insulating layer (95) over the substrate (10), wherein the insulating layer covers (102B) the epitaxial structure and surrounds the gate stack (104);
removing the gate stack (104) to form a trench (portion above 104) surrounded by the insulating layer (95); and
forming a metal gate stack (106) (the formation of the cap layer completes the metal stack) in the trench. ([0047])
Fung teaches, in claim 4, further comprising removing a portion of the dielectric layer (102) exposed by the trench. (figure 18; [0046])
Fung teaches, claim 5, wherein the metal gate stack comprises a gate dielectric layer (102), and the gate dielectric layer extends along a sidewall and a bottom of the trench (figures 22A-22C; [0050-0053])
Fung teaches, claim 6, wherein the gate dielectric layer (102B) is formed to be in direct contact with the dielectric layer (102). ([0043])
Fung teaches, in claim 7, wherein the gate dielectric layer is formed to be in direct contact with the spacer element. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 8. The method for forming a semiconductor device structure as claimed in claim 1, further comprising: forming an oxide layer over the channel structure before the formation of the dielectric layer. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 9, further comprising: forming an oxide layer over the channel structure after the formation of the dielectric layer and before the formation of the gate stack. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 10, wherein the dielectric layer is formed to be in direct contact with the channel structure. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 11, a method for forming a semiconductor device structure, comprising: (figures 22A-22C; [0050-0053])
forming a semiconductor structure over a substrate; forming a metal-containing oxide layer ([0043]) over the semiconductor structure; forming a gate stack (104) over the metal-containing oxide layer; and forming a spacer element (90) over a sidewall of the gate stack, wherein the spacer element (55) covers a top of the metal-containing oxide layer.
Fung teaches, in claim 12, wherein the top of the metal-containing oxide layer is formed to be vertically between the substrate and a top of the spacer element. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 13, further comprising: surrounding the gate stack with an insulating layer; and replacing the gate stack with a metal gate stack. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 14, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the metal-containing oxide layer is formed to be in direct contact with the gate dielectric layer. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 15, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the gate dielectric layer extends upwards along a sidewall of the metal-containing oxide layer. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 21, a method for forming a semiconductor device structure, comprising: (figures 22A-22C; [0050-0053])
forming a semiconductor stack having a plurality of sacrificial layers (20, 25) and a plurality of semiconductor layers, wherein the sacrificial layers (20) and the semiconductor layers (25) have an alternating configuration; forming a dielectric layer over the semiconductor stack, wherein the dielectric layer (102) has a higher dielectric constant than silicon nitride; forming a gate stack (104) over the dielectric layer; and forming a spacer element (55) over a sidewall of the gate stack (54), wherein the spacer element partially covers the dielectric layer.
Fung teaches, in claim 22, further comprising: forming a second dielectric layer over the semiconductor stack after the formation of the dielectric layer and before the formation of the gate stack. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 23, wherein the second dielectric layer has a lower dielectric constant than the dielectric layer. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 24, further comprising: forming a second dielectric layer over the semiconductor stack before the formation of the dielectric layer. (figures 22A-22C; [0050-0053])
Fung teaches, in claim 25, wherein the second dielectric layer has a lower dielectric constant than the dielectric layer. (figures 22A-22C; [0050-0053])
Response to Arguments
Applicant's arguments filed 12/11/25 have been fully considered but they are not persuasive. In the remarks on pages 7-13:
Applicant raises the clear issue as to whether Fung suggests in claim 1, “forming a gate stack over the dielectric layer; and forming a spacer element over a sidewall of the gate stack.”; in claim 4, removing a portion of the dielectric layer 102 exposed by the trench; in claim 9, forming an oxide layer over the channel structure after formation of the dielectric layer and before the formation of the gate stack; in claim 11, forming a metal-containing oxide over the semiconductor structure; forming a gate stack over the metal containing oxide layer; and forming a spacer element over a sidewall of the gate stack, wherein the spacer element covers a top of the metal-containing oxide layer; in claim 13, replacing the gate stack with a metal stack; in claims 14 and 15, unable to identify the claims limitations; in claim 15, forming a dielectric layer over the semiconductor stack, wherein the dielectric layer has a higher dielectric constant than silicon nitride; forming a gate stack over the dielectric layer; and forming a spacer element over a sidewall of the gate stack, wherein the spacer elements partially covers the dielectric layer; In claims 22-25, unable to identify claims limitation.
The Examiner views that Fung does suggest the above limitation and/or statements. In addition, the examiner would like to provide a teaching of a universal fact regarding completed metal gates (see Zhang et al. US PGPub 2020/0176324, [0023], teaches the convention processes of forming a metal gate). (See MPEP 2124)
Specifically, in claim 1, Fung teaches forming a gate stack (104) over the gate dielectric layer (102) (dielectric layer), where the gate electrode layer is deposited into the opening and over the channel structures (25) and then recessed ([0046]). It is at this step based on the manufacturing steps of forming a metal gate, the planarized gate electrode layer is still in fact a gate stack and it is not a metal gate until the cap layer is formed over top of the recessed gate electrode. Furthermore, the spacers (55) are already present on the opposite sides of the opening prior to the formation of the recessed gate stack (104) thus are already formed over the sidewall of the gate stack (figures 18-21; [0043-0048]).
Regarding claim 4, Fung teaches depositing the gate dielectric layer and gate electrode layer to be planarized, thus a portion of the gate dielectric layer is removed ([0046]).
Regarding claim 9, the gate dielectric layer includes more than one layers of dielectric material ([0043-0044]).
Regarding claim 11, Fung teaches that the gate electrode layer is more than one layer including metal oxide layers ([0045-0046]). In addition, Fung teaches forming work-function adjustment layers that is interposed between the gate dielectric layer (102) and the gate electrode layer (104) ([0048]) formed over the channel structure (25); forming a gate stack (104) that is recessed over the metal containing oxide layer [0047]); and forming a spacer element (55) over a sidewall of the gate stack, wherein the spacer element (55) covers a top of the metal-containing oxide layer.
Regarding claim 13, Fung teaches replacing by recessing the gate stack (104) and replacing with a cap layer thereby completing the metal stack (106, 104, 102) ([0045-0047]).
Regarding claims 14 and 15, Fung teaches the gate stack (104) and then replacing the gate stack by recessing the gate stack and forming a cap layer thereby completing the metal stack. The examiner would like to draw to the attention to the applicant as stated in theses sections [0043-0048], and throughout the office action that an interfacial layer, the gate dielectric, the work-function layer, and the gate electrode layer all include more than one layer. In addition, these layers are listed out that include high-k dielectrics metal-oxide layers ([0045], [0048]).
Regarding claim 15, Fung clearly teaches this forming a dielectric layer over the semiconductor stack, wherein the dielectric layer has a higher dielectric constant than silicon nitride; forming a gate stack over the dielectric layer; and forming a spacer element over a sidewall of the gate stack, wherein the spacer elements partially covers the dielectric layer [0043-0048].
Regarding claims 22-25, Fung teaches wherein the second dielectric layer (102A) has a lower dielectric constant than the dielectric layer (102B). (figure 22A and 22B; [0051-0052]).
The examiner concludes that Fung meets the limitations and to suggest that the applicant further incorporate claim language to define the gate stack to be a “dummy gate stack” as it is described in the applicant’s disclosure ([0034]). In addition, the examiner believes that this change will help to define the specific gate stack the applicant is referring to.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 March 26, 2026
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898