DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/09/26 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-15 and 21-25 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ching et al. (US PGPub 2018/0151450, hereinafter referred to as “Ching”).
Ching discloses the semiconductor method as claimed. See figures 1-21 and corresponding text, where Ching teaches, in claim 1, a method for forming a semiconductor device structure, comprising:
forming a channel structure (310) over a substrate (210); (figure 8; [0044-0045])
forming a dielectric layer (620) over the channel structure (310), wherein the dielectric layer (620) has a higher dielectric constant than silicon nitride (figure 8; [0044-0045]);
forming a gate stack (710) over the dielectric layer (620) (figure 9; [0045-0046]); and
forming a spacer element (820) over a sidewall of the gate stack (710) after the gate stack (710) is formed, wherein the spacer element (820) covers a portion of the dielectric layer (620) (figures 11A and 11B; [0050-0057]).
Ching teaches, in claim 2, further comprising:
partially removing portions of the channel structure beside the spacer element to form a recess; and
forming an epitaxial structure (870, 875) in the recess (figure 14; [0058-0061]).
Ching teaches, in claim 3, further comprising:
forming an insulating layer (910) over the substrate (210), wherein the insulating layer (910) covers the epitaxial structure (870, 875) and surrounds the gate stack (710);
removing the gate stack to form a trench (920) surrounded by the insulating layer (910) (figure 15; [0062-0064]); and
forming a metal gate stack (1016) in the trench (920) (figures 16A-19C; [0065-0077]).
Ching teaches, in claim 4, further comprising removing a portion of the dielectric layer exposed by the trench (figures 16A-18A; [0065-0069]).
Ching teaches, in claim 5, wherein the metal gate stack comprises a gate dielectric layer, the gate dielectric layer extends along a sidewall and a bottom of the trench, and the gate dielectric layer extends across an interface between the dielectric layer and the spacer element (figures 19A-19C; [0073-0077]).
Ching teaches, in claim 6, wherein the gate dielectric layer is formed to be in direct contact with the dielectric layer (figures 19A-19C; [0073-0077]).
Ching teaches, in claim 7, wherein the gate dielectric layer is formed to be in direct contact with the spacer element (figures 19A-19C; [0073-0077]).
Ching teaches, in claim 8, further comprising:
forming an oxide layer over the channel structure before the formation of the dielectric layer (figures 16A-19C; [0065-0077]).
Ching teaches, in claim 9, further comprising:
forming an oxide layer over the channel structure after the formation of the dielectric layer and before the formation of the gate stack (figures 16A-19C; [0065-0077]).
Ching teaches, in claim 10, wherein the dielectric layer is formed to be in direct contact with the channel structure (figures 16A-19C; [0065-0077]).
Ching teaches, in claim 11, a method for forming a semiconductor device structure, comprising:
forming a semiconductor structure (310) over a substrate (210); (figure 8; [0044-0045])
forming a metal-containing oxide layer (620) over the semiconductor structure (310); (figure 8; [0044-0045])
forming a gate stack (710) over the metal-containing oxide layer (620), wherein the gate stack (710) is a dummy gate stack; (figure 9; [0045-0046]) and
forming a spacer element (820) over a sidewall of the gate stack (710), wherein the spacer element (820) covers a top of the metal-containing oxide layer (620) (figures 11A and 11B; [0050-0057]).
Ching teaches, in claim 12, wherein the top of the metal-containing oxide layer is formed to be vertically between the substrate and a top of the spacer element.
Ching teaches, in claim 13, further comprising:
surrounding the gate stack (710) with an insulating layer (910); and
replacing the gate stack with a metal gate stack (1016).
Ching teaches, in claim 14, wherein the metal gate stack comprises a gate dielectric layer (1014) and a work function layer, and the metal-containing oxide layer (620) is formed to be in direct contact with the gate dielectric layer. (figures 19A-19C; [0073-0077]).
Ching teaches, in claim 15, wherein the metal gate stack comprises a gate dielectric layer and a work function layer, and the gate dielectric layer extends upwards along a sidewall of the metal-containing oxide layer (figures 19A-19C; [0073-0077]).
Ching teaches, in claim 21, a method for forming a semiconductor device structure, comprising:
forming a semiconductor stack (310) having a plurality of sacrificial layers (314) and a plurality of semiconductor layers (316), wherein the sacrificial layers (314) and the semiconductor layers (316) have an alternating configuration (figure 3; [0027]);
forming a dielectric layer (620) over the semiconductor stack (310), wherein the dielectric layer (620) has a higher dielectric constant than silicon nitride; figure 8; [0044-0045])
forming a gate stack (710) over the dielectric layer (620), wherein the gate stack (710) is a dummy gate stack (figure 9; [0045-0046]);
forming a spacer element (820) over a sidewall of the gate stack (710), wherein the spacer element (820) partially covers the dielectric layer (620); and
removing the gate stack (710) (figures 11A and 11B; [0050-0057]).
Ching teaches, in claim 22, further comprising:
forming a second dielectric layer over the semiconductor stack after the formation of the dielectric layer and before the formation of the gate stack ([0044], more than one layer where one is a silicon oxide).
Ching teaches, in claim 23, wherein the second dielectric layer has a lower dielectric constant than the dielectric layer ([0044], more than one layer where one is a silicon oxide).
Ching teaches, in claim 24, further comprising:
forming a second dielectric layer over the semiconductor stack before the formation of the dielectric layer ([0044], more than one layer where one is a silicon oxide).
Ching teaches, in claim 25, wherein the second dielectric layer has a lower dielectric constant than the dielectric layer ([0044], more than one layer where one is a silicon oxide).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 June 25, 2026
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