Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I in the reply filed on 6/30/25 is acknowledged.
Claims 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6/30/25.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amano (US PGPub 2018/0331118).
Claim 1: Amano teaches (Fig. 6-12H) a memory device, comprising: a super-pillar (20/58) formed through a plurality of sub-decks; a string of memory cells formed along the super-pillar; and respective regions of transition material disposed between respective sub-decks of the plurality of sub-decks, wherein the super-pillar comprises at least a first pillar formed through a first sub-deck of the plurality of sub-decks substantially aligned with a second pillar formed through a second sub-deck of the plurality of sub-decks.
Claim 2: Amano teaches (Fig. 6-12H) the first sub-deck comprises a first layer stack with alternated layers of conductor material (146) and insulator material (132, 170), the second sub-deck comprises a second layer stack with alternated layers of conductor material (246) and insulator material (232), and wherein a first region of transition material (180) is disposed directly between a first outermost layer of insulator material (170) of the first layer stack and a second outermost layer of insulator material (232) of the second layer stack.
Claim 3: Amano teaches [0085, 0090] the first region of transition material, the first layer of insulator material, and the second layer of insulator material all comprise a same material.
Claim 4: Amano teaches [0095] the first region of transition material comprises a different material from one or more of the first layer of insulator material and the second layer of insulator material.
Claim 5: Amano teaches (Fig. 14) an array of super-pillars formed through the plurality of sub-decks; and respective strings of memory cells formed along respective super-pillars of the array of super-pillars.
Claim 6: Amano teaches [0002,0118, 0124] the memory cells comprise floating gate NAND memory cells.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Amano (US PGPub 2018/0331118).
Claim 7: Amano teaches (Fig. 6-12H) system, comprising: a processor; and a three-dimensional (3D) memory device coupled with the processor, wherein the 3D memory device includes: a super-pillar formed through a plurality of sub-decks; a 3D string of memory cells formed along the super-pillar; and respective regions of transition material disposed between respective sub-decks of the plurality of sub-decks, wherein the super-pillar comprises at least a first pillar formed through a first sub-deck of the plurality of sub-decks is substantially aligned with a second pillar formed through a second sub-deck of the plurality of sub-decks. Amano does not specifically teach the processor in conjunction with the memory device but one of ordinary skill in the art would know their standard use together. See PTO-892 for evidence in similar prior art.
Claim 8: Amano teaches (Fig. 6-12H) the first sub-deck comprises a first layer stack with alternated layers of conductor material and insulator material, the second sub-deck comprises a second layer stack with alternated layers of conductor material and insulator material, and wherein a first region of transition material is disposed directly between a first layer of insulator material of the first layer stack and a second layer of insulator material of the second layer stack.
Claim 9: Amano teaches [0085, 0090] the first region of transition material, the first layer of insulator material, and the second layer of insulator material all comprise a same material.
Claim 10: Amano teaches [0095] the first region of transition material comprises a different material from one or more of the first layer of insulator material and the second layer of insulator material.
Claim 11: Amano teaches (Fig. 14) the 3D memory device further comprises: an array of super-pillars formed through the plurality of sub-decks; and respective 3D strings of memory cells formed along respective super-pillars of the array of super-pillars.
Claim 12: Amano teaches [0002,0118, 0124] the memory cells comprise floating gate NAND memory cells.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SARAH KATE SALERNO whose telephone number is (571)270-1266. The examiner can normally be reached M-F 6:30am-2:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at 5712721705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SARAH K SALERNO/Primary Examiner, Art Unit 2814