Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/02/2025 has been entered.
Response to Amendment
Applicant's arguments Pages 6-7 of Applicant Arguments/Remarks, filed 11/02/2025, have been fully considered but they are not persuasive.
Applicant amends claims 1, 13, and 19, to include that there is at least on dummy metal pad that is located only at a periphery of the overlapping region, that is the region that is between the dummy die and the bottom die. Even with the new limitation, the cited references already on record can still be used to make anticipatory or as an obviousness combination rejection.
Applicant states that the purpose of the invention in the instant application is to solve the technical problem of chip delamination especially at the edges of the overlapping area. Meanwhile the cited reference by Chen which is used as an anticipatory rejection, uses the dummy metal pads in order to help with uniformity of the CPM process or are used to even out pattern density. However, while these things may be true, the recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP § 2114. Because the invention of Chen has the same structural features that are described in the claim, the invention of Chen is able to anticipated the invention in the instant application.
Furthermore, the new claim limitation for claims 1, 13, and 19, can still be found in Chen. Below is fig. 30 from Chen.
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Element 32-1 is the overlapping region where the dummy die (31-1) is bonded to the bottom (70) where there is first bonding layer (76) in the overlapping region (32-1). It would be reasonable to choose any of the outer ring of dummy metal pads (152D/27) within the overlapping region (32-1). It is reasonable that any one of the dummy metal pads (152D/27) in the outer ring of the dummy metal pads in the overlapping region (32-1) is located at the periphery of the overlapping region.
Applicant’s arguments, see Page 6 of Applicant Arguments/Remarks, filed 11/02/2025, with respect to 112 rejections have been fully considered and are persuasive. The 35 U.S.C. 112 rejection of claim 13 has been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1, 13, and 19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Currently, Examiner believes that the limitation requiring that at least one dummy metal pad is located only at a periphery of the overlapping region is not explicitly disclosed in the originally filed disclosure. Applicant points to at least figure 4 for the support. The problem, however, is that the drawings are not illustrative, that is, they do not need to show all possible embodiments. There is nothing stopping an embodiment where none of the dummy metal pads are only at the periphery. The negative limitation that at least one of the dummy metal pads are only at the periphery of the overlapping region needed to have been explicitly disclosed, however, the drawings can’t explicitly disclose this as the position of the dummy metal pads can be changed in the drawings in order to fit alternative embodiments. Furthermore, Examiner believes that the specification is silent to this negative limitation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 13, 19, 21-22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 20200161263 A1; Chen).
Regarding Claim 1 Chen discloses a semiconductor package comprising:
a bottom die (70) having a first bonding layer (76) formed at a top surface of the bottom die (Fig. 16, Where bond layer 76 is on first die 70);
a top die (60) on the bottom die (Fig. 17, wherein the top die is vertically stacked on the bottom die), wherein the top die comprises a second bonding layer (54) formed at a bottom surface of the top die (Para. 21, where bonding layer is formed at the bottom surface of the top die as seen in Fig. 8 and later seen on the bottom of top die in Fig. 17), and the top die is bonded to the bottom die by bonding the first bonding layer and the second bonding layer using hybrid bonding (Para. 32, “the bonding may include fusion bonding, which includes the direct metal bonding between bond pads 152A/152B and bond pads 52A/52B, and the dielectric-to-dielectric bonding between dielectric layer 54 and dielectric layer 76”, The instant application defines hybrid bonding as “stacks and bonds dies using both dielectric bonding layers and metal-to-metal interconnects”, this definition would match the definition of “fusion bonding” as quoted above.);
a dummy die (31-1) on the bottom die and lateral to the top die (Fig. 18, where the dummy die is lateral to the top die [60] and directly above bottom die [70]), wherein the dummy die comprises a third bonding layer (26) formed at a bottom surface of the dummy die (Fig. 18, where bonding layer is below dummy die), and the dummy die is bonded to the bottom die by bonding the first bonding layer and the third bonding layer (Para. 34, “dielectric layers 26 in dummy dies 32-1 bonded to dielectric layer 76”);
and at least one dummy metal pad (152D/27) formed within an overlapping region between the dummy die and the bottom die (Fig. 18, where dummy bond pad 152D is formed in the region between dummy die 32-1 and bottom die 70, and Fig. 29, where dummy metal pad 27 is formed in in the region between dummy die 32-1 and bottom die 70), in only one of the first bonding layer and the third bonding layer (Fig. 18, where dummy metal bond pad 152D are present in the first bonding layer 76 and no other dummy metal pads are present in the third bonding layer) and not electrically connected (Para. 47, “dummy pads 152D are electrically floating”), wherein the at least one dummy metal pad is located only at a periphery of the overlapping region (Fig. 30, where any one of the dummy metal pads (152D/27) in the outer ring of the dummy metal pads in the overlapping region (32-1) is located at the periphery of the overlapping region.
Regarding Claim 13, Chen discloses a semiconductor package comprising:
a first die (70) having a first bonding layer (76) formed at a top surface of the first die (Fig 16, Where bond layer 76 is on first die 70);
a second die (60) on the first die (Fig. 17, where the second die is vertically stacked on the first die), wherein the second die (60) comprises a second bonding layer (54) formed at a bottom surface of the second die (Para. 21, where bonding layer is formed at the bottom surface of the second die as seen in Fig. 8 and later seen on the bottom of second die in Fig. 17), and the second die is bonded to the first die by bonding the first bonding layer and the second bonding layer (Para. 32, “device die(s) 60 are bonded to device dies 70 … dielectric-to-dielectric bonding between dielectric layer 54 and dielectric layer 76”); and
at least one dummy metal pad (52B/152B) formed in one of the first bonding layer and the second bonding layer (Para. 21 “FIG. 8 illustrates the formation of dielectric layer 50, vias 51, dielectric layer 54, and bond pads 52A and 52B in dielectric layer 54), wherein the at least one dummy metal pad is not electrically connected (Para. 33, “In accordance with some embodiments of the present disclosure, since tier-2 die 60-1 is connected to tier-1 die 70, bond pad 52B does not have an electrical and signal function, and hence is dangling”), wherein the at least one dummy metal pad is located only at a periphery of the overlapping region (Fig. 30, where any one of the dummy metal pads (152D/27) in the outer ring of the dummy metal pads in the overlapping region (32-1) is located at the periphery of the overlapping region.
Regarding Claim 19, Chen discloses a method comprising:
forming a first bonding layer (76) at a top surface of a bottom die (70) (Fig. 16, Where bond layer 76 is on first die 70);
forming a second bonding layer (54) at a bottom surface of a top die (Para. 21, where bonding layer is formed at the bottom surface of the top die as seen in Fig. 8 and later seen on the bottom of top die in Fig. 17);
forming a third bonding layer (26) at a bottom surface of a dummy die (Fig. 18, where bonding layer is below dummy die);
forming at least one dummy metal pad (152B-D/27), within an overlapping region between the dummy die and the bottom die (Fig. 18, where dummy bond pad 152D is formed in the region between dummy die 32-1 and bottom die 70, and Fig. 29, where dummy metal pad 27 is formed in in the region between dummy die 32-1 and bottom die 70), in only in one of the first bonding layer and the third bonding layer (Fig. 18, where dummy metal bond pad 152D are present in the first bonding layer 76 and no other dummy metal pads are present in the third bonding layer), the at least one dummy metal pad being not electrically connected (Para. 47, “dummy pads 152C and 152D are electrically floating”);
bonding, using hybrid bonding, the top die on the bottom die by bonding the first bonding layer and the second bonding layer (Para. 32, “the bonding may include fusion bonding, which includes the direct metal bonding between bond pads 152A/152B and bond pads 52A/52B, and the dielectric-to-dielectric bonding between dielectric layer 54 and dielectric layer 76”, The instant application defines hybrid bonding as “stacks and bonds dies using both dielectric bonding layers and metal-to-metal interconnects”, this definition would match the definition of “fusion bonding” as quoted above.); and
bonding the dummy die on the bottom die by bonding the first bonding layer and the third bonding layer (Para. 34, “dielectric layers 26 in dummy dies 32-1 bonded to dielectric layer 76”), wherein the at least one dummy metal pad is located only at a periphery of the overlapping region (Fig. 30, where any one of the dummy metal pads (152D/27) in the outer ring of the dummy metal pads in the overlapping region (32-1) is located at the periphery of the overlapping region.
Regarding claim 21, the limitation of “copper atoms of the at least one dummy metal pad are oxidized after the dummy die is bonded to the bottom die” is a process, and the claim is directed to a product. It has been held that a product-by-process claim is directed to the product per se, regardless of how the product is actually made. In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein make it clear that it is the final product which must determine patentability in a product-by-process claim, and not the process by which it is made. Further, an old or obvious product produced by a new method is not patentable as a product, whether claimed in a product-by-process claim or not. As stated in In re Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935) Perdue Pharma v. Epic Pharma, App. No. 2014-1294 (Fed. Cir. 2016); As long as the prior art meets the limitations of having the dummy metal pads comprising copper, the prior art discloses the fictional limitations.
Furthermore, Chen semiconductor package of claim 1, wherein the at least one dummy metal pad comprises copper, and copper atoms of the at least one dummy metal pad are oxidized after the dummy die is bonded to the bottom die (Chen: Para. 15, lines 4-5).
Regarding claim 22, the limitation of “copper atoms of the at least one dummy metal pad are oxidized after the dummy die is bonded to the bottom die” is a process, and the claim is directed to a product. It has been held that a product-by-process claim is directed to the product per se, regardless of how the product is actually made. In re Thorpe, 227 USPQ 964 (CAFC, 1985) and the related case law cited therein make it clear that it is the final product which must determine patentability in a product-by-process claim, and not the process by which it is made. Further, an old or obvious product produced by a new method is not patentable as a product, whether claimed in a product-by-process claim or not. As stated in In re Thorpe, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. In re Brown, 459 F.2d 531, 535, 173 USPQ 685, 688 (CCPA 1972); In re Pilkington, 411 F.2d 1345, 162 USPQ 145 (CCPA 1969); Buono v. Yankee Maid Dress Corp., 77 F.2d 274, 279, 26, USPQ 57, 61 (2d. Cir 1935) Perdue Pharma v. Epic Pharma, App. No. 2014-1294 (Fed. Cir. 2016); As long as the prior art meets the limitations of having the dummy metal pads comprising copper, the prior art discloses the fictional limitations.
Furthermore, Chen semiconductor package of claim 22, wherein the at least one dummy metal pad comprises copper, and copper atoms of the at least one dummy metal pad are oxidized after the dummy die is bonded to the bottom die (Chen: Para. 15, lines 4-5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8, 14-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable as obvious by Chen in view of Kao Et al. (US 20180025970 A1; Kao)
Regarding Claim 2. Chen discloses the semiconductor package of claim 1. Also, Chen discloses wherein the first bonding layer, the second bonding layer, and the third bonding layer are made of silicon oxide (Para. 14, lines 1-4; Para. 21, lines 6-10; Para. 30, lines 4-6), which may include silicon dioxide, but does not explicitly disclose silicon dioxide as the dielectric bond layer.
In a similar field of endeavor, Kao discloses a semiconductor package stacking die’s using hybrid bonding where the dielectric-to-dielectric bonding portion is made using silicon dioxide (Kao: Para. 29, Lines 3-7)
In view of the disclosure of Kao, it would have been obvious for a person of
ordinary skill in the art to apply the disclosure of Kao to Chen at the time the instant application was filed in order to use dielectric-to-dielectric bonding with silicon dioxide. Accordingly, one would be motivated to make the modification for the benefit of increased design freedom and flexibility (Kao: Para. 21, Lines 5-11).
Regarding Claim 3, Chen and Kao disclose the semiconductor package of claim 2, and further wherein the at least one dummy metal pad is made of copper (Chen: Para. 15, lines 4-5).
Regarding Claim 4, Chen and Kao disclose the semiconductor package of claim 3 and further wherein the at least one dummy metal pad is formed in the first bonding layer (Chen: Fig. 18, where the dummy metal pad [152D] is formed in the first bonding layer [76]).
Regarding Claim 5, Chen and Kao disclose the semiconductor package of claim 4 and further wherein at least one first hybrid bonding metal pad (Chen: 152A) is formed in the first bonding layer (Chen: 76), at least one second hybrid bonding metal pad (Chen: 52A) is formed in the second bonding layer (Chen: 54), and the first hybrid bonding metal pad is in contact with the second hybrid bonding metal pad (Chen: Fig. 17, where the 2 hybrid bond pads are in contact, Para. 32, Lines 14-17)
Regarding Claim 6. Chen and Kao disclose the semiconductor package of claim 5, wherein the at least one first hybrid bonding metal pad and the at least one dummy metal pad are formed simultaneously.
“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)
United Therapeutics Corp. v Liquidia Techs., Inc., 74 F.4th 1360, 1373, 2023 USPQ2d 862 (Fed. Cir. 2023) (the court held that product-by-process claims were properly rejected as “anticipated by a disclosure of the same product irrespective of the processes by which they are made.”); and Purdue Pharma v. Epic Pharma, 811 F.3d 1345, 117 USPQ2d 1733 (Fed. Cir. 2016). However, in the context of an infringement analysis, a product-by-process claim is only infringed by a product made by the process recited in the claim. Id. at 1370 (“a product in the prior art made by a different process can anticipate a product-by-process claim, but an accused product made by a different process cannot infringe a product-by-process claim”).
Because the only limitation added to this claim is related to a process step of forming the pads simultaneously, the device claim will maintain the 35 U.S.C. 103 obviousness rejection from the above dependency claims.
Regarding Claim 7, Chen and Kao disclose the semiconductor package of claim 3, and furthermore, wherein the at least one dummy metal pad is formed in the third bonding layer (Chen: Para. 15, “dummy metal pads 27 are formed in bond layer 26”).
Regarding Claim 8, Chen and Kao disclose the semiconductor package of claim 3, wherein the at least one dummy metal pad is configured to reduce water-containing voids.
Paragraph 29 of the instant application describes the way the water containing voids is reduced, is based on a few key elements. An example is the dummy metal pads being made of copper, and the copper metal pads are in contact with the dielectric containing an oxide making a dielectric-to-metal contact. “Then the dummy metal pads are oxidized to become copper oxide (CuO), and gaseous hydrogen (H2) is generated. The gaseous hydrogen can diffuse and exit the dielectric-to-dielectric bonding interface. As a result, the water- containing voids are reduced or even eliminated, therefore enhancing the bonding force between”.
Accordingly, in the Chen reference, the dummy copper metal pads are formed in the oxide containing dielectric layer (Chen: Para, 15 where the pads are formed and made of copper; Para. 14, for the bond layer being a silicon oxide layer). As a result, according to the instant application, the water containing voids will be reduced because of the configuration and materials used.
Regarding Claim 14 Chen discloses the semiconductor package of claim 13.
Chen also discloses wherein the first bonding layer and second bonding layer are made of silicon oxide (Chen: Para. 21, lines 6-10; Para. 30, lines 4-6), which may include silicon dioxide, but does not explicitly disclose silicon dioxide as the dielectric bond layer.
In a similar field of endeavor, Kao discloses a semiconductor package stacking die’s using hybrid bonding where the dielectric-to-dielectric bonding portion is made using silicon dioxide (Kao: Para. 29, Lines 3-7)
In view of the disclosure of Kao, it would have been obvious for a person of
ordinary skill in the art to apply the disclosure of Kao to Chen at the time the instant application was filed in order to use dielectric-to-dielectric bonding with silicon dioxide. Accordingly, one would be motivated to make the modification for the benefit of increased design freedom and flexibility (Kao: Para. 21, Lines 5-11).
Regarding Claim 15, Chen and Kao disclose the semiconductor package of claim 14, and further wherein the at least one dummy metal pad is made of copper (Chen: Para. 15, lines 4-5).
Regarding Claim 16, Chen and Kao disclose the semiconductor package of claim 15, and further wherein the at least one dummy metal pad is formed in the first bonding layer (Chen: Fig. 18, where the dummy metal pad [152D] is formed in the first bonding layer [76]).
Regarding Claim 17, Chen and Kao disclose the semiconductor package of claim 15, wherein the at least one dummy metal pad is formed in the second bonding layer (Chen: Para. 21, lines 1-3).
Regarding Claim 18, Chen and Kao disclose the semiconductor package of claim 15, wherein the at least one dummy metal pad is configured to reduce water-containing voids.
Paragraph 29 of the instant application describes the way the water containing voids is reduced, is based on a few key elements. An example is the dummy metal pads being made of copper, and the copper metal pads are in contact with the dielectric containing an oxide making a dielectric-to-metal contact. “Then the dummy metal pads are oxidized to become copper oxide (CuO), and gaseous hydrogen (H2) is generated. The gaseous hydrogen can diffuse and exit the dielectric-to-dielectric bonding interface. As a result, the water- containing voids are reduced or even eliminated, therefore enhancing the bonding force between”.
Accordingly, in the Chen reference, the dummy copper metal pads are formed in the oxide containing dielectric layer (Chen: Para, 15 where the pads are formed and made of copper; Para. 14, for the bond layer being a silicon oxide layer). As a result, according to the instant application, the water containing voids will be reduced because of the configuration and materials used.
Regarding Claim 20, Chen discloses the method of claim 19, and wherein the at least one dummy metal pad is made of copper.
Also, Chen discloses wherein the first bonding layer, the second bonding layer, and the third bonding layer are made of silicon oxide (Para. 14, lines 1-4; Para. 21, lines 6-10; Para. 30, lines 4-6), which may include silicon dioxide, but does not explicitly disclose silicon dioxide as the dielectric bond layer.
In a similar field of endeavor, Kao discloses a semiconductor package stacking die’s using hybrid bonding where the dielectric-to-dielectric bonding portion is made using silicon dioxide (Kao: Para. 29, Lines 3-7)
In view of the disclosure of Kao, it would have been obvious for a person of
ordinary skill in the art to apply the disclosure of Kao to Chen at the time the instant application was filed in order to use dielectric-to-dielectric bonding with silicon dioxide. Accordingly, one would be motivated to make the modification for the benefit of increased design freedom and flexibility (Kao: Para. 21, Lines 5-11).
Claims 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Sung et al. (US 20200091123 A1; Sung).
Regarding claim 9, Chen discloses the semiconductor package of claim 1 but fails to explicitly disclose any distances or scale of the device. So, while it could very well be true that Chen has a first distance between the at least one dummy metal pad and an outline of the dummy die in a first horizontal direction is larger than 0.5µm, Chen fails to explicitly disclose it.
In a similar field of endeavor, Sung discloses a semiconductor package 10 with dummy die 250 in (Fig 7) and dummy pads 370-5 in (Figs. 4 and 7). Sung also discloses wherein a first distance between the at least one dummy metal pad and an outline of the dummy die in a first horizontal direction is larger than 0.5µm (The post bumps 400 which are disposed over the dummy pads 370-5 making them the same length in the horizontal direction, is 60pm. Looking at fig. 7, there is at least the distance of other post bumps between the furthest dummy pad and the outline to dummy die 250).
In view of the disclosure of Sung, it would have been obvious for a person of
ordinary skill in the art to apply the disclosure of Sung to Chen at the time the instant application in order to augment the distance of the dummy metal pads to the border of the dummy die in a horizontal direction. Accordingly, one would have been motivated to make this modification for the benefit of redundancy (Para. 56).
Regarding claim 11, Chen discloses the semiconductor package of claim 1 but fails to explicitly disclose any distances or scale of the device. So, while it could very well be true that Chen has at least one dummy metal pad includes a plurality of dummy metal pads, and a second distance between any two of the plurality of dummy metal pads in a first horizontal direction is equal to or larger than 0.1µm, Chen fails to explicitly disclose it.
In a similar field of endeavor, Sung discloses a semiconductor package 10 with dummy die 250 in (Fig 7) and dummy pads 370-5 in (Figs. 4 and 7). Sung also discloses wherein the at least one dummy metal pad includes a plurality of dummy metal pads (Fig. 7, where there are multiple dummy metal pads 370-5), and a second distance between any two of the plurality of dummy metal pads in a first horizontal direction is equal to or larger than 0.1µm (Para. 43, where the post bumps 400 are 60um in length in the horizontal direction).
In view of the disclosure of Sung, it would have been obvious for a person of
ordinary skill in the art to apply the disclosure of Sung to Chen at the time the instant application in order to augment the distance of the dummy metal pads from each other in the horizontal direction. Accordingly, one would have been motivated to make this modification for the benefit of redundancy (Para. 56).
Conclusion
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/DANIEL J HIBBERT/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899