DETAILED ACTION
Claims 1-9, 12-13, and 17-25 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The amended title of the invention is not sufficiently descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
This is a reminder that patent numbers must be provided in paragraphs 2 and 3 for related applications, when they issue.
The disclosure is objected to because of the following informalities:
In paragraph 29, replace “used to execution” with --used to execute--.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 17-18 set forth ignoring operations associated with the branch decision that are not indicated by the branch decision. Parent claim 1 has been amended to set forth suppressing operations associated with the branch decision that are not indicated by the branch decision. The examiner cannot find support for performing both ignoring and suppressing of operations associated with the same branch decision. The application describes the two actions as alternatives (using “or” language in at least paragraphs 29, 32, and 45, and illustrating separate steps 140 and 142 in FIG.1) and the examiner does not understand the difference between these two terms based on the specification. As such, saying that a single branch decision corresponds to an ignored operation and a suppressed operation appears to be new matter.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 12-13, and 17-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hamzeh et al., “Branch-Aware Loop Mapping on CGRAs”.
Referring to claim 1, Hamzeh has taught a processor-implemented method for program execution, the method comprising:
accessing a two-dimensional (2D) array of compute elements (FIGs.1-5), wherein each compute element within the array of compute elements is known to a compiler (see FIGs.3-5 and note the partial prediction, full prediction, and dual issue streams, all of which involve a compiler transforming code and assigning code to the compute elements (see section 3 as well)) and is coupled to its neighboring compute elements within the array of compute elements (see FIGs.1-5);
providing control for the array of compute elements on a cycle-by-cycle basis (see FIGs.3-5. Instructions are assigned to compute elements to provide control over a number of cycles), wherein the control is enabled by a stream of variable length control words generated by the compiler (a control word may either be the entirety of what is assigned to the CGRA (e.g. everything assigned in FIG.5 is a control word), in which case, a stream of control words would be generated and assigned to the CGRA as loops are executed over the course of executing one or more programs. Note that, based on the loop, or optimization algorithm, a number of different operations may be assigned, and, thus, the control word size may be different. Alternatively, a control word may include a subset of operations assigned to the CGRA (e.g. just those in one row of the FIG.5). Note that each row may have a different number of operations (e.g. in FIG.5, the first and second rows have three-op control words, the third row has a two-operation control word, and the last row has a one-operation control word). Note that the size is determined by the loop and the optimization performed by the compiler);
coalescing two or more operations into a control word (again, when the control word is the entirety of the loop body that is assigned, all loop body operations are coalesced to form a control word. Alternatively, a single row would have multiple coalesced operations forming a control word), wherein the control word includes a branch decision and operations associated with the branch decision (see FIGs.3-5. Note that the control word representing the entire loop body includes an operation to make a branch decision, and operations associated therewith. As an example, in FIG.3(d), h is determined by the 3rd element at time 1. This corresponds to instruction 4 in FIG.3(b), which is an instruction that determines which branch to take. The control word also includes operations associated with the branch decision, e.g. the operations to determine et and ef, the select operation, and the operation to determine f. When the control word is a single row of operations, such operations are similarly coalesced (e.g. in FIG.5, the second row has a branch decision operation (e.g. accessing h in the 3rd element) combined with performing an e operation based on h, and a c operation, which is also associated with the branch decision because it determines a value c that is used in the calculation of f, which is also based on the branch decision)), and
suppressing one or more operations associated with the branch decision that are not indicated by the branch decision, wherein the suppressing prevents data from being committed (this is the case in each of examples of FIGs.3-5. Note the descriptions thereof. The loop body executes a branch that causes only one of two paths to fully execute. The other is suppressed in some way (e.g. in FIG.3(d), which shows partial predication (section 2.1), operations to set et and ef are both performed, but the result of only one of the operations is selected to set e. Thus, the non-selected one could be said to be suppressed since it’s result is prevented from being propagated to and committed into e. In FIG.4(c), which shows full predication, has two instructions (5 and 6) to set variable e). One of them is allowed to execute and the other is squashed (suppressed) such that the suppressed operation’s data is not committed. This is based on the branch decision represented by predicate h. Finally, in FIG.5(c), both e instructions are dual issued to the same PE, but only one is executed based on h. The other can thus be said to be suppressed/prevented from acting).
Referring to claim 2, Hamzeh has taught the method of claim 1 wherein the control word includes speculatively encoded operations for at least two possible branch paths (when the control word is the entirety of what is assigned, see FIGs.3-5, and note that the control word includes two branches (e) (e.g. FIG.3(d), row 2; or FIG.5(c), row 2, ‘e’, which represents both paths). This is speculative encoding, because branches are put in there because either one may be executed. In the case of FIG.3(d), both are executed (one incorrectly), which is resolved by the subsequent select operation). When the control word is just one row, similar reasoning applies. For instance, see FIG.3(d), row 2. Both ‘e’ branches are coalesced and performed in that cycle).
Referring to claim 3, Hamzeh has taught the method of claim 2 wherein the at least two possible branch paths generate independent side effects (the loop body that is the example of FIGs.3-5 has two separate paths based on whether e < X3. In one path, a side effect of e being set to b x X4 occurs, and in the other, a side effect of e being set to b x X5 occurs).
Referring to claim 4, Hamzeh has taught the method of claim 2 wherein the at least two possible branch paths generate compute element actions that must be committed (from above, the two paths generate an update to e that must be committed for the correctly executed path. Otherwise, incorrect execution would result).
Referring to claim 5, Hamzeh has taught the method of claim 2 wherein the operations for at least two possible branch paths can be performed in parallel by the 2D array of compute elements (again, see FIG.3(d), row 2, where both branch paths are executed in parallel).
Referring to claim 7, Hamzeh has taught the method of claim 1 wherein the branch decision supports a programming loop (see the title, the caption of FIG.3(a), etc. Hamzeh is concerned with accelerating loops on a CGRA. The code of FIGs.3-5 is a loop body. Thus, any operation assigned to the CGRA is one that supports performance of the loop).
Referring to claim 8, Hamzeh has taught the method of claim 7 wherein the two or more operations include operations from both an end of the loop and a beginning of the loop (when the control word is the entirety of what is assigned, it includes the entire loop, including a beginning and end).
Referring to claim 9, Hamzeh has taught the method of claim 1 wherein the two or more operations control data flow within the 2D array of compute elements (all operations result in some data flow to carry out the loop body).
Referring to claim 12, Hamzeh has taught the method of claim 1 wherein the suppressing is accomplished dynamically (the suppressing would occur in response to runtime (dynamic) determination of the direction of the branch).
Referring to claim 13, Hamzeh has taught the method of claim 1 wherein the suppressing enables power reduction in the 2D array of compute elements (in FIG.3, both paths are executed, which requires some power in both elements executing both paths. However, from section 2.2 and 2.3, the suppressing in FIGs.4-5 causes only one of the two paths to be executed. Thus, in terms of executing the branch paths, FIGs.4-5 would require lower power than that of FIG.3).
Referring to claim 17, Hamzeh has taught the method of claim 1 further comprising ignoring one or more operations associated with the branch decision that are not indicated by the branch decision (see sections 2.2 and 2.3. In FIGs.4-5, only one branch path is executed. The other is ignored. Even in FIG.3, though both paths are executed, the wrong path is still ignored because it is not selected).
Referring to claim 18, Hamzeh has taught the method of claim 17 wherein the ignoring is accomplished by setting an idle bit in the control word (The setting of the h bit in the control word causes the ignoring).
Referring to claim 19, Hamzeh has taught the method of claim 1 wherein the coalescing includes two or more operational cycles of the cycle-by-cycle basis (see FIGs.3-5).
Referring to claim 20, Hamzeh has taught the method of claim 19 wherein the coalescing enables a reduction of operational cycles of the cycle-by-cycle basis (see FIG.5, which shows a II of two cycles, which means the next iteration can start after 2 cycles of starting the previous iteration (see caption of FIG.2(d)). Thus, the mapping of FIG.5 reduces overall loop cycles).
Referring to claim 21, Hamzeh has taught the method of claim 1 wherein each operation from the operations represents an instruction equivalent (each operation in FIGs.3-5 is an instruction equivalent, e.g. a branch instruction, an operation instruction, a select instruction, etc.).
Referring to claim 22, Hamzeh has taught the method of claim 21 wherein the instruction equivalent comprises a building block for a high-level language (from section 2.3, all mapping schemes are performed by the compiler, whose understood purpose is to change code from a high-level language (e.g. C, C+, etc.) to low-level assembly code instructions (building blocks). That is, each high-level instruction corresponds to one or more assembly instructions. Thus, each assembly instruction is a building block for a high-level language).
Referring to claim 23, Hamzeh has taught the method of claim 1 wherein the stream of variable length, control words generated by the compiler provide direct, fine-grained control of the 2D array of compute elements (the control words control each individual functional unit in the compute elements. Thus, they provide for fine-grained control).
Claim 24 is mostly rejected for similar reasoning as claim 1. Hamzeh has further taught a computer program product embodied in a non-transitory computer readable medium for program execution, the computer program product comprising code which causes one or more processors to perform the claimed operations (Hamzeh’s compiler is software stored on a medium for execution by at least one processor. The compiler here would access the 2D array by compiling instructions for it, e.g. it references the functional units in the particular array so as to coalesce instructions into control words to provide control for those functional units).
Claim 25 is rejected for similar reasoning as claim 24. That is, a compiler must be stored in memory, which is accessed by a processor to execute the compiler to perform the claimed steps.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Hamzeh in view of the examiner’s taking of Official Notice.
Referring to claim 6, Hamzeh has taught the method of claim 1 but has not taught wherein the branch decision supports subroutine execution. However, Official Notice is taken that a subroutine was well known in the art before applicant’s invention. A subroutine is a callable unit of software that may be invoked multiple times without having to repeat the code multiple times. As such, in order to efficiently execute code without repeating it (to keep code size lower), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hamzeh such that the branch decision supports subroutine execution (this could be by including the loop of FIGs.3-5 in a subroutine).
---------------------------------------------------------------------------------------------------------------------
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 9, 12-13, and 17-25 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., U.S. Patent No. 8,949,806 (as cited by applicant), in view of Moreno, U.S. Patent No. 5,669,001.
Referring to claim 1, Lee has taught a processor-implemented method for program execution, the method comprising:
accessing a two-dimensional (2D) array of compute elements (FIGs.1 and 2A), wherein each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements (see column 5, lines 18-23, and note the array may include VLIW architecture, where a compiler is known to statically schedule instructions on parallel compute units. Also, from at least FIGs.1-2C, the compute units are coupled to neighboring compute units);
providing control for the array of compute elements on a cycle-by-cycle basis (such is the case with VLIW, where a compiler controls which elements execute instructions each cycle), wherein the control is enabled by a stream of control words generated by the compiler (this is the nature of VLIW. Multiple instructions corresponding to multiple hardware resources are packed into a VLIW (control word) for parallel execution);
coalescing two or more operations into a control word (again, this is the nature of VLIW); and
suppressing one or more operations associated with the branch decision that are not indicated by the branch decision, wherein the suppressing prevents data from being committed (this is necessarily the case for execution of t2 in Moreno. Again, recall that all instructions are executed in parallel in a tree instruction. Thus, in FIG.4, for t2, multiple branch paths are executing at once. However, only one branch is the correct branch based on the branch condition C4. In order to realize correct execution (and not erroneous results), the operations associated with the incorrect path must be suppressed in some manner, which would include not committing any results generated by the incorrect path).
Lee has not taught that the control words are variable length control words, wherein the control word includes a branch decision and operations associated with the branch decision. However, Moreno has taught VLIW instructions that are variable in length to execute a tree with conditional branches (see the tree of FIG.1, which is compiled into VLIW instructions shown in FIG.4 (the bolded boundaries create variable-length VLIWs). A given control word may include a branch decision (e.g. a branch, indicated by “if” in FIG.4) and operations associated with the branch decision (e.g. op# in FIGs.1 and 4)). The ability to provide for variable length allows the system to configurably create instructions based on the given tree being executed, which may vary in number of branches, ops, etc. Additionally, coalescing branches and operations associated therewith, as done in Moreno, would allow for parallel execution of branches and those operations so that the operations don’t have to wait for the branch outcome to be determined (see column 4, lines 29-31, where all operations in a tree instruction are executable in parallel). As a result, to accommodate different tree configurations and to increase speed of execution, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee such that the control words are variable length control words, wherein the control word includes a branch decision and operations associated with the branch decision.
Referring to claim 2, Lee, as modified, has taught the method of claim 1 wherein the control word includes speculatively encoded operations for at least two possible branch paths (see Moreno’s FIG.4, the instruction beginning with t2. This instruction includes op5 and op1, which from Moreno’s FIG.1, are in the two possible paths of branch C4).
Referring to claim 3, Lee, as modified, has taught the method of claim 2 wherein the at least two possible branch paths generate independent side effects (for t2, one path executes op5 and branches to path D, and the other executes op1 and branches to path C. These are independent side effects).
Referring to claim 4, Lee, as modified, has taught the method of claim 2 wherein the at least two possible branch paths generate compute element actions that must be committed (results of execution need to be committed. For t2, a result of op5 in one path, and a result of op1 in another path, must be committed (if the path is executed)).
Referring to claim 5, Lee, as modified, has taught the method of claim 2 wherein the operations for at least two possible branch paths can be performed in parallel by the 2D array of compute elements (again, see column 4, lines 29-31, or Moreno, where all operations in a tree instruction are executable in parallel).
Referring to claim 9, Lee, as modified, has taught the method of claim 1 wherein the two or more operations control data flow within the 2D array of compute elements (from FIGs.1 and 4 of Moreno, the t2 instruction has multiple branches, which control data flow. Even the primitive operations (op4, op5, op1) will cause data to flow through the system in some manner).
Referring to claim 12, Lee, as modified, has taught the method of claim 1 wherein the suppressing is accomplished dynamically (the suppressing would occur in response to runtime (dynamic) determination of the direction of the branch).
Referring to claim 13, Lee, as modified, has taught the method of claim 1 wherein the suppressing enables power reduction in the 2D array of compute elements (it takes more power to fully process an operation than it does not fully process an operation. As such, suppressing/canceling the operations involved with the incorrect path would reduce power (e.g. the processor would not spend power writing the result of an operation that should not have its result written)).
Referring to claim 17, Lee, as modified, has taught the method of claim 1 further comprising ignoring one or more operations associated with the branch decision that are not indicated by the branch decision (for similar reasoning given above, only one of the two branch paths is ultimately correct and executed. The other is canceled/suppressed/ignored, i.e., the results of the execution would not be written).
Referring to claim 18, Lee, as modified, has taught the method of claim 17 wherein the ignoring is accomplished by setting an idle bit in the control word (for t2 in FIG.4 of Moreno, C4 is an idle bit in the control word. Setting it will cause one of the two paths emanating from C4 in FIG.1 to be ignored).
Referring to claim 19, Lee, as modified, has taught the method of claim 1 wherein the coalescing includes two or more operational cycles of the cycle-by-cycle basis (t2 includes a branch cycle and subsequent operation cycles (note FIG.1)).
Referring to claim 20, Lee, as modified, has taught the method of claim 19 wherein the coalescing enables a reduction of operational cycles of the cycle-by-cycle basis (this is the point of parallel execution with VLIW; to operate in parallel where possible to reduce overall cycles required).
Referring to claim 21, Lee, as modified, has taught the method of claim 1 wherein each operation from the operations represents an instruction equivalent (each operation in FIG.1 of Moreno is an instruction equivalent, e.g. a branch instruction, an operation instruction, etc.).
Referring to claim 22, Lee, as modified, has taught the method of claim 21 wherein the instruction equivalent comprises a building block for a high-level language (both Lee (e.g. title) and Moreno (e.g. abstract) are based on compiling code. The purpose of a compiler is to change code from a high-level language (e.g. C, C+, etc.) to low-level assembly code instructions (building blocks). That is, each high-level instruction corresponds to one or more assembly instructions. Thus, each assembly instruction is a building block for a high-level language).
Referring to claim 23, Lee, as modified, has taught the method of claim 1 wherein the stream of variable length, control words generated by the compiler provide direct, fine-grained control of the 2D array of compute elements (the control words control each individual functional unit in the compute elements. Thus, they provide for fine-grained control).
Claim 24 is mostly rejected for similar reasoning as claim 1. Lee has further taught a computer program product embodied in a non-transitory computer readable medium for program execution, the computer program product comprising code which causes one or more processors to perform the claimed operations (Lee, throughout discusses a compiler to generate the VLIW instructions for the array. A compiler is software stored on a medium for execution by at least one processor. The compiler here would access the 2D array by compiling instructions for it, e.g. it references the functional units in the particular array so as to coalesce instructions into VLIWs to provide control for those functional units).
Claim 25 is rejected for similar reasoning as claim 24. That is, a compiler must be stored in memory, which is accessed by a processor to execute the compiler to perform the claimed steps.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Moreno and the examiner’s taking of Official Notice.
Referring to claim 6, Lee, as modified, has taught the method of claim 1 but has not taught wherein the branch decision supports subroutine execution. However, Official Notice is taken that a subroutine was well known in the art before applicant’s invention. A subroutine is a callable unit of software that may be invoked multiple times without having to repeat the code multiple times. A subroutine is branched to in a manner similar to the code branches to in Moreno. As such, in order to efficiently execute code without repeating it (to keep code size lower), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee such that the branch decision supports subroutine execution (e.g. by either conditionally calling a subroutine, or by having the branch decision made in a subroutine).
Referring to claim 7, Lee, as modified, has taught the method of claim 1 but has not taught wherein the branch decision supports a programming loop. However, a loop was well known in the art before applicant’s invention. A loop allows for repeating a segment of code without repeating the code itself, thereby keeping program size smaller. Loops include conditional branches such as backwards branches, which are similar to those in Lee. As a result, in order to efficiently execute code without repeating it (to keep code size lower), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee such that the branch decision supports a programming loop. (e.g. by either conditionally branching back to the beginning of the loop, or by having the branch decision made in a loop).
Referring to claim 8, Lee, as modified, has taught the method of claim 7 but has not taught wherein the two or more operations include operations from both an end of the loop and a beginning of the loop. However, the loop can be implemented in any way, i.e., can contain any number of instructions, and/or loop over any segment of code as desired by the programmer. As an example, from Moreno’s FIG.1, instead of a branch to D, a branch to loop back to the beginning of f4 could be implemented so as to repeat op5 some number of times. As a result, in order to repeat op5 when desired, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee such that the “branch to D” instruction is replaced with a “branch to f4” instruction. With such a loop, op5 (beginning of loop) and the branch at the end of the loop (branch to f4) would be coalesced as shown in FIG.4 of Lee.
Response to Arguments
On page 12 of applicant’s response, applicant argues that “the cited Hamzeh art explicitly states that only one operation is executed, which is chosen at run time. Hamzeh goes on to describe that ‘Depending on the result of the conditional operation, only one of them is executed at runtime’ (Hamzeh, page 3, section 2.3, first paragraph, emphasis added). The cited Hamzeh art, thus, strongly teaches away from the applicant's claimed invention.”
The examiner respectfully disagrees. FIG.3 of Hamzeh explicitly shows executing both conditional operations. A subsequent select operation is then used to select the result of only one of the conditional operations (that one that is to execute when the condition is satisfied). Thus, the other is suppressed, and the data generated thereby, is not committed (written to variable e). In FIGs.4-5, only one operation executed while the other is squashed or not executed, which is a reasonable mapping to suppression, which is merely a prevention of an action. When an instruction is forcibly not executed/squashed, its action is prevented/suppressed.
On page 13 of applicant’s response, applicant argues that “Lee describes extensive use of predication, in which instructions are scheduled, but not ultimately executed, which is the opposite of executing both sides of a branch instruction. In fact, at no time does the cited Lee art describe” applicant’s amended claim 1. Applicant also summarizes Moreno and concludes that “at no time does the cited Moreno art describe” applicant’s amended claim 1, before concluding that the combination of the prior art does not teach amended claim 1.
The examiner respectfully disagrees. First, applicant’s claim 1 does not require executing both sides of a branch instruction. Second, it is the combination with Moreno that teaches claim 1, and applicant does not explain why reliance on Moreno is improper. Therefore, the rejection is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to David J. Huisman whose telephone number is 571-272-4168. The examiner can normally be reached on Monday-Friday, 9:00 am-5:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta, can be reached at 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/David J. Huisman/Primary Examiner, Art Unit 2183