The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8-10, 13-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hong et al. (7,220,991) in view of Yuan et al. (2013/0207100).Regarding claims 1 and 18, Hong et al. teach in figure 24 and related text a display device comprising:
a substrate 10 including a display area and a pad area (on the left);
a first conductive layer disposed on the substrate and including a first signal line 92 disposed in the display area;
a buffer layer 40 disposed on the first conductive layer;
a semiconductor layer 70 disposed on the buffer layer 40 in the display area;
a gate insulating film 60 disposed on the semiconductor layer 70;
a second conductive layer disposed on the gate insulating film and including a gate electrode 56 (see figure 4) overlapping with the semiconductor layer in the display area,
a first transistor electrode 111/85 of a transistor disposed to overlap one side of the semiconductor layer in the display area and connected to the first signal line 92 through a contact hole 61 penetrating through the buffer layer 40 and the gate insulating film 60, and
a second transistor electrode 86 of the transistor disposed to overlap the other side of the semiconductor layer in the display area;
a first pad 54 disposed on the buffer layer 40 in the pad area and exposed by a pad opening;
a first insulating layer (un-numbered) disposed on the second conductive layer and the first pad 54; and
a light emitting element (inherently located in display area 151, see figures 1 and 2) disposed on the first insulating layer in the display area,
wherein the first pad 54 is formed of the first conductive layer or the second conductive layer, and
wherein the gate electrode, the first transistor electrode of the transistor, and the second transistor electrode of the transistor are disposed directly on a same layer (the substrate).
Hong et al. do not explicitly state having a light emitting element disposed on the first insulating layer in the display area and do not teach that the gate electrode overlapping the semiconductor layer such that the gate electrode, the first transistor electrode of the transistor, and the second transistor electrode of the transistor are of the same second conductive layer and respectively have bottom surfaces contacting a same upper surface of the gate insulating film.
Yuan et al. teach in figure 5 and related text a light emitting element (not shown) disposed on the first insulating layer in the display area (transmitted by a pixel area which comprises TFT) and wherein the gate electrode 402a overlapping the semiconductor layer 224, such that the gate electrode 402a, the first transistor electrode 406a of the transistor, and the second transistor electrode 406b of the transistor are of the same second conductive layer and respectively have bottom surfaces contacting a same upper surface of the gate insulating film 403.
French et al., Yuan et al. and Hong et al. are analogous art because they are directed to TFT devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hong et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to dispose a light emitting element on the first insulating layer in the display area and to use an SOI substrate such that the gate electrode overlapping the semiconductor layer and to form the gate electrode, the first transistor electrode of the transistor, and the second transistor electrode of the transistor are of the same second conductive layer and respectively have bottom surfaces contacting a same upper surface of the gate insulating film, as taught by Yuan et al., in Hong et al.’s device, in order to operate the device in its intended use, in order to provide better protection to the device (by using SOI substrate) and in order to improve the device characteristics, respectively.
Regarding the claimed limitation of “wherein a bottom surface of the gate electrode directly contacts an upper surface of the gate-insulating film, wherein a bottom surface of the first transistor electrode of the transistor directly contacts the upper surface of the gate-insulating film, wherein a bottom surface of the second transistor electrode of the transistor directly contacts the upper surface of the gate-insulating film”, Hong et al. do not teach said limitation.
In other words, Hong et al. do not teach using top gate structure instead of bottom gate.
French et al. teach in related text using top gate structure instead of bottom gate.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use a top gate structure instead of a bottom gate, as taught by French et al., in prior art’s device, in order to improve the device characteristics, by the ease with which a low resistance gate line can be made with a highly conductive top-gate metal such as aluminum and the ability to also have a fully self-aligned structure in a top-gate TFT opens up the prospect of combining these advantages, for large area electronics applications.
The combination is motivated by the teaching of French et al. who point out the advantageous of using bottom gate structures instead of bottom gate structures.
Regarding claim 18, Hong et al., Yuan et al. and French teach substantially the entire claimed structure, as applied to claim 1 above, including a first pad disposed in the pad area;
a first contact electrode 111 disposed in the display area and electrically connecting the transistor, the first electrode 85, and one end of the light emitting element LEL to each other (inherently therein); and
a pad electrode 114 disposed in the pad area and electrically connected to the first pad 54 through a pad opening penetrating through the buffer layer 60 and the first insulating layer,
wherein the first electrode of the transistor is electrically connected to the first signal line through a contact hole penetrating through the buffer layer and the gate insulating film.
Regarding claim 2, in the combined device, Hong et al. teach in figure 24 and related text a passivation layer (un-numbered) disposed on the second conductive layer and the first pad; a via layer (un-numbered) disposed on the passivation layer; and a first electrode 85 and a second electrode 86 disposed on the via layer in the display area and spaced apart from each other, wherein the first insulating layer is disposed on the first electrode and the second electrode, the light emitting element (in the combined device) is disposed between the first electrode and the second electrode on the first insulating layer, and the pad opening is defined by the first insulating layer.
Regarding claim 3, Hong et al. do not teach in figure 24 and related text that the first pad is formed of the first conductive layer, the pad opening is defined by the first insulating layer and the buffer layer, and sidewalls of the first insulating layer and the buffer layer defining the pad opening are aligned with each other.
It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first pad of the first conductive layer, wherein the pad opening is defined by the first insulating layer and the buffer layer, and sidewalls of the first insulating layer and the buffer layer defining the pad opening are aligned with each other in prior art’s device in order to use the device in application which requires a pad connection at the bottom of the device.
Regarding claim 4, Hong et al. teach in figure 24 and related text that the passivation layer and the via layer are not disposed in the pad area.
Regarding claim 5, Hong et al. teach in figure 24 and related text that sidewalls of the via layer and sidewalls of the passivation layer are aligned with each other.
Regarding claim 8, Hong et al. teach in figure 24 and related text that the first transistor electrode of the transistor is covered by the passivation layer (un-numbered) and the via layer, and the second transistor electrode of the transistor is exposed by a first electrode contact hole penetrating through the passivation layer and the via layer.
Regarding claim 9, Hong et al. teach in figure 24 and related text that the first electrode is in contact with and electrically connected to the second electrode of the transistor through the first electrode contact hole.
Regarding claim 10, in the combined device a first contact electrode (see Chen et al.) in contact with one end of the light emitting element and the first electrode exposed by the first insulating layer.
Regarding claim 13, Hong et al. teach in figure 24 and related text a pad electrode 114 disposed on the first insulating layer in the pad area and in contact with the first pad 54 exposed by the pad opening. Hong et al. do not teach that a first contact electrode disposed on the light emitting element in the display area and in contact with one end of the light emitting element and a second contact electrode disposed on the light emitting element in the display area and in contact with the other end of the light emitting element. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a first contact electrode disposed on the light emitting element in the display area and in contact with one end of the light emitting element and a second contact electrode disposed on the light emitting element in the display area and in contact with the other end of the light emitting element in prior art’s device in order to be able to operate the device by providing external connections to the device.
Regarding claim 14, in the combined device, the first conductive layer further includes a second signal line disposed in the display area, and the second contact electrode is electrically connected to the second signal line.
Regarding claim 15, Hong et al. teach in figure 24 and related text a second electrode in the display are, wherein the second conductive layer further includes a first conductive pattern 111 (e.g.) disposed to overlap the second signal line in the display area and connected to the second signal line through a second contact hole 61 penetrating through the buffer layer and the gate insulating film 60, the second electrode is in contact with the first conductive pattern, and the second contact electrode is in contact with the second electrode exposed by the first insulating layer.
Regarding claim 17, in the combined device, the first contact electrode, the second contact electrode, and the pad electrode are formed on the same layer 10.
Regarding claim 19, in the combined device, the first contact electrode and the pad electrode are formed on the same layer 10.
Regarding claim 20, in the combined device, sidewalls of the buffer layer and the first insulating layer defining the pad opening are aligned with each other.
Response to Arguments
Applicant’s arguments with respect to the claim(s) have been considered but are moot because of the new ground of rejection.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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O.N. /ORI NADAV/
3/21/2026 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800
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