DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/06/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8,13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al (US Patent No. 10211314).
With respect to claim 8, Hsu et al discloses a fin (14, Fig.5) over a semiconductor substrate (12); a gate stack overlying the fin (40,44,42,46,50); a spacer adjacent to the gate stack (26), the spacer comprising: a first spacer in physical contact with the gate stack (28,30); and a second spacer (36) in physical contact with both the first spacer and the gate stack (36’s lower edge contacts the top corner of the gate stack, top corner of the 50), the second spacer being a different material than the first spacer (Col3 states that layers 28 and 30 have the same material and both of them can be made from SiO2, and states that layer 36 is an etch stop layer made from SiCN); and a source/drain region adjacent to the spacer (32,34).
With respect to claim 13, Hsu et al discloses wherein both the first portion and the second portion have the "L" shape (Fig.5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al (US Pub No. 10211314), in view of Van Cleemput et al (US Pub No. 20180233398).
With respect to claim 14, Hsu et al does not explicitly disclose wherein the first spacer comprises a third portion and the third portion, the second portion, and the first portion have sidewalls aligned with each other. On the other hand, Van Cleemput et al discloses wherein the first spacer (305,307-311,309,Fig.3G) comprises a third portion (309) and the third portion, the second portion, and the first portion have sidewalls aligned with each other (Fig.3G). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Hsu et al according to the teachings of the Van Cleemput et al such that there would be a third portion, in order to improve the isolation of the first transistor from outside interference.
Claim(s) 15-17,20-23,26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Van Cleemput et al (US Pub No. 20180233398), in view of Hsu et al (US Pub No. 10211314).
With respect to claim 15, Van Cleemput et al discloses a first top spacer (313,Fig.3G) adjacent to the gate electrode stack (301);a first bottom spacer below the first top spacer (305); wherein both the first top spacer and the first bottom spacer are aligned with each other along a plane that is in physical contact with a single sidewall of the gate electrode stack (an imaginary plane extending in the y direction parallel and in contact with vertical side of the gate electrode, then portion of 313 which is in direct contact with 305 is vertically aligned with each other and they are along the imaginary plane), each of the first bottom spacer (the vertical portion of 305) and the first top spacer (vertical portion of the 313) comprising a sidewall that extends along the plane (along does not mean in physical contact since each of these elements extend in the vertical direction; therefore, they satisfy this element.
However, Van Cleemput does not explicitly disclose and a first source/drain region adjacent to the fin and isolated from the gate electrode stack by the first bottom spacer; a fin over a substrate; a gate electrode stack over the fin. On the other hand, Hsu et al discloses a fin (14,Fig.5) over a substrate (12); a gate electrode stack (46,50,40,44) over the fin; a first source/drain region (32) adjacent to the fin (Fig.5) and isolated from the gate electrode stack by the first bottom spacer (bottom portion of 28). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the art cited above according to the teachings of the Hsu et al such that such that the device is formed on the fin and has a source and drain in order to make a finfet device which has more capacity than classical transistors.
With respect to claim 16, Van Cleemput et al discloses, wherein the first top spacer comprises a multi-layer film (313,309) having an L-shape (in general, Fig.3G).
With respect to claim 17, Van Cleemput et al discloses wherein the first bottom spacer comprises a multi-layer film having a backwards L-shape ( it is a L shape and , and it is a backward L shape) .
With respect to claim 20, Van Cleemput et al discloses wherein the first top spacer comprises a first material (Para 55) and the first bottom spacer comprises a second material different from the first material (Para 54).
With respect to claim 21, Van Cleemput et al discloses; a first top spacer (313, Fig.3G) adjacent to the gate electrode stack (301); a first bottom spacer (305) adjacent to the gate electrode stack and between the substrate (303) and the first top spacer (Fig.3G), wherein the first top spacer (portion of 313 protruding downward which is between 309 and 305) and the first bottom spacer (portion of 305 in direct contact with 301) form a planar surface facing and in physical contact with (top corner) the gate electrode stack (the plane going in out in and out of the page between those portions of 313 and 305). However , the art cited above does not explicitly disclose fin over a substrate; a gate electrode stack over the fin; and a first source/drain region adjacent to the fin and isolated from the gate electrode stack by the first bottom spacer. On the other hand, Hsu e t al discloses a fin (14,Fig.5) over a substrate (12); a gate electrode stack (46,50,40,44) over the fin; a first source/drain region (32) adjacent to the fin (Fig.5) and isolated from the gate electrode stack by the first bottom spacer (bottom portion of 28). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the art cited above according to the teachings of the Hsu et al such that such that the device is formed on the fin and has a source and drain in order to make a finfet device which has more capacity than classical transistors.
With respect to claim 22, Van Cleemput et al discloses wherein the first bottom spacer is a multi- layer film having a backwards L-shape in a first cross-sectional view ( cross sectional view).
With respect to claim 23, Van Cleemput et al discloses wherein the first top spacer is a multi-layer film having an L-shape in a second cross-sectional view (from left side of the page).
With respect to claim 26, Van Cleemput et al disclsoes wherein the first top spacer comprises a first material (Para 54-55)and the first bottom spacer comprises a second material different from the first material (Para 54-55).
Response to Arguments
Applicant's arguments filed 03/06/2026 have been fully considered but they are not persuasive. Applicant argued against the finality of the previous office action. No new references were used, examiner was trying to explain his rejection better; therefore, the finality was appropriate. As far as applicant’s argument against the rejection of the claim 8; element 36 or the second spacer physically contacts the gate stack 50 because the lower side of the second spacer intersects the upper corners of the gate stack 50; therefore, it must be logically in contact with the gate stack 50. As far as the new amendments for the claim 15, each of the top spacer and the bottom spacer have vertical portions in 90 degrees angle which would by default extend along the plane which is in physical contact with a single sidewall of the gate. Also, along does no mean in physical contact. Furthermore, Van Cleemput et al discloses that the top space and the bottom spacer form a planar surface facing and physical contact with the top right corner of the gate stack.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm.
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/ALI NARAGHI/Primary Examiner, Art Unit 2817