DETAILED ACTION
This action is responsive to the amendment filed April 29, 2026. The amendment has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The prior drawing objections are withdrawn in view of the amended claims.
Claim Objections
Claims 15, 16, 18, 20, 23, and 24 are objected to because of the following informalities:
In claim 15, “a trench region within the semiconductor substrate on the first oxide layer” should be changed to -- a trench region within the semiconductor substrate and the first oxide layer --.
One does not form a trench “on” a material, a trench is formed in, within, into, or through a material. Reciting a trench is formed “on” a material is grammatically incorrect. A trench is defined as a long, narrow channel or depression, it involves removing the substance of the material itself. Therefore, the trench exists inside the volume of the material, not “on” the material.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The prior §112 rejections are withdrawn in view of the amended claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 24 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Clam 24 recites the chemical process includes an MAE etch. This is indefinite because an “MAE” etch is not defined in the claim or specification and is not a standardized etch process or known etch composition. It is unclear what is required or excluded by the claimed MAE etch. This could mean a variety of different things, e.g. metal assisted etching, mixed acid etchant, mean absolute error, etc. Even if one were to assume this means some mixture of acids, this composition is still unknown. For the purpose of examination, any etching is understood to meet the undefined “MAE etch”.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 15, 16, 18, 20, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chadda et al. (US 4,228,581) in view of Igel et al. (US 5,858,808), all of record.
(Re Claim 15) Chadda teaches a method of forming a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first conductivity type, and a first surface layer, disposed on the inner region, on a first side of the semiconductor substrate, and a second surface layer, disposed on the inner region, on a second side of the semiconductor substrate, opposite the first side, wherein the first surface layer and the second surface layer comprise a second conductivity type, opposite the first conductivity type, wherein the first surface layer and the inner region on the first side of the semiconductor substrate define a first p/n junction and the second surface layer and the inner region on the second side of the semiconductor substrate define a second p/n junction, and wherein the first surface layer and the second surface layer are formed in a single diffusion process that also forms a first oxide layer and a second oxide layer on the first surface layer and the second surface layer, respectively (see Fig. 2 and col 3, lines 23-38, wafer is P-N-P, formed in a single diffusion step which simultaneously forms a surface oxide);
removing a first surface portion of the semiconductor substrate, on the first side, wherein removing the first surface portion forms a trench region within the semiconductor substrate and the first oxide layer and the first surface layer that extends to at least a first depth of the first p/n junction and into the inner region (see Fig. 2 and col 3 line 23 - col 5 line 48, the oxide and surface portions are removed from each side to form trenches having a depth extending into the inner region 1);
wherein at least one mesa structure is formed within the semiconductor substrate on the first side (see Fig. 2).
Chadda is silent regarding using a saw and cleaning the first trench region using a chemical process, wherein the chemical process removes residual semiconductor debris and ion contamination in a surface of the trench region. A PHOSITA desiring to make, use, and improve upon Chadda’s process would be motivated to look to related art to teach possible improvements. Related art from Igel teaches the trenches (12) can be formed using a saw (col 3 lines 1-56) followed by a chemical clean (col 3 lines 51-56) rather than by etching. Using a saw is faster and easier than the processing required for the chemical etching (noting just the etching disclosed by Chadda takes up to 40 min, col 5 lines 46-48), which further involves forming an additional protective film on the oxide, and the use of slow wet chemistry, in addition having to carefully time the process to ensure the desired depth is reached. While the use of a saw is known to form rough/damaged surfaces, Igel mitigates these issues by using a chemical clean to provide a smooth surface after cutting with a saw. The saw can be easily set to a desired depth, avoiding the need to carefully test and time a wet etching process for a specific depth, and requires no additional protective layers. In view of Igel, a PHOSITA would find it obvious to quickly and easily form the trenches using a saw, followed by a cleaning step to remove any damage, debris, or ion contamination present, instead of using Chadda’s more involved and time consuming masking and wet etching processes. The silicon etching disclosed will remove any silicon debris from the saw and any ion contamination present on/in the surface of the trench in the silicon.
(Re Claim 16) wherein the trench region comprises a trench depth, and wherein the trench depth is greater than a thickness of the first oxide layer and the first surface layer combined (see Fig. 2, the trench depth extends into inner region 1 and is formed while the oxide from the diffusion process is still present, col 5 lines 46-48, as such even in the combination wherein sawing is used, the oxide is still beneficial and offers protection of the device faces of the mesas from contamination and damage).
(Re Claim 18) wherein the trench depth is at least two mils.
Chadda teaches the trenches extend into the inner region by up to 10 microns, col 5 lines 40-45, and shows the preliminary recesses 100 having a depth of up to 50 microns, col 5 lines 13-15, which are not the full thickness of layer 2 as shown in Fig. 1, and further has a surface oxide of several microns, col 3 lines 36-38, as well, thus the final trench depth in Fig. 2 is greater than 60 microns and is therefore at least 2 mils).
(Re Claim 20) wherein the trench region is arranged in a grid pattern that defines a plurality of mesas on the first side (see Fig. 2 and col 5 line 16 - col 6 line 26, the trenches symmetrically surround each device, also see Igel: see Figs. 4-7 and discussion in col 2 line 49 – col 4 line 15, conventional dicing using a saw is disclosed to make a plurality of mesa-shaped devices between a plurality of saw grooves extending across the wafer on opposite sides).
(Re Claim 23) wherein the first surface portion includes the first oxide layer and the first surface layer (Chadda removes the first surface portion including both the surface oxide and first surface layer 2/3, Fig. 2).
(Re Claim 24) wherein the chemical process includes an MAE etch.
See §112 rejection above. The MAE etch is undefined. Igel performs a silicon etch, understood to meet the unknown MAE etch.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant asserts the language regarding “a trench… on the first oxide layer” is correct. The Examiner respectfully disagrees. One does not form a trench “on” a material, a trench is formed in, within, into, or through a material. Reciting a trench is formed “on” a material is grammatically incorrect. A trench is defined as a long, narrow channel or depression, it involves removing the substance of the material itself. Therefore, the trench exists inside the volume of the material, not “on” the material. Applicant argues Igel does not teach the silicon etching would not remove residual semiconductor debris (understood to be silicon debris from the sawing) or ion contamination. The Examiner respectfully disagrees. The disclosed silicon etching will remove any silicon debris present from the sawing and will also etch the surface of the silicon, and any ion contamination present in or on the silicon surface will be removed when the silicon is etched whether expressly stated or not.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches various etching/cleaning processes and etchant compositions that can remove damage, contamination, debris, etc.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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