DETAILED ACTION
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 23, 2026, has been entered.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The prior objection to the specification is withdrawn in light of the amendments to the specification and drawings.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the removing a second surface portion of the semiconductor substrate on the second side, the second trench region, at least one additional mesa structure is formed within the semiconductor substrate on the second side, the second trench region are arranged in a grid pattern that defines a plurality of mesas on the…second side, the removing the second surface portion forms a second trench region within the semiconductor substrate on the second oxide layer and the second surface layer that extends to at least a second depth of the second p/n junction and into the inner region, and wherein the second trench region comprises a trench depth, and wherein the trench depth is greater than a first thickness of the first oxide layer and the first surface layer combined and a second thickness of the second oxide layer and the second surface layer combined must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next
Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 15-18 and 20-23 are objected to because of the following informalities:
In claim 15, “a first trench region within the semiconductor substrate on the first oxide layer” should be changed to -- a first trench region within the semiconductor substrate and the first oxide layer --.
This is similarly recited in claim 21 and the “on” should be changed to “and”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 17, 21, and 22 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 21 recites “wherein removing the second surface portion forms a second trench region within the semiconductor substrate on the second oxide layer and the second surface layer that extends to at least a second depth of the second p/n junction and into the inner region”, adding new matter. The originally filed specification provided no details with respect to the wherein removing the second surface portion forms a second trench region within the semiconductor substrate on the second oxide layer. The second trench is not shown and there is no discussion with respect to forming the second trench while second oxide layer is present.
Claim 22 recites “the second trench region comprises a trench depth, and wherein the trench depth is greater than a first thickness of the first oxide layer and the first surface layer combined and a second thickness of the second oxide layer and the second surface layer combined”, adding new matter. The originally filed specification provided no details with respect to the second trench region comprises a trench depth, and wherein the trench depth is greater than a first thickness of the first oxide layer and the first surface layer combined and a second thickness of the second oxide layer and the second surface layer combined. The second trench is not shown and there is no discussion with respect the second trench having a combined thickness the four layers as claimed.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-18 and 20-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 15 and 20 recite “the second trench region”, lacking antecedence.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 15, 16, 18, 20, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chadda et al. (US 4,228,581) in view of Igel et al. (US 5,858,808), all of record.
(Re Claim 15) Chadda teaches a method of forming a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate comprising an inner region of a first conductivity type, and a first surface layer, disposed on the inner region, on a first side of the semiconductor substrate, and a second surface layer, disposed on the inner region, on a second side of the semiconductor substrate, opposite the first side, wherein the first surface layer and the second surface layer comprise a second conductivity type, opposite the first conductivity type, wherein the first surface layer and the inner region on the first side of the semiconductor substrate define a first p/n junction and the second surface layer and the inner region on the second side of the semiconductor substrate define a second p/n junction, and wherein the first surface layer and the second surface layer are formed in a single diffusion process that also forms a first oxide layer and a second oxide layer on the first surface layer and the second surface layer, respectively (see Fig. 2 and col 3, lines 23-38, wafer is P-N-P, formed in a single diffusion step which simultaneously forms a surface oxide);
removing a first surface portion of the semiconductor substrate, on the first side, and removing a second surface portion of the semiconductor substrate on the second side, wherein removing the first surface portion forms a first trench region within the semiconductor substrate and the first oxide layer and the first surface layer that extends to at least a first depth of the first p/n junction and into the inner region (see Fig. 2 and col 3 line 23 - col 5 line 48, the oxide and surface portions are removed from each side to form trenches having a depth extending into the inner region 1);
wherein at least one mesa structure is formed within the semiconductor substrate on the first side, and at least one additional mesa structure is formed within the semiconductor substrate on the second side (see Fig. 2).
Chadda is silent regarding using a saw and cleaning the first trench region and the second trench region using a chemical process. A PHOSITA desiring to make, use, and improve upon Chadda’s process would be motivated to look to related art to teach possible improvements. Related art from Igel teaches the trenches (12) can be formed using a saw (col 3 lines 1-56) followed by a chemical clean (col 3 lines 51-56) rather than by etching. Using a saw is faster and easier than the processing required for the chemical etching (noting just the etching disclosed by Chadda takes up to 40 min, col 5 lines 46-48), which further involves forming an additional protective film on the oxide, and the use of dangerous wet chemistry, in addition having to carefully time the process to ensure the desired depth is reached. While the use of a saw is known to form rough/damaged surfaces, Igel mitigates these issues by using a chemical clean to provide a smooth surface after cutting with a saw. The saw can be easily set to a desired depth, avoiding the need to carefully test and time a wet etching process for a specific depth, and requires no additional protective layers. In view of Igel, a PHOSITA would find it obvious to quickly and easily form the trenches using a saw, followed by a cleaning step to remove damage and debris from the saw, instead of using Chadda’s more involved and time consuming masking and wet etching processes.
(Re Claim 16) wherein the first trench region comprises a trench depth, and wherein the trench depth is greater than a first thickness of the first oxide layer and the first the first surface layer combined (see Fig. 2, the trench depth extends into inner region 1 and is formed while the oxide from the diffusion process is still present, col 5 lines 46-48, as such even in the combination wherein sawing is used, the oxide is still beneficial and offers protection of the device faces of the mesas from contamination and damage).
(Re Claim 18) wherein the trench depth is at least two mils.
Chadda teaches the trenches extend into the inner region by up to 10 microns, col 5 lines 40-45, and shows the preliminary recesses 100 having a depth of up to 50 microns, col 5 lines 13-15, which are not the full thickness of layer 2 as shown in Fig. 1, and further has a surface oxide of several microns, col 3 lines 36-38, as well, thus the final trench depth in Fig. 2 is greater than 60 microns and is therefore at least 2 mils).
(Re Claim 20) wherein the first trench region and the second trench region are arranged in a grid pattern that defines a plurality of mesas on the first side and on the second side (see Fig. 2 and col 5 line 16 - col 6 line 26, the trenches symmetrically surround each device, also see Igel: see Figs. 4-7 and discussion in col 2 line 49 – col 4 line 15, conventional dicing using a saw is disclosed to make a plurality of mesa-shaped devices between a plurality of saw grooves extending across the wafer on opposite sides).
(Re Claim 23) wherein the first surface portion includes the first oxide layer and the first surface layer (Chadda removes the first surface portion including both the surface oxide and first surface layer 2/3, Fig. 2).
Response to Arguments
Applicant’s arguments have been considered but are moot in view of the new grounds of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches oxidation, passivation, diffusion, forming trenches to different depths, and dicing mesa shaped vertical PN junction devices.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
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/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898