Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed 9/24/2025 have been entered and considered. The amendment to claim 1 and the new claims 24-27 are acknowledged.
Response to Arguments
Applicant's arguments filed 9/24/2025 have been fully considered but they are not persuasive. Applicant asserts that an underfill layer and a dielectric layer are different kinds of structure. The examiner disagrees because an underfill is a dielectric layer that is formed after the bonding of devices. The examiner understands that the usage of the term “underfill layer” is attached to an underfill process as disclosed in applicant’s disclosure in paragraph 0048. Unless the process of forming the dielectric layer implies a structural difference, limitations regarding the formation of the dielectric layer have no patentable weight.
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 22 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “An IC packaging structure, comprising:a substrate with a passivation layer covering a first surface of the substrate, wherein a plurality of holes are formed in the passivation layer; a plurality of solder balls respectively accommodated in the plurality of holes; a semiconductor chip with a first plurality of pads, wherein a plurality of copper pillar micro-bumps respectively extend from the first plurality of pads; and a dielectric layer covering a first surface of the semiconductor chip, wherein a plurality of holes are formed in the dielectric layer and corresponding to the first plurality of pads, the dielectric layer has a top surface contacting the passivation layer, wherein the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls, the passivation layer is spaced apart from the plurality of copper pillar micro-bumps.“ need not be formed by the process of “there is no underfill layer between the dielectric layer and the passivation layer”. An underfill layer is inherently associated with a particularly manufacturing step, namely underfilling. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Claims 22 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Suzuki et al. US 20110316149 Ai (hereinafter referred to as Suzuki).
Regarding claim 22, Suzuki teaches
An IC packaging structure (“first specific example of the electronic component mounting method”, para. 0059 FIG. 1e), comprising:
a substrate (“wiring substrate 1” para. 0059 FIG. 1e) with a passivation layer (“resist patterns 3” para. 0059 FIG. 1e) covering a first surface of the substrate (surface of “wiring substrate 1” facing “chip substrate 5”), wherein a plurality of holes (gaps in “resist patterns 3” where “electrode terminal 2” are formed) are formed in the passivation layer;
a plurality of solder balls (“solder bumps 4” para. 0059 FIG. 1e) respectively accommodated in the plurality of holes;
a semiconductor chip (“chip substrate 5” para. 0059 FIG. 1e) with a first plurality of pads (“electrode terminals 7” para. 0059 FIG. 1e), wherein a plurality of copper pillar micro-bumps (“Copper pillars 8” para. 0059 FIG. 1e) respectively extend from the first plurality of pads; and
a dielectric layer (“underfill 10” para. 0059 FIG. 1e) covering a first surface of the semiconductor chip (surface of “chip substrate 5” facing “wiring substrate 1”), wherein a plurality of holes (the spaces occupied by “copper pillars 8” and overlapping the “electrode terminals 7”) are formed in the dielectric layer and corresponding to the first plurality of pads, the dielectric layer has a top surface contacting the passivation layer (the “underfill 10” contacts a top surface of “resist patterns 3”),
wherein the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls (“copper pillars 8 are joined with the solder bumps 4” para. 0059 FIG. 1e), and the passivation layer is spaced apart from the plurality of copper pillar micro-bumps (“copper pillars 58” remain a certain distance away from “resist patterns 3” as seen in FIG. 1e).
However, Suzuki fails to expressly teach and there is no underfill layer between the dielectric layer and the passivation layer.
Nevertheless, underfill is a dielectric layer formed after bonding. The examiner understands it is a dielectric structure inherently associated with a particularly manufacturing step as disclosed in paragraph 0048 in applicant’s disclosure. The finished structure in Suzuki teaches the dielectric layer covering the semiconductor chip whether it was formed prior to or after bonding with the substrate. As such, the limitation “there is no underfill layer between the dielectric layer and the passivation layer” holds no patentable weight.
Regarding claim 23, Suzuki further teaches wherein the passivation layer extends from one edge of the first surface of the substrate to another edge of the first surface of the substrate (“resist patterns 3” extend from left edge of “wiring substrate 1” to the right edge as seen in FIG. 1e).
Claims 22-23, and 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. US 20220271018 A1 (hereinafter referred to as Chen), in view of Meyer et al. US 20140306355 A1 (hereinafter referred to as Meyer).
Claim 22 is a product-by-process claim. A product-by-process claim is a product claim. Applicant has merely chosen to define the claimed product by the process by which it was made. It has been well established that process limitations do not impart patentability to an old/obvious product. Process limitations are significant only to the extent that they distinguish the claimed product over the prior art product. Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir.1985). In this case, the claimed “An IC packaging structure, comprising:a substrate with a passivation layer covering a first surface of the substrate, wherein a plurality of holes are formed in the passivation layer; a plurality of solder balls respectively accommodated in the plurality of holes; a semiconductor chip with a first plurality of pads, wherein a plurality of copper pillar micro-bumps respectively extend from the first plurality of pads; and a dielectric layer covering a first surface of the semiconductor chip, wherein a plurality of holes are formed in the dielectric layer and corresponding to the first plurality of pads, the dielectric layer has a top surface contacting the passivation layer, wherein the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls, the passivation layer is spaced apart from the plurality of copper pillar micro-bumps.“ need not be formed by the process of “there is no underfill layer between the dielectric layer and the passivation layer”. An underfill layer is inherently associated with a particularly manufacturing step, namely underfilling. Once the Examiner provides a rationale tending to show that the claimed product appears to be the same or similar to that of the prior art, although produced by a different process, the burden shifts to applicant to come forward with evidence establishing an unobvious difference between the claimed product and the prior art product. In re Marosi, 710 F.2d 798, 802, 218 USPQ 289, 292 (Fed. Cir.1983).
Regarding claim 22, Chen teaches
An IC packaging structure (“double-layer stacked 3D fan-out packaging structure” para. 0039 FIG. 2-16), comprising:
a substrate (structure comprising “first rewiring layer 16”, “first semiconductor chip 14”, and “packaging material layer 15”, para. 0052-0053 FIG. 16) with a passivation layer (“second wiring dielectric layer 121” para. 0084) covering a first surface of the substrate, wherein a plurality of holes are formed in the passivation layer (“etched window 123” as seen in FIG. 13-16, para. 0069);
a plurality of solder balls (“solder ball 193” para. 0069) respectively accommodated in the plurality of holes (“etched window 123” are in the “etched windows 123”, para. 0069);
a semiconductor chip (“second semiconductor chip 19” para. 0069) with a first plurality of pads (“contact pads 191” para. 0069), wherein a plurality of pillar micro-bumps (“metal pillar 192”, para. 0069) respectively extend from the first plurality of pads; and
a dielectric layer (“underfill layer 20” para. 0070) covering a first surface of the semiconductor chip, wherein a plurality of holes are formed in the dielectric layer and corresponding to the first plurality of pads (the openings above “contact pads 191” in which “metal pillars 192” are disposed correspond to holes in “underfill layer 20”), the dielectric layer has a top surface contacting the passivation layer (“underfill layer 20” contacts “second wiring dielectric layer 121”),
wherein the plurality of pillar micro-bumps are respectively connected to the plurality of solder balls (“One end of the metal pillar 192 is connected to the contact pad 191, the other end is connected to the solder ball 193” para. 0069), wherein the dielectric layer directly contacts the passivation layer (“underfill layer 20” contacts “second wiring dielectric layer 121”),
and the passivation layer is spaced apart from the plurality of copper pillar micro-bumps (“second wiring dielectric layer 121” and “metal pillars 192” are shown as being spaced apart in FIG. 16),
However, Chen fails to teach copper pillar micro-bumps, and there is no underfill layer between the dielectric layer and the passivation layer.
Nevertheless, underfill is a dielectric layer formed after bonding. The examiner understands it is a dielectric structure inherently associated with a particularly manufacturing step as disclosed in paragraph 0048 in applicant’s disclosure. The finished structure in FIG. 16 of Chen teaches the dielectric layer covering the semiconductor chip whether it was formed prior to or after bonding with the substrate. As such, the limitation there is no underfill layer between the dielectric layer and the passivation layer holds no patentable weight.
However, Chen fails to teach copper pillar micro-bumps.
Nevertheless, Meyer teaches
copper pillar micro-bumps (“first and second interconnects 304-1 and 304-2” may consist of copper, para. 0107 FIG. 3).
Main and Meyer teach interconnections between a substrate and a chip using metal pillars. The “first and second interconnects 304-1 and 304-2” can consist of copper or other metals. The “metal pillars 192” in MAIN are of unspecified material. Copper is a well-known material used throughout the art, as further seen in para. 0100 of Hurwitz et al. US 20140363927 A1 and para. 0021 of Bhaktar et al. US 20150187714 A1. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “metal pillars 192” can be made of the known suitable material that is copper.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the IC packaging structure in MAIN with the copper pillar micro-bumps as taught in Meyer. Copper is a well-known material suitable for use as a metal pillar interconnect.
Regarding claim 23, Chen, modified by Meyer, teaches the IC packaging structure of claim 22, wherein the passivation layer extends from one edge of the first surface of the substrate to another edge of the first surface of the substrate (“second wiring dielectric layer 121” extends from one edge of the substrate structure to the other as seen in FIG. 16).
Regarding claim 26, Chen, modified by Meyer, teaches the IC packaging structure of claim 22, wherein a portion of one copper pillar micro-bump remote from the first surface of the substrate extends into a corresponding hole of the plurality of holes in the passivation layer (at least a portion of “metal pillar 192” extends into the “etched window 123” as seen in FIG. 16).
Regarding claim 27, Chen, modified by Meyer, teaches the IC packaging structure of claim 22, wherein a diameter of one copper pillar micro-bump is smaller than that of a corresponding hole of the plurality of holes in the passivation layer (as seen in FIG. 16, parts of “underfill layer 20” are between the “metal pillars 192” and sidewalls of “etched windows 123”).
Allowable Subject Matter
Claims 24 and 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 24, the most relevant prior art Chen teaches a dielectric layer on the semiconductor chip that fills gaps between the solder balls, the pillar micro-bumps, and sidewalls of the holes in the passivation layer. Because of this, portions of the top surface of the dielectric layer extend along the side of the solder balls. As such, Chen fails to teach wherein all of the plurality of solder balls is between the top surface of the dielectric layer and the substrate. Claim 24 is considered to contain allowable subject matter.
Regarding claim 25, the most relevant prior art Chen teaches the plurality of copper pillar micro- bumps protrude beyond a surface of the dielectric layer to connect to the plurality of solder balls. However, Chen fails to teach wherein a top of the solder balls are at the same level as a surface of the passivation layer. Therefore, claim 25 is considered to contain allowable subject matter.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898