DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant' s amendments filed 4/24/2026 have been entered and considered. The amendment to claims 22 is acknowledged.
The indicated allowability of claim 28 is withdrawn in view of the newly discovered reference(s) to Wang et al. US 20230238346 A1. Rejections based on the newly cited reference(s) follow.
Response to Arguments
Applicant’s arguments with respect to claim(s) 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments with respect to the rejections under 35 U.S.C. 112(a) have been fully considered and are persuasive. The rejections under 112(a) of claims28-31 have been withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 22-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. US 20200365550 A1 (hereinafter referred to as Yu).
Regarding claim 22, Yu teaches
An IC packaging structure (“semiconductor package 300” para. 0015 FIG. 1), comprising:
a substrate (“substrate 202” with “interconnect structure 206” on top, para. 0031) with a passivation layer covering a first surface of the substrate (“passivation layer 212” para. 0031), wherein a plurality of holes are formed in the passivation layer (“opening 216” para. 0031. Though only one “opening 216” is shown, the examiner understands that a die will comprise multiple openings such as the “cavities 716A-716D” in the “package 750” in para. 0067-0068 FIG. 5.);
a plurality of solder balls (“solder layer 126” shown in FIG. 1H para. 0025) respectively accommodated in the plurality of holes;
a semiconductor chip (“semiconductor die 100” para. 0015) with a first plurality of pads (“topmost metallization pattern 108” in FIG. 1H, para. 0018. Though only one “topmost metallization pattern 108” is shown, the examiner understands that a die will comprise multiple pads is in “package 750”.), wherein a plurality of copper pillar micro-bumps (“pads 114” made of copper para. 0019 FIG. 1C-1H) respectively extend from the first plurality of pads; and
a dielectric layer (“passivation film 112” para. 0020) covering a first surface of the semiconductor chip, wherein a plurality of holes are formed in the dielectric layer and corresponding to the first plurality of pads (“pads 114” are disposed within “passivation film 112”), the dielectric layer has a top surface contacting the passivation layer (“passivation layer 112” is in direct contact with “passivation layer 212”, para. 0032),
wherein the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls (“solder layer 126” is electrically connected to “pad 114” through “UBM 128A”, para. 0023-0027),
wherein the dielectric layer directly contacts the passivation layer (“passivation layer 112” is in direct contact with “passivation layer 212”, para. 0032), an edge of the dielectric layer is aligned with an edge of the passivation layer in a vertical direction (“die 100” and “die 200” are shown as having aligned side surfaces and “passivation layer 112” and “passivation layer 212”. Furthermore, “die 100” and “die 200” may be singulated after bonding separate wafers, para. 0016, such that their lateral dimensions are the same.), and there is no underfill layer between the dielectric layer and the passivation layer (there is no underfill between “passivation layer 112” and “passivation layer 212”),
and the passivation layer is spaced apart from the plurality of copper pillar micro-bumps (“pad 114” is laterally spaced apart from “passivation layer 212”);
wherein all of the plurality of solder balls is between the top surface of the dielectric layer and the substrate (“solder layer 126” is between “passivation layer 112” of “die 100” and “interconnect structures 206” layer on “substrate 202”).
Regarding claim 23, Yu teaches the IC packaging structure of claim 22, wherein the passivation layer extends from one edge of the first surface of the substrate to another edge of the first surface of the substrate (“passivation layer 212” is shown as extending from one end of “die 200” to the other.)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 26-31 are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 22, in view of Wang et al. US 20230238346 A1 (hereinafter referred to as Wang).
Regarding claim 26, Yu teaches the IC packaging structure of claim 22 but fails to teach wherein a portion of one copper pillar micro-bump remote from the first surface of the substrate extends into a corresponding hole of the plurality of holes in the passivation layer.
However, Wang teaches an “electrical connection column 120” that protrudes from “first face 100” of “passivation layer 111” such that the protrusion is located in the “first groove 160” and “second groove 170” in a “second base 140” (para. 0016 and 0018 FIG. 1 and 9). The “conductive body of the “electrical connection column 120” comprises copper (para. 0026). The grooves are filed by the “electrical connection column 120” and “welded structure 180” (para. 0016). By filling the grooves with “welded structure 180” around “electrical connection column 120”, the connection between “first base 110” and “second base 120” can be tightened (para. 0022). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having “pads 114” in Yu protruding as in Wang and filling the remaining cavity with solder to form a “welded structure 180” will produce a tighter connection between “die 100” and “die 200”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaging structure in Yu with the extended copper pillar micro-bump taught in Wang. When the copper pillar micro-bump extends into a hole of the passivation layer and the solder fills the remainder of the hole, the connection between the substrate and the semiconductor die is tightened.
Regarding claim 27, Yu teaches the IC packaging structure of claim 22 but fails to teach wherein a diameter of one copper pillar micro-bump is smaller than that of a corresponding hole of the plurality of holes in the passivation layer.
Nevertheless, Wang teaches an “electrical connection column 120” that protrudes from “first face 100” of “passivation layer 111” such that the protrusion is located in the “first groove 160” and “second groove 170” in a “second base 140” (para. 0016 and 0018 FIG. 1 and 9). The “conductive body of the “electrical connection column 120” comprises copper (para. 0026). The grooves are filed by the “electrical connection column 120” and “welded structure 180” (para. 0016). By filling the grooves with “welded structure 180” around “electrical connection column 120”, the connection between “first base 110” and “second base 120” can be tightened (para. 0022). Because “electrical connection column 120” fits into “first and second grooves 160 and 170” and is laterally surrounded by “welded structure 180”, it is understood that the diameter of “electrical connection column 120” is less than the diameter of “first and second grooves 160 and 170”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having “pads 114” in Yu protruding as in Wang and filling the remaining hole with solder to form a “welded structure 180” will produce a tighter connection between “die 100” and “die 200”. This is possible when the diameter of “pads 114” are less than the “openings 216”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaging structure in Yu with the extended copper pillar micro-bumps taught in Wang. When the copper pillar micro-bumps have a smaller diameter than that of their corresponding hole, they can extend into the hole of the passivation layer. In this manner, the solder fills the remainder of each hole, producing a tighter connection between the substrate and the semiconductor die.
Regarding claim 28, Yu teaches
An IC packaging structure (“semiconductor package 300” para. 0015 FIG. 1), comprising:
a substrate (“substrate 202” with “interconnect structure 206” on top, para. 0031) with a passivation layer covering a first surface of the substrate (“passivation layer 212” para. 0031), wherein a plurality of holes are formed in the passivation layer (“opening 216” para. 0031. Though only one “opening 216” is shown, the examiner understands that a die will comprise multiple openings such as the “cavities 716A-716D” in the “package 750” in para. 0067-0068 FIG. 5.);
a plurality of solder balls (“solder layer 126” shown in FIG. 1H para. 0025) respectively accommodated in the plurality of holes;
a semiconductor chip (“semiconductor die 100” para. 0015) with a first plurality of pads (“topmost metallization pattern 108” in FIG. 1H, para. 0018. Though only one “topmost metallization pattern 108” is shown, the examiner understands that a die will comprise multiple pads is in “package 750”.), wherein a plurality of copper pillar micro-bumps (“pads 114” made of copper para. 0019 FIG. 1C-1H) respectively extend from the first plurality of pads; and
a dielectric layer (“passivation film 112” para. 0020) covering a first surface of the semiconductor chip, wherein a plurality of holes are formed in the dielectric layer and corresponding to the first plurality of pads (“pads 114” are disposed within “passivation film 112”), the dielectric layer has a top surface contacting the passivation layer (“passivation layer 112” is in direct contact with “passivation layer 212”, para. 0032),
wherein the plurality of copper pillar micro-bumps are respectively connected to the plurality of solder balls (“solder layer 126” is electrically connected to “pad 114” through “UBM 128A”, para. 0023-0027),
wherein the dielectric layer directly contacts the passivation layer (“passivation layer 112” is in direct contact with “passivation layer 212”, para. 0032), and there is no underfill layer between the dielectric layer and the passivation layer (there is no underfill between “passivation layer 112” and “passivation layer 212”),
and the passivation layer is spaced apart from the plurality of copper pillar micro-bumps (“pad 114” is laterally spaced apart from “passivation layer 212”);
However, Yu fails to teach wherein a top of the solder balls are at the same level as a surface of the passivation layer, and the plurality of copper pillar micro-bumps protrude beyond a surface of the dielectric layer to connect to the plurality of solder balls.
Nevertheless, Wang teaches
However, Wang teaches an “electrical connection column 120” that protrudes from “first face 100” of “passivation layer 111” such that the protrusion is located in the “first groove 160” and “second groove 170” in a “second base 140” (para. 0016 and 0018 FIG. 1 and 9). The “conductive body of the “electrical connection column 120” comprises copper (para. 0026). “Welded structure 180” is at a level of the sidewalls of “first groove 160” and “second groove 170”. Furthermore, from “The first groove 160 and the second groove 170 are filled up by the welded structure 180” in para. 0037, the examiner understands that “welded structure 180” is at substantially the same level as the top surface of “second base 140”. By filling the grooves with “welded structure 180” around “electrical connection column 120”, the connection between “first base 110” and “second base 120” can be tightened (para. 0022). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that having “pads 114” in Yu protruding as in Wang and filling the remaining cavity with solder to form a “welded structure 180” will produce a tighter connection between “die 100” and “die 200”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the packaging structure in Yu with the extended copper pillar micro-bump taught in Wang. When the copper pillar micro-bump extends into a hole of the passivation layer and the solder fills the remainder of the hole, the connection between the substrate and the semiconductor die is tightened.
Regarding claim 29, Yu, modified by Wang, teaches the IC packaging structure of claim 28, wherein the passivation layer extends from one edge of the first surface of the substrate to another edge of the first surface of the substrate (“passivation layer 212” is shown as extending from one end of “die 200” to the other.).
Regarding claim 30, Yu, modified by Wang, teaches the IC packaging structure of claim 28, wherein a portion of one copper pillar micro-bump remote from the first surface of the substrate extends into a corresponding hole of the plurality of holes in the passivation layer (as modified, “pad 114” extends beyond “passivation layer 112” into “opening 216”).
Regarding claim 31, Yu, modified by Wang, teaches the IC packaging structure of claim 28, wherein a diameter of one copper pillar micro-bump is smaller than that of a corresponding hole of the plurality of holes in the passivation layer (Because “electrical connection column 120” in Wang fits into “first and second grooves 160 and 170” and is laterally surrounded by “welded structure 180”, it is understood that the diameter of “electrical connection column 120” is less than the diameter of “first and second grooves 160 and 170”. As modified, “pads 114” have a smaller diameter than “openings 216” so they can fit and have “solder layer 126” surround the protruding “pads 114”.).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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