Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/16/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 14, and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park) in view of Huang et al. (U.S. 2020/0203300 A1, hereinafter refer to Huang), Yu et al. (U.S. 2014/0001644 A1, hereinafter refer to Yu), and Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa).
Regarding Claim 1: Park discloses a semiconductor structure (see Park, Figs.12-13 and 16 as shown below and ¶ [0002]) comprising:
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a package (200/31/302/303) comprising bonding pads (215) (see Park, Figs.12-13 and 16 as shown above);
a substrate package (100) (see Park, Figs.12-13 and 16 as shown above) comprising:
a core (110) including through-core vias (115) (see Park, Figs.12-13 and 16 as shown above);
a chip-side insulating layer (120) on the core (110) (see Park, Figs.12-13 and 16 as shown above);
chip-side wiring interconnects (125) in the chip-side insulating layer (120) (see Park, Figs.12-13 and 16 as shown above);
chip-side bonding pads (135) on an upper surface of the chip-side insulating layer (120) and electrically connected to the chip-side wiring interconnects (125) (see Park, Figs.12-13 and 16 as shown above);
a solder mask (130) deposited over the chip-side bonding pads (135) (see Park, Figs.12-13 and 16 as shown above); and
at least one substrate trench (130-O21/022) formed in the solder mask (130), and wherein a chip-side wiring interconnect (125) of the chip-side wiring interconnects (125) is above a through-core via (115) of the through-core vias (115) in a first direction, and adjacent an inner sidewall of the at least one substrate trench (130-O21/022) in a second direction perpendicular to the first direction (see Park, Figs.12-13 and 16 as shown above);
solder material portions (20) bonded to the chip-side bonding pads (125) and the bonding pads (215) (see Park, Figs.12-13 and 16 as shown above); and
a second underfill material portion (25) laterally surrounding the solder material portions (20) (see Park, Figs.12-13 and 16 as shown above),
wherein the at least one substrate trench (130-O21/022) is laterally aligned with a sidewall of a molding compound die frame (500) of the package (see Park, Figs.12-13 and 16 as shown above).
Park is silent upon explicitly disclosing wherein a portion of the second underfill material portion is disposed within the at least one substrate trench and in contact with the sidewall of the molding compound die frame.
For support see Huang, which teaches wherein a portion of the second underfill material portion (210) is disposed within the at least one substrate trench (192a) and in contact with the sidewall of the molding compound die frame (150) (see Huang, Fig.2A as shown below and ¶ [0003]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Huang to enable the Park’s portion of the second underfill material portion disposed within the at least one substrate trench to be in contact with the sidewall of the molding compound die frame as taught by Huang in order to obtain a reliable packages with electronic components with high integration density.
The combination of Park and Huang is silent upon explicitly disclosing wherein an outer periphery of the second underfill material portion is located between the inner sidewall of the at least one substrate trench formed in the solder mask and an outer sidewall of the at least one substrate trench formed in the solder mask.
For support see Yu, which teaches wherein an outer periphery of the second underfill material portion (147) is located between the inner sidewall of the at least one substrate trench (142) formed in the solder mask (140) and an outer sidewall of the at least one substrate trench (142) formed in the solder mask (140) (see Yu, Figs.5-6 as shown below and ¶ [0018]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Huang, and Yu to enable an outer periphery of the second underfill material portion to be located between the inner sidewall of the at least one substrate trench to be formed in the solder mask and an outer sidewall of the at least one substrate trench to be formed in the solder mask as taught by Yu in order to improve packaging yield.
The combination of Park, Huang, and Yu is silent upon explicitly disclosing wherein at least one substrate trench formed in the solder mask and the chip-side insulating layer, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layer,
a second underfill material portion laterally surrounding the solder material portions and contacting the bottom surface of the at least one substrate trench.
For support see Matsuzawa, which teaches wherein at least one substrate trench (120) formed in the solder mask (15) and the chip-side insulating layer (13), wherein the at least one substrate trench (120) includes a bottom surface in the chip-side insulating layer (13) (see Matsuzawa, Fig.10 as shown below and ¶ [0088]),
a second underfill material portion (60) laterally surrounding the solder material portions (33) and contacting the bottom surface of the at least one substrate trench (120) (see Matsuzawa, Fig.10 as shown below and ¶ [0088]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Huang, Yu, and Matsuzawa to enable the combination of Park’s, Huang’s, and Yu’s at least one substrate trench to be formed in the solder mask and the chip-side insulating layer, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layer and the second underfill material portion laterally surrounding the solder material portions and contacting the bottom surface of the at least one substrate trench as taught by Matsuzawa in order to reduces voids remaining in the at least one substrate trench and improve the reliability of the electronic component.
Regarding Claim 2: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the inner sidewall and the outer sidewall are equidistant to each other throughout the at least one substrate trench (120) (see Matsuzawa, Fig.10 as shown above).
Regarding Claim 3: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein a lateral distance (W1) between the outer periphery of the second underfill material portion (147) and a proximal sidewall of the package (200) is within a range of 500 microns to 1100 microns (see Yu, Figs.3A-3B and ¶ [0017]).
Regarding Claim 4: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein a lateral distance (D1) between the inner sidewall of the at least one substrate trench (142) and a proximal edge of a solder material portion (132) of the solder material portions (132) is within a range of 100 microns to 300 microns (see Yu, Figs.5-6 as shown above and ¶ [0021]).
Regarding Claim 5: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the at least one substrate trench (142) has a depth (T1) that is within a range of 10 microns to 100 microns (see Yu, Figs.5-6 as shown above and ¶ [0011]), and
the chip- side insulating layer (13) comprises a photosensitive epoxy compound (note: liquid or paste of an epoxy resin is known as a photosensitive epoxy resin) (see Matsuzawa, Fig.10 as shown above, ¶ [0066], and ¶ [0070]).
Regarding Claim 6: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein a stabilization structure (400) attached to an upper surface of the molding compound die frame (500) of the package (see Park, Figs.12-13 and 16 as shown above).
The combination of Park, Huang, Yu, and Matsuzawa is silent upon explicitly disclosing wherein the stabilization structure has a width equal to a width of the molding compound die frame.
However, it would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of stabilization structure with respect to the width of molding compound die frame through routine experimentation and optimization to obtain optimal or desired device performance because the width of stabilization structure with respect to the width of molding compound die frame is a result-effective variable and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Regarding Claim 7: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the inner sidewall of the at least one substrate trench (120) is located inside a periphery of an area of the package in a plan view (see Matsuzawa, Fig.10B as shown above),
the substrate package (100) further comprises a metal layer on an upper surface of the core (110) and contacting the through-core via (115), and the inner sidewall of the at least one substrate trench (130-O21/022) is above the metal layer in the first direction (see Park, Figs.12-13 and 16 as shown above).
Regarding Claim 8: Park as modified teaches a semiconductor structure as set forth in claim 7 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the outer sidewall of the at least one substrate trench (192a) is located inside the periphery of the area of the package (100/110) in a plan view (see Huang, Fig.2B as shown above).
Regarding Claim 9: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the package (200/301/302/303) comprises at least one semiconductor die (301/302/303), a redistribution structure (200) comprising the bonding pads (215), and a first underfill material portion (35) located between the at least one semiconductor die (301/302/303) and the redistribution structure (200) (see Park, Figs.12-13 and 16 as shown above).
Regarding Claim 10: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein: the inner sidewall of the at least one substrate trench (142) comprises a frame-shaped inner sidewall and the outer sidewall of the at least one substrate trench (142) comprises a frame-shaped outer sidewall that laterally surrounds the frame-shaped inner sidewall (see Yu, Fig.5B as shown above), and
the frame-shaped inner sidewall laterally surrounds the solder material portions (see Yu, Fig.5B as shown above).
Regarding Claim 11: Park as modified teaches a semiconductor structure as set forth in claim 10 as above. The combination of Park, Huang, Yu, and Matsuzawa is silent upon explicitly disclosing wherein the frame-shaped inner sidewall and the frame-shaped outer sidewall have rounded corners in a plan view proximate to corner regions of the package.
However, the combination of Park, Huang, Yu, and Matsuzawa teaches wherein the frame-shaped inner sidewall and the frame-shaped outer sidewall have corners in a plan view proximate to corner regions of the package (see Yu, Fig.5B as shown above).
Hence, the configuration of the claimed at least one substrate trench was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed at least one substrate trench was significant.
Regarding Claim 12: Park as modified teaches a semiconductor structure as set forth in claim 1 as above. The combination of Park, Huang, Yu, and Matsuzawa further teaches wherein the at least one substrate trench comprises a plurality of L-shaped substrate trenches (192a) in a plan view proximate to corner regions of the package (100/110) (see Huang, Fig.2B as shown above), and
the chip-side wiring interconnect (125) is between the through-core via (115) and the package (200/301/302/303) in the first direction (see Park, Figs.12-13 as shown above).
Claim(s) 13 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park), Huang et al. (U.S. 2020/0203300 A1, hereinafter refer to Huang), Yu et al. (U.S. 2014/0001644 A1, hereinafter refer to Yu), and Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa) as applied to claim 1, and further in view of Chou (U.S. 2016/0315028 A1, hereinafter refer to Chou).
Regarding Claim 13: Park as modified teaches a semiconductor structure as applied to claim 1 above. The combination of Park, Huang, Yu, and Matsuzawa is silent upon explicitly disclosing wherein the at least one substrate trench comprises a plurality of rectangular substrate trenches in a plan view located adjacent to corner regions of the package, wherein the plurality of rectangular substrate trenches have inner sidewalls that are parallel to proximal sidewalls of the package in a plan view.
For support see Chou, which teaches wherein the at least one substrate trench (128) comprises a plurality of rectangular substrate trenches (128) in a plan view located adjacent to corner regions of the package (140), wherein the plurality of rectangular substrate trenches (128) have inner sidewalls that are parallel to proximal sidewalls of the package (140) in a plan view (see Chou, Figs.1- 2D and ¶ [0030]- ¶ [0035]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Huang, Yu, Matsuzawa, and Chou to enable the known plan view configuration of substrate trench as taught by Chou in order to effectively reducing the chance for the underfill to overflow to the first conductive bumps.
Claim(s) 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park) in view of Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa).
Regarding Claim 14: Park discloses a substrate package (see Park, Figs.12-13 and 16 as shown above and ¶ [0002]) comprising:
a core (110) including through-core vias (115) (see Park, Figs.12-13 as shown above); and
a chip-side surface laminar circuit (SLC) (120/125) (see Park, Figs.12-13 as shown above), comprising:
chip-side insulating layers (120) on the core (110) (see Park, Figs.12-13 as shown above);
chip-side wiring interconnects embedded within the chip-side insulating layers (120) (see Park, Figs.12-13 as shown above); and
chip-side bonding pads (125) embedded within the chip-side insulating layers (120) at an upper surface of the chip-side insulating layers (120) and electrically connected to the chip-side wiring interconnects (see Park, Figs.12-13 as shown above);
a solder mask (130) deposited over the chip-side insulating layers (120) and top surfaces of the chip-side bonding pads (125) (see Park, Figs.12-13 as shown above); and
at least one substrate trench (130-O21/022) formed in the solder mask (130), the at least one substrate trench (130-O21/022) has an inner sidewall located between an outer sidewall of the at least one substrate trench (130-O21/022) and proximal edges of the chip-side bonding pads (125) (see Park, Figs.12-13 as shown above), and
a chip-side wiring interconnect of the chip-side wiring interconnects is above a through-core via (115) of the through-core vias (115) in a first direction, and adjacent the inner sidewall of the at least one substrate trench (130-O21/022) in a second direction perpendicular to the first direction (see Park, Figs.12-13 as shown above).
Park is silent upon explicitly disclosing wherein at least one substrate trench formed in the solder mask and the chip-side insulating layers, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layers.
For support see Matsuzawa, which teaches wherein at least one substrate trench (120) formed in the solder mask (15) and the chip-side insulating layers (13), wherein the at least one substrate trench (120) includes a bottom surface in the chip-side insulating layers (13) (see Matsuzawa, Fig.10 as shown above and ¶ [0088]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Matsuzawa to enable the Park’s at least one substrate trench to be formed in the solder mask and the chip-side insulating layers, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layers as taught by Matsuzawa in order to reduces voids remaining in the at least one substrate trench and improve the reliability of the electronic component.
Regarding Claim 15: Park as modified teaches a substrate package as set forth in claim 14 as above. The combination of Park and Matsuzawa further teaches wherein the inner sidewall of the at least one substrate trench (120) and the outer sidewall of the at least one substrate trench (120) comprise sidewalls of the chip-side insulating layers (13) and sidewalls of the solder mask (15), and an outermost chip-side wiring interconnect (14) of the chip-side wiring interconnects (14) is adjacent the inner sidewall of the at least one substrate trench (120) (see Matsuzawa, Fig.10 as shown above).
Claim(s) 16 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park) and Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa) as applied to claim 14 above, and further in view of Yu et al. (U.S. 2014/0001644 A1, hereinafter refer to Yu).
Regarding Claim 16: Park as modified teaches a substrate package as applied to claim 14 above. The combination of Park and Matsuzawa is silent upon explicitly disclosing wherein the at least one substrate trench has a depth that is within a range of 10 microns to 100 microns.
For support see Yu, which teaches wherein the at least one substrate trench (142) has a depth (T1) that is within a range of 10 microns to 100 microns (see Yu, Figs.5-6 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Matsuzawa, and Yu to enable the depth of at least one substrate trench of the combination of Park’s and Matsuzawa’s to have the known depth as taught by Yu in order to improve packaging yield.
Claim(s) 17 and 19- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park) in view of Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa), Yu et al. (U.S. 2014/0001644 A1, hereinafter refer to Yu), and Huang et al. (U.S. 2020/0203300 A1, hereinafter refer to Huang).
Regarding Claim 17: Park discloses a method of forming a semiconductor structure (see Park, Figs.12-13 as shown above and ¶ [0002]), comprising:
providing a package (200/301/302/303) comprising at least one semiconductor die (301/302/303) and a redistribution structure (200) (see Park, Figs.12-13 as shown above);
forming a substrate package (100) comprising at least one substrate trench (130-O21/022) within a solder mask (130);
bonding the package (200/301/302/303) to the substrate package (100) such that the redistribution structure (200) is bonded to the substrate package (100) by solder material portions (20) (see Park, Figs.12-13 as shown above); and
applying an underfill material portion (25) around the solder material portions (20) (see Park, Figs.12-13 as shown above),
wherein the at least one substrate trench (130-O21/022) is laterally aligned with a sidewall of a molding compound die frame (500) of the package (see Park, Figs.12-13 as shown above), and
wherein the forming of the substrate package (100) is performed such that the substrate package (100) further (see Park, Figs.12-13 as shown above) comprises:
a core (110) including through-core vias (115) (see Park, Figs.12-13 as shown above); and
chip-side wiring interconnects in the chip-side insulating layer (120), wherein a chip- side wiring interconnect of the chip-side wiring interconnects is above a through-core via (115) of the through-core vias (115) in a first direction, and adjacent the inner sidewall of the at least one substrate trench (130-O21/022) in a second direction perpendicular to the first direction (see Park, Figs.12-13 as shown above).
Park is silent upon explicitly disclosing wherein forming a substrate package comprising at least one substrate trench within a solder mask and a chip-side insulating layer of the substrate package, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layer, and the at least one substrate trench has a width greater than a width of the chip-side insulating layer between the at least one substrate trench and an outer sidewall of the substrate package;
applying an underfill material portion around the solder material portions such that the underfill material portion contacts the bottom surface of the at least one substrate trench.
For support see Matsuzawa, which teaches wherein forming a substrate package comprising at least one substrate trench (18) within a solder mask (15) and a chip-side insulating layer (13) of the substrate package, wherein the at least one substrate trench (18) includes a bottom surface in the chip-side insulating layer (13), and the at least one substrate trench (18) has a width greater than a width of the chip-side insulating layer (13) between the at least one substrate trench (18) and an outer sidewall of the substrate package (see Matsuzawa, Fig.5B as shown above);
applying an underfill material portion (60) around the solder material portions (33) such that the underfill material portion (60) contacts the bottom surface of the at least one substrate trench (18) (see Matsuzawa, Fig.5B as shown above).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park and Matsuzawa to enable the Park’s at least one substrate trench to be formed within a solder mask and a chip-side insulating layer of the substrate package, wherein the at least one substrate trench includes a bottom surface in the chip-side insulating layer, and the at least one substrate trench has a width greater than a width of the chip-side insulating layer between the at least one substrate trench and an outer sidewall of the substrate package and to apply an underfill material portion around the solder material portions such that the underfill material portion contacts the bottom surface of the at least one substrate trench as taught by Matsuzawa in order to reduces voids remaining in the at least one substrate trench and improve the reliability of the electronic component.
The combination of Park and Matsuzawa is silent upon explicitly disclosing wherein an outer periphery of the underfill material portion is located between an inner sidewall of the at least one substrate trench formed in the solder mask and an outer sidewall of the at least one substrate trench formed in the solder mask.
For support see Yu, which teaches wherein an outer periphery of the underfill material portion (147) is located between an inner sidewall of the at least one substrate trench (142) formed in the solder mask (140) and an outer sidewall of the at least one substrate trench (142) formed in the solder mask (140) (see Yu, Figs.5-6 as shown above and ¶ [0018]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Matsuzawa, and Yu to enable an outer periphery of the underfill material portion to be located between an inner sidewall of the at least one substrate trench to be formed in the solder mask and an outer sidewall of the at least one substrate trench to be formed in the solder mask as taught by Yu in order to improve packaging yield.
The combination of Park, Matsuzawa, and Yu is silent upon explicitly disclosing wherein a portion of the second underfill material portion is disposed within the at least one substrate trench and in contact with the sidewall of the molding compound die frame.
For support see Huang, which teaches wherein a portion of the second underfill material portion (210) is disposed within the at least one substrate trench (192a) and in contact with the sidewall of the molding compound die frame (150) (see Huang, Fig.2A as shown above and ¶ [0003]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Matsuzawa, Yu, and Huang to enable the portion of the second underfill material portion of the combination of ark, Matsuzawa, and Yu to be disposed within the at least one substrate trench and in contact with the sidewall of the molding compound die frame as taught by Huang in order to obtain a reliable packages with electronic components with high integration density.
Regarding Claim 19: Park as modified teaches a method of forming a semiconductor structure as set forth in claim 17 as above. The combination of Park, Matsuzawa, Yu, and Huang further teaches wherein the forming of the substrate package comprises forming the at least one substrate trench within the substrate package by computer numerical control (CNC) machining chip-side insulating layers of the substrate package (see Matsuzawa, Fig.5B as shown above and ¶ [0071]).
Regarding Claim 20: Park as modified teaches a method of forming a semiconductor structure as set forth in claim 17 as above. The combination of Park, Matsuzawa, Yu, and Huang further teaches wherein a periphery of an area of the package (30) is located between the inner sidewall and the outer sidewall of the at least one substrate trench (18) in a plan view (see Matsuzawa, Figs.3 and 10B as shown above).
Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. 2021/0384143 A1, hereinafter refer to Park), Matsuzawa (U.S. 2020/0098656 A1, hereinafter refer to Matsuzawa), Yu et al. (U.S. 2014/0001644 A1, hereinafter refer to Yu), and Huang et al. (U.S. 2020/0203300 A1, hereinafter refer to Huang) as applied to claim 17 above, and further in view of Ko et al. (U.S. 2011/0316162 A1, hereinafter refer to Ko).
Regarding Claim 18: Park as modified teaches a method of forming a semiconductor structure as applied to claim 17 above. The combination of Park, Matsuzawa, Yu, and Huang is silent upon explicitly disclosing wherein the forming of the substrate package comprises forming the at least one substrate trench within the substrate package by lithographically patterning the solder mask of the substrate package.
For support see Ko, which teaches wherein the forming of the substrate package comprises forming the at least one substrate trench (122) within the substrate package (102) by lithographically patterning the solder mask (120) of the substrate package (102) (see Ko, Fig.6, ¶ [0022], and ¶ [0043]- ¶ [0046]).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Park, Matsuzawa, Yu, Huang, and Ko to enable forming of the substrate package to comprise forming the at least one substrate trench within the substrate package by lithographically patterning the solder mask of the substrate package as taught by Ko in order to increase the reliability performance of the integrated circuit packaging system.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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