Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 13th, 2026 has been entered.
Response to Arguments
2. Applicant’s arguments, filed January 13th, 2026, with respect to the rejections of the independent claims have been fully considered and are persuasive in light of the claim amendments. Therefore, the rejections have been withdrawn. However, upon further consideration, new grounds of rejection are made in view of Gabor et al (US 2020/0409847).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-32 are rejected under 35 U.S.C. 103 as being unpatentable over Brady (US 2019/0392296, cited in the previous Office Action) in view of Flanagan et al (US 2002/0129306, herein Flanagan) and Gabor et al (US 2020/0409847, herein Gabor).
In the following rejections, the processor embodiment of claim 27 will be addressed first.
Regarding claim 27, Brady teaches one or more processors, comprising:
circuitry to cause one or more compilers to cause information to be used by a plurality of threads to be selectively stored in one or more storage locations for on one or more threads to use the data ([0024-0025], [0045], compiler 105 generates code to be processed, [0089], threaded execution, & claim 3, [0087], [0139], allocate data in memory based on the mapping of data to the device for processing the data).
Brady fails to teach wherein the information is stored using one or more source code annotations, wherein the one or more source code annotations indicate a set of threads to have access to at least one shared copy of the information, or wherein the set of threads corresponds to a level of thread access within a hierarchy of thread levels.
Flanagan teaches a processor comprising circuitry wherein information is stored using one or more source code annotations, wherein the one or more source code annotations indicate a set of threads to have access to at least one shared copy of the information (Abstract, [0030-0033], annotating global and shared variables as thread-shared for threads which utilize the data).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Brady and Flanagan to utilize source code annotations. While Brady does not explicitly state that the compiler may determine where to store thread information based on source code annotations, Brady does contemplate the use of annotations when validating compiled code (Brady [0061]). As compilation and code annotations are a routine and conventional aspect of the microprocessor art, this combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Brady and Flanagan fail to teach wherein the set of threads corresponds to a level of thread access within a hierarchy of thread levels.
Gabor teaches a processor wherein a set of threads corresponds to a level of thread access within a hierarchy of thread levels ([0045-0047], threads with different hierarchical levels of privilege within the architecture of the computer system).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Brady and Flanagan with those of Gabor to utilize multiple privilege levels for the threads being executed. While Brady and Flanagan do not explicitly teach multiple hierarchical levels of thread access beyond the thread-shared or local levels of Flanagan, one of ordinary skill in the art would understand that different privilege levels which may have different capabilities to access shared or otherwise secure memory is a routine and conventional aspect of the microprocessor art. Therefore, as all three references disclose techniques for handling memory allocation and access in a multithreaded processing system, the combination would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 28, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 27, wherein the information includes one or more function argument values that correspond to one or more function parameters (Brady [0048], [0055], data used by device for activation or other functions, [0082], configuration parameters).
Regarding claim 29, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 27, wherein the one or more compilers are to identify one or more annotations of one or more function parameters and generate instructions to selectively store the information based, at least in part, on the annotations (Brady [0052], [0068], compiler directed allocation based on value attributes, [0045], [0087], [0139] compiler instruction generation & mapping).
Regarding claim 30, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 27, wherein the one or more compilers are to identify one or more annotations of one or more function parameters based, at least in part, on a function definition, and generate instructions to selectively store the information based, at least in part, on the annotations, where the one or more annotations designate a kind of memory and a level of thread access (Brady [0052-0053], compiler directed memory allocation based on attributes and resources, [0089], threaded execution & [0040], [0073], memory access control & Flanagan [0030], source code annotations).
Regarding claim 31, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 27, wherein the one or more compilers are to generate instructions to be performed on a graphics processing unit (GPU) (Brady [0034], GPU).
Regarding claim 32, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 27, wherein the one or more compilers are to cause the data to be selectively stored in the one or more storage locations based, at least in part, on one or more annotations of one or more function parameters (Brady [0033], function specialized hardware, [0052-0053], compiler directed memory allocation based on attributes and resources & Flanagan [0030], source code annotations).
Claims 1-3 and 5 are directed toward an alternate processor embodiment of the embodiment of claims 27-29 and 32, respectively. Therefore, the above rejections for claims 27-29 and 32 are applicable to claims 1-3 and 5, respectively.
Regarding claim 4, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 1, wherein the information includes one or more function argument values that correspond to one or more function parameters, and the one or more circuits are to cause the compiler to be selectively identify the storage location as memory designated to hold constant values (Brady [0087], [0139], compiler directed allocation & [0068], constant values).
Regarding claim 6, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 1, wherein the one or more circuits are to cause the compiler to be selectively identify the storage location based, at least in part, on one or more annotations of one or more function parameters, where the one or more annotations indicate a set of threads to use the information (Brady [0089], threaded execution & [0072] operation parameters used to tune hardware to appropriate resources & Flanagan [0030], source code annotations).
Regarding claim 7, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 1, wherein a first number of threads is to use the information and the one or more circuits are to cause a second number of copies of the information to be selectively stored based, at least in part, on one or more annotations that designate one or more sets of threads to use the information, where the second number is less than the first number (Brady [0089], threaded execution, [0068-0069], [0072-0073], compiler uses operation parameters to tune hardware resources including data sizes, [0081-0083], mapping of input and output data between operation nodes).
Regarding claim 8, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 1, wherein the information includes one or more function argument values that correspond to one or more function parameters, and the one or more circuits are to cause the compiler to selectively identify the storage location based, at least in part, one or more annotations of one or more function parameters that designate a set of threads and a kind of memory (Brady [0089], threaded execution, [0068-0069], [0072-0073], compiler uses operation parameters to direct data allocation & Flanagan [0030], source code annotations).
Claims 9-12 refer to a system embodiment of claims 1-3 and 8. Therefore, the above rejections for claims 1-3 and 8 are applicable to claims 9-12, respectively.
Regarding claim 13, The combination of Brady, Flanagan, and Gabor teaches the system of claim 9, wherein the information includes one or more function argument values that correspond to one or more function parameters, and the one or more processors are to cause the compiler to selectively identify the storage location based, at least in part, one or more annotations of one or more function parameters that designate one or more of constant memory and shared memory (Brady [0089], threaded execution, [0068-0069], [0072-0073], compiler uses operation parameters to direct data allocation & [0024], shared memories, [0068], constant values).
Regarding claim 14, The combination of Brady, Flanagan, and Gabor teaches the processor of claim 9, wherein one or more processors are to cause the compiler to selectively identify the storage location based, at least in part, on an annotation of a function definition, wherein the annotation designates a set of threads and a kind of memory (Brady [0089], threaded execution, [0068-0069], [0072-0073], compiler uses operation parameters to direct data allocation & [0024], compiler uses graph definition in code generation & Flanagan [0030], source code annotations).
Claims 15-18 and 20 refer to a method embodiment of claims 1-4 and 30, respectively. Therefore, the above rejections for claims 1-4 and 30 are applicable to claims 15-18 and 20.
Regarding claim 19, The combination of Brady, Flanagan, and Gabor teaches the method of claim 15, wherein the method further includes identifying an annotation of one or more parameters of a function and selectively identifying the storage location as memory designated to hold shared values based, at least in part, on the annotation (Brady [0068-0069], [0072-0073], operation parameters used to tune hardware to appropriate resources & [0024], shared memories & Flanagan [0030], source code annotations).
Claims 21-26 refer to a medium embodiment of claims 27-32, respectively. Therefore, the above rejections for claims 27-32 are applicable to claims 21-26.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu (US 2018/0276815) discloses a processor wherein each thread may have up to three levels of memory access.
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/MICHAEL J METZGER/Primary Examiner, Art Unit 2183