DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed May 11 2026, with respect to the rejection(s) of claims 1, 9, and 16 under USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2002/0153579), Bilodeau et al. (“Bilodeau” US 2018/0337253), and Weyers et al. (“Weyers” US 2019/0051647).
Regarding claim 1, Yamamoto discloses:
A method for patterning a silicon layer (10, para. [0104]) of a semiconductor device (Figure 7D), the method comprising:
positioning an etch stop layer (4, para. [0104]) between a dielectric layer (3) and the silicon layer (10, Figure 7D); and
etching the silicon layer (10) with a chemical etchant (para. [0104], Figure 7D) comprising one or more chemical solutions to selectively remove one or more portions of the silicon layer.
Yamamoto does not explicitly disclose the specific etchant used to etch the silicon layer, or a non-gaseous etchant, and also does not disclose that the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1.
Bilodeau discloses, however, in para. [0021] an etching process of etching polysilicon relative to an etch stop layer (silicon nitride here, see para. [0021]) using a non-gaseous etchant (see wet etching, para. [0013], and acid solution composition in para. [0032]), wherein the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1 (see para. [0021] which discloses a etch rate selectivity ratio of about 2:1 to about 1000:1).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Bilodeau into the teachings of Yamamoto, specifically to include a non-gaseous chemical etchant as disclosed by Bilodeau for the purpose of achieving a high etch rate of polysilicon (Bilodeau, para. [0032]).
Yamamoto and Bilodeau do not disclose depositing, after the etching, one or more metal layers onto the silicon layer.
Weyers discloses, however, a process of depositing a contact metal layer (620) onto a silicon layer (polysilicon 321, para. [0077]) of a capacitor (see para. [0203], [0204], and Figure 2).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Weyers into the teachings of Yamamoto and Bilodeau to include a metal layer deposited on the silicon layer for the purpose of providing electrical wiring/external connection to the device (Weyers, para. [0075], [0095]). The combination of Weyers into Yamamoto and Bilodeau would result in the claimed order of operations because the final step of Yamamoto is the etching of the silicon layer.
Regarding claim 2, Yamamoto discloses wherein a dielectric constant of the etch stop layer (4, para. [0102]) is greater than or equal to a dielectric constant of the dielectric layer (3, para. [0073]).
Regarding claim 3, Yamamoto discloses wherein the semiconductor device is a capacitor (9, 3, 4, 6, 10, Figure 7D) comprising a top plate (10) and a bottom plate (9), wherein the silicon layer (10, para. 104) is a top plate of the capacitor comprising doped polysilicon (para. [0104], Figure 7D),
wherein the dielectric layer (3, para. 95) is comprised within a dielectric stack (3, 17, para. 95, Figure 5A).
Regarding claim 4, Yamamoto discloses wherein the etch stop layer (4) comprises at least one material selected from the group consisting of hafnium oxide and zirconium oxide (para. [0062]).
Regarding claim 5, Yamamoto discloses wherein the material is hafnium oxide (para. [0062]), and wherein the silicon layer (10) comprises doped polysilicon (see para. [0098]).
Regarding claim 7, Yamamoto further discloses depositing the etch stop layer (4) onto the dielectric layer (3) via an atomic layer deposition process (para. [0103], Figure 7C).
Regarding claim 8, Yamamoto further discloses depositing the etch stop layer (4, Figure 7C) via a deposition process that provides a continuous and pinhole free conformality of the etch stop layer (4, para. [0105]) over the dielectric layer (3, Figure 7A-7D).
Claims 9-10 and 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto (US 2002/0153579), Bilodeau et al. (“Bilodeau” US 2018/0337253), and Weyers et al. (“Weyers” US 2019/0051647).
Regarding claim 9, Yamamoto discloses a method comprising:
depositing an etch stop layer (4, para. 102) onto a dielectric layer (3, para. 102) of a semiconductor device (Figure 7C);
depositing a silicon layer (10, para. 104, Figure 7D) onto the etch stop layer (4, para. 102); and
performing an etching process (para. 104, Figure 7D) on the silicon layer (10, para. 104) using a chemical etchant (para. 104), wherein the etch stop layer (4, Figure 7D) shields the dielectric layer (3, Figure 7D) from the etching process (para. 104).
Yamamoto does not explicitly disclose the specific etchant used to etch the silicon layer, or a non-gaseous etchant, and also does not disclose that the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1, and depositing, after the etching, one or more metal layers onto the silicon layer.
Bilodeau discloses, however, in para. [0021] an etching process of etching polysilicon relative to an etch stop layer (silicon nitride here, see para. [0021]) using a non-gaseous etchant (see wet etching, para. [0013], and acid solution composition in para. [0032]), wherein the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1 (see para. [0021] which discloses a etch rate selectivity ratio of about 2:1 to about 1000:1).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Bilodeau into the teachings of Yamamoto, specifically to include a non-gaseous chemical etchant as disclosed by Bilodeau for the purpose of achieving a high etch rate of polysilicon (Bilodeau, para. [0032]).
Further, Weyers discloses a process of depositing a contact metal layer (620) onto a silicon layer (polysilicon 321, para. [0077]) of a capacitor (see para. [0203], [0204], and Figure 2).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Weyers into the teachings of Yamamoto and Bilodeau to include a metal layer deposited on the silicon layer for the purpose of providing electrical wiring/external connection to the device (Weyers, para. [0075], [0095]). The combination of Weyers into Yamamoto and Bilodeau would result in the claimed order of operations because the final step of Yamamoto is the etching of the silicon layer.
Regarding claim 10, Yamamoto discloses wherein the etch stop layer (4, para. [0102]) is deposited via a deposition process selected from the group consisting of: an atomic layer deposition process, low pressure chemical vapor deposition, and plasma enhanced chemical vapor deposition (para. [0103]).
Regarding claim 12, Yamamoto discloses wherein the etch stop layer (4, para. [0107]) comprises at least one material selected from the group consisting of hafnium oxide and zirconium oxide (para. [0107]).
Regarding claim 13, Yamamoto discloses wherein the at least one material is hafnium oxide (para. [0107]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto, Bilodeau, and Weyers as applied to claim 9 above and further in view of Sakata (US Pub. 20070072403).
Regarding claim 14, Yamamoto discloses a lithography and etching process (see para. [0104]) of the silicon layer (10), which would imply a photolithography and etch process. However, Yamamoto does not explicitly disclose depositing a photoresist onto the silicon layer prior to the etching process, wherein the photoresist shields a portion of the silicon layer from the etching process.
Sakata discloses, however, depositing a photoresist (120, para. [0046]) onto the silicon layer (118) prior to the etching process, wherein the photoresist shields a portion of the silicon layer from the etching process (para. [0046], Figure 2(A) – 2(B)).
It would have been obvious to one of ordinary skill in the art at the time of the effective filing date of the invention to incorporate the teachings of Sakata into the method of Yamamoto, Bilodeau, and Weyers to include deposition of a photoresist onto the silicon layer prior to the etching process, the photoresist shielding a portion of the silicon layer from the etching process. The ordinary artisan would have been motivated to modify Yamamoto in the above manner with a reasonable expectation of success and resulting in the predictable result of precise etching of the silicon layer. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto, Bilodeau, and Weyers as applied to claims 1 and 9 above, respectively, and further in view of Kuo (US 2023/0068481 A1).
Regarding claim 23, Kuo discloses wherein the dielectric layer (112) extends into one or more trenches (see trenches shown in Figure 1) formed within a substrate (102, shown in Figure 1, disclosed in para. [0011]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kuo into the teachings of Yamamoto, Bilodeau, and Weyers to include the dielectric layer extending into one or more trenches formed within a substrate for the purpose of increasing capacitance and reducing die area (Kuo, para. [0011]).
Regarding claim 24, Kuo discloses wherein the dielectric layer (112) extends into one or more trenches (see trenches shown in Figure 1) formed within a substrate (102, shown in Figure 1, disclosed in para. [0011]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present invention to incorporate the teachings of Kuo into the teachings of Yamamoto, Bilodeau, and Weyers to include the dielectric layer extending into one or more trenches formed within a substrate for the purpose of increasing capacitance and reducing die area (Kuo, para. [0011]).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto, Bilodeau, and Weyers as applied to claim 9 above and further in view of Wu et al. (“Wu” US 2002/0094611).
Regarding claim 25, Wu discloses one or more metal layers (para. [0046], a polycide capacitor plate 24b, where polycide is known in the art as comprising a stacked structure comprising metal silicide and polysilicon layers, it is also obvious to split a single layer of a material into several layers, and thus comprises a one or more metal layers) wherein the one or more metal layers comprise a first metal layer with a thickness between 50 angstroms and 1000 angstroms deposited using an epitaxial growth process, a second metal layer with a thickness between 250 angstroms and 1000 angstroms, and a third metal layer with a thickness between 500 angstroms and 2000 angstroms (Wu discloses the total thickness of the capacitor plate 24b is formed to have a thickness of 1000 to 3000 Angstroms, which the total thickness of the first through third layers as claimed overlaps with Wu’s range).
It would have been obvious to one having ordinary skill in the art to incorporate the metal layer of Wu (polycide layer) into the teachings of Yamamoto, Bilodeau, and Weyers above for the purpose of utilizing a preferred material and thickness for the metal layers (see Wu, para. [0046]). Further, it would be obvious to one having ordinary skill in the art to optimize the thickness of each of the layers within the polycide to have the thicknesses as claimed according to the desired characteristics of the semiconductor device.
Claims 26 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo (US 2023/0068481 A1), Bilodeau et al. (“Bilodeau” US 2018/0337253), and Tran et al. (“Tran” US 2013/0161792).
Regarding claim 26, Kuo discloses a method (Figures 2A-7), comprising:
depositing an etch stop layer (218, made of hafnium oxide which is an etch stop material) onto a dielectric layer (214, para. [0024]) of a semiconductor device (200, Figure 7), wherein the dielectric layer (214) extends into one or more trenches formed within a substrate (202) of the device (see Figure 7);
depositing a silicon layer (232, para. [0031] discloses that 232 may be silicon) onto the etch stop layer (218, see Figure 7);
etching the silicon layer (232) to selectively remove one or more portions of the silicon layer (232, see Figures 4 and 5),
depositing, after the etching of the silicon layer (etching of silicon layer 232 shown in Figures 4 and 5), a first metal layer (via 240) onto the silicon layer (232, see Figure 7);
depositing, [after the depositing of the first metal layer,] a silicon nitride layer (etch stop layer 236, para. [0037] discloses 236 may be silicon nitride) onto a first portion of the first metal layer (240, lateral portions) and a first portion of the substrate (202, see Figure 7); and
depositing, [after the depositing the silicon nitride layer,] a[n insulating layer] (238, analogous to the claimed benzocyclobutane layer) onto a first portion of the silicon nitride layer (236) and a second portion of the first metal layer (240, see Figure 7).
Kuo does not disclose a non-gaseous etchant comprising one or more chemical solutions, wherein the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1.
Bilodeau discloses in para. [0021] an etching process of etching polysilicon relative to an etch stop layer (silicon nitride here, see para. [0021]) using a non-gaseous etchant (see wet etching, para. [0013], and acid solution composition in para. [0032]), wherein the etching has a selectivity ratio characterizing etch rates of the silicon layer to the etch stop layer of at least 200:1 and less than or equal to 1000:1 (see para. [0021] which discloses a etch rate selectivity ratio of about 2:1 to about 1000:1).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Bilodeau into the teachings of Kuo, specifically to include a non-gaseous chemical etchant as disclosed by Bilodeau for the purpose of achieving a high etch rate of polysilicon (Bilodeau, para. [0032]).
Kuo does not disclose that the insulating layer (238) is made of benzocyclobutane.
Tran discloses, however, an insulating layer (132) capping a trench capacitor (see Figure 1A) that is made of benzocyclobutane (see para. [0024]).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Tran into the teachings of Kuo and Bilodeau because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo, Bilodeau, and Tran as applied to claim 26 above and further in view of Lyu et al. (“Lyu” Us 2004/0173825).
Regarding claim 27, Lyu discloses in Figure 12 a first metal layer (220a, disposed on polysilicon layer 205a, see Figure 12) wherein the first metal layer comprises titanium, platinum, gold, copper, silver, nickel, chrome, a titanium tungsten composite, or a combination thereof (para. [0060]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lyu into the teachings of Kuo, Bilodeau, and Tran above because the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Claim 28 is rejected under 35 U.S.C. 103 as being unpatentable over Kuo, Bilodeau, and Tran as applied to claim 26 above and further in view of Sato (US 2002/0018278).
Regarding claim 28, Sato discloses a dielectric layer used for a capacitor which comprises a stacked multilayer of silicon nitride and a low temperature oxide (such as silicon oxide) in para. [0098]. Thus, Sato discloses depositing, onto a moisture seal layer (silicon nitride) of the semiconductor device, a low temperature oxide layer (LTO silicon oxide, see para. [0098]).
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Sato into the teachings of Kuo, Bilodeau, and Tran for the purpose of assuring reliability of the device. Additionally, the selection of a known material based on its suitability for its intended use is prima facie obvious. See MPEP 2144.07.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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