DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Group I, Species 2, was elected.
Amendment filed February 13, 2026 is acknowledged. New Claim 28 has been added. Claim 7 has been cancelled. Claims 1, 8, 21 and 25 have been amended. Claims 1, 3-6, 8-13, 15 and 21-28 are pending.
Action on merits of Elected Invention and Species, claims 1, 3-6, 8-13, 15 and 21-28 follows.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21-23 and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by HO et al. (US. Patent No. 9,548,366).
With respect to claim 21, HO teaches a method of forming a semiconductor device as claimed including:
forming a dummy gate structure (28) over a substrate (20), the dummy gate structure comprising a dummy dielectric (22), a dummy gate electrode (24), and a gate spacer (26);
etching the substrate to form a first recess (not shown) adjacent the dummy gate structure (28);
forming an epitaxial region (30) in the first recess;
forming an interlayer dielectric (34) over the epitaxial region (30) and adjacent the gate spacer (26);
removing the dummy gate electrode (24) and the dummy dielectric (22) to form a second recess (36);
forming a gate dielectric (38) and a gate electrode (40) in the second recess (36);
performing a first planarization to level the gate electrode (40) with the interlayer dielectric (34);
etching the gate electrode (40) and the gate spacer (26) to form a third recess (44), the gate electrode (40) having a first height above the substrate, the gate spacer (26) having a second height above the substrate, the interlayer dielectric (34) having a third height above the substrate, the second height being greater than the first height;
depositing a first dielectric layer (46) in the third recess (44);
etching the first dielectric layer (46) to form a fourth recess (50); and
depositing a semiconductor layer (52) over a remaining portion of the first dielectric layer (46) in the fourth recess (50); and
etching the interlayer dielectric (34) to expose the epitaxial region (30), wherein etching the interlayer dielectric (34) comprises etching the semiconductor layer (52) to expose the first dielectric layer (46). (See FIGs. 1-13).
With respect to claim 22, the depositing the first dielectric layer (46) of HO in the third recess (44) comprises forming a first void (48) in the first dielectric layer (46) above the gate electrode (40).
With respect to claim 23, etching the first dielectric layer (46) of HO comprises removing the first void (48) in the first dielectric layer.
With respect to claim 26, the method of HO further comprises performing a second planarization to level the semiconductor layer (52) with the interlayer dielectric (34), wherein after performing the second planarization, the gate spacer (26) still has the second height above the substrate.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over HO ‘366 as applied to claim 23 above.
With respect to claim 24, HO teaches the method as described in claim 23 above including: depositing the semiconductor layer (52) comprising forming the semiconductor layer (52) above the gate electrode (40).
Thus, HO is shown to teach all the features of the claim with the exception of explicitly disclosing depositing the semiconductor layer comprises forming a second void in the semiconductor layer.
However, similar to the invention, the second hardmask layer 202, semiconductor layer, can be formed without void, FIG. 16E. Moreover, the second hard mask layer 202, being formed with or without void, is completely removed to provide for the lower source/drain contact.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to deposit the semiconductor layer of HO above the gate electrode, with or without the second void to protect the gate structure during the etching of the interlayer dielectric.
An OFFICIAL NOTICE is taken regarding the semiconductor layer comprises a second void, since the invention can be formed with void (FIG 16D) or without void (FIG. 16E), therefore, the formation of the second void in the semiconductor layer is not critical because the second hard mask, the void in the semiconductor layer, is subsequently, completely, removed, to expose the epitaxial region, as shown in FIG. 20D.
With respect to claim 25, the method of HO, further comprising:
performing a second planarization to level the semiconductor layer (52) with the interlayer dielectric (34); and
etching the interlayer dielectric (34) to expose the epitaxial region (30), wherein after the etching the interlayer dielectric (34) comprises converting the semiconductor layer, with or without void, into a fifth recess. (See FIG. 13).
Regarding “converting the second void into a fifth recess”, the etching of the interlayer dielectric 34 of HO converting the semiconductor layer 52 into a fifth recess.
The Official Notice is also applied here.
Claims 1, 3-6, 8-9 and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over HO et al. (US. Patent No. 9,548,366) in view of HSIAO et al. (US. Pub. No. 2020/0343088) both of record.
With respect to claim 1, HO ‘366 teaches a method of forming a semiconductor device as claimed including:
forming a source/drain region (30) over a substrate (20);
forming a first interlayer dielectric (34) over the source/drain region (30);
forming a gate structure (42) over the substrate (20) and laterally adjacent to the source/drain region (30), the gate structure (42) comprising a gate electrode (40) and a gate dielectric (38), a gate spacer (26/32) being interposed between the gate dielectric (38) and the source/drain region (30);
forming a gate mask over the gate structure (42), the forming the gate mask comprising:
etching a portion of the gate structure (42A) and a portion of the gate spacer (26/32) to form a recess relative to a top surface of the first interlayer dielectric (34);
depositing a first dielectric layer (46) over the gate structure in the recess and over the first interlayer dielectric (34);
etching a portion of the first dielectric layer (46);
depositing a semiconductor layer (52) over the first dielectric layer (46) in the recess; and
planarizing the semiconductor layer (52) to be coplanar with the first interlayer dielectric (34);
etching the first interlayer dielectric (34) to expose the source/drain region (30) and the semiconductor layer (52);
forming a metal layer (barrier layer, not shown) over the source/drain region (30) and over the semiconductor layer (52); and
forming a lower source/drain contact (60) over the metal layer (barrier layer, not shown). (See FIGs. 5-14).
Thus HO is shown to teach all the features of the claim with the exception of explicitly disclosing converting a portion of the metal layer into alloy region.
However, HSIAO teaches a method for forming a semiconductor device including:
forming a gate mask over a gate structure (120);
forming a metal layer (300) over a source/drain region (160) and over the gate mask;
converting a first portion of the metal layer (300) into source/drain alloy region (302) at an interface with the source/drain region (160); and
forming a lower source/drain contact (304) over the source/drain alloy region (302) and over the gate mask region. (See FIGs. 2C-E).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device including converting the portion of the metal layer (barrier layer, not shown) of HO into the source/drain alloy region at an interface with the source/drain region as taught by HSIAO to reduce contact resistance.
Regarding the limitation “converting a second portion of the metal layer into a gate mask alloy region at an interface with the semiconductor layer of the gate mask”, the barrier layer (not shown) of HO is formed over the regions 58, as shown in FIG. 13, which includes the semiconductor layer 52 of the gate mask.
Thus, in view of HSIAO, the converting portion of the metal layer 300 into the source/drain alloy region (302) would obviously converting a second portion of the metal layer (not shown) of HO, that formed on the semiconductor layer 52, into a gate mask alloy region at an interface with the semiconductor layer (52) of the gate mask.
Therefore, the limitations: “converting a first portion of the metal layer into source/drain alloy region at an interface with the source/drain region; converting a second portion of the metal layer into a gate mask alloy region at an interface with the semiconductor layer of the gate mask; and forming a lower source/drain contact over the source/drain alloy region and over the gate mask alloy region” are met.
With respect to claim 3, the etching the portion of the first dielectric layer (46) of HO comprises removing the first dielectric layer (46) from over the first interlayer dielectric (34).
With respect to claim 4, after depositing the first dielectric layer (46) of HO, the first dielectric layer (46) comprises a first void (48) located at a first height above the gate structure (40).
With respect to claim 5, the etching the portion of the first dielectric layer (46) of HO comprises removing the first void (48).
With respect to claim 6, after depositing the semiconductor layer (52) of HO, the semiconductor layer (52) located at a second height above the gate structure (42), and wherein the second height is greater than the first height.
Thus, HO, in view of HSIAO, is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor layer comprises a second void.
However, similar to the invention, the second hardmask layer 202, semiconductor layer, can be formed without void, FIG. 16E. Moreover, the second hard mask layer 202, being formed with or without void, is completely removed to provide for the lower source/drain contact.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to deposit the semiconductor layer of HO in the first recess, with or without void to protect the gate structure during the etching of the first dielectric layer.
An OFFICIAL NOTICE is taken regarding the semiconductor layer comprises a second void, since the invention can be formed with void (FIG 16D) or without void (FIG. 16E), therefore, the formation of the second void in the semiconductor layer is not critical because the second hard mask, the void in the semiconductor layer, is subsequently, completely, removed, as shown in FIG. 20D.
With respect to claim 8, forming the metal layer of HO comprises conformally depositing a metal (barrier layer, not shown) on the source/drain region (30) and on the gate mask.
With respect to claim 9, in view of HSIAO, the source/drain alloy region comprises a silicon-germanide, and wherein the gate mask alloy region comprises a silicide.
With respect to claim 27, the gate dielectric (38) of HO comprises a different material than the gate spacer (26).
With respect to claim 28, etching the first interlayer dielectric (34) to expose the source/drain region (30) and the semiconductor layer (52) of HO comprises exposing and etching the first dielectric layer (46).
Claims 10-13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over HO ‘366.
With respect to claim 10, HO teaches a method of forming a semiconductor device substantially as claimed including:
forming a first dielectric layer (34) over a source/drain region (30);
forming a gate dielectric (38) and a gate electrode (40) laterally adjacent the first dielectric layer (34);
etching the gate electrode (40) to form a first recess (44) above the gate electrode (40);
conformally depositing a second dielectric layer (46) in the first recess (44) over the gate electrode (40);
etching the second dielectric layer (46) to partially re-form the first recess (44);
depositing a semiconductor layer (52) in the first recess (44) over the second dielectric layer (46); and
etching the first dielectric layer (34) to expose the source/drain region (30), wherein the etching the first dielectric layer (34) comprises using an etchant that etches the semiconductor layer (52) at a lower rate than the second dielectric layer (46). (See FIGs. 1-13).
Thus, HO is shown to teach all the features of the claim with the exception of explicitly disclosing the semiconductor layer comprising a first void.
However, similar to the invention, FIG. 16E, the second hardmask layer, semiconductor layer, can be formed without void. Moreover, the second hard mask layer 202, being formed with or without void, is completely removed to provide for the lower source/drain contact.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to deposit the semiconductor layer of HO in the first recess, with or without void to protect the gate structure during the etching of the first dielectric layer.
An OFFICIAL NOTICE is taken regarding the formation of the first void, since the invention can be formed with void (FIG 16D) or without void (FIG. 16E), therefore, the formation of the first void in the semiconductor layer is not critical because the second hard mask, the void in the semiconductor layer, is subsequently, completely, removed, to expose the sour/drain region, as shown in FIG. 20D.
With respect to claim 11, the second dielectric layer (46) of HO comprises silicon nitride.
With respect to claim 12, the semiconductor layer (52) of HO comprises silicon.
With respect to claim 13, after conformally depositing the second dielectric layer (46) of HO, the second dielectric layer (46) comprises a second void (48).
With respect to claim 15, the etching the first dielectric layer (34) of HO further comprises etching a portion of the semiconductor layer (52).
Response to Arguments
Applicant’s arguments with respect to amended (claims 1 and 21) and new claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments, regarding claim 10, filed February 13, 2026 have been fully considered but they are not persuasive.
Regarding claim 10, Applicant argues:
Applicant respectfully disagrees that the Office Action makes a prima facie case and/or otherwise meets its burdens for rejecting claim 10. Applicant further notes that the Office action includes analogous reasonings in the rejections of claims 6 and 24, and Applicant respectfully hereby applies the articulated traversals of the rejection of claim 10 to the rejections of claims 6 and 24. Accordingly, Applicant respectfully requests that the rejection of claim 10 - as well as the rejections of claims 6 and 24-25 - be withdrawn and that claim 10 be deemed allowable.
However, the scope of claim 10, which includes the limitation of claim 14, was reconsidered in light of the OFFICIAL NOTICE. It is determined that regardless of the semiconductor layer 202 being formed with or without the void. The void in the semiconductor layer 202 would have been completely removed. The void in the semiconductor layer 202 would not, in any ways, shapes or forms, contribute to the etching of the first dielectric layer to expose the source/drain region.
Applicant argues:
Applicant respectfully contends that the asserted Official Notice is insufficient because the Office Action fails to make clear exactly what fact(s) the purported official notice is being taken of.
However, Applicant is correctly citing the MPEP: “The M.P.E.P. provides that "an examiner may take official notice of facts not in the record or rely on 'common knowledge' in making a rejection, however such rejections should be judiciously applied." M.P.E.P. § 2144 (Reliance on Common Knowledge in the Art or "Well Known" Prior Art) (emphasis added).”
Note that, as clearly indicated in the Rejection above, the Examiner has clearly showed that the semiconductor layer can be formed with void (FIG. 16D) or without void (FIG. 16E) because the void being formed in the semiconductor layer would have been removed (FIG. 20D).
Applicant fails to provide any evidence that without the void being formed in the semiconductor layer, the “etching of the first dielectric layer to expose the source/drain region” would not have materialized.
According to the process step, the etchant would have removed the “first dielectric layer to expose the sour/drain region”, not the semiconductor layer, with or without void.
The rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 8:00-5:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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