DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: 1 through 17 rejected, 18 through 20 withdrawn.
Present action: 1 through 17 rejected, 18 through 20 withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 4, 5, and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346)
Regarding claim 1.
Maeda teaches:
A method of wafer testing, comprising: contacting, prior to completion of die formation on a first wafer (fig 9a:substrate; (column 6 lines 55-67),
a first plurality of test pads exposed on a first interior metal layer (fig 6g; [column 2 lines 5-10], fig 9a:1st interconnect layer; [column 6 lines 55-67]) of the first wafer with one or more test probes (fig 9a; [column 6 lines 55-67]),
the first plurality of test pads coupled to a plurality of test structures (fig 9a:primitive device; [column 7 lines 5-10]) spatially arranged across different levels of the first wafer;
testing (fig 17:105; [column 12 lines 55-65]) the test structures utilizing one or more signals provided by the one or more test probes to the first plurality of test pads;
and forming (fig 17:103; [column 13 lines 5-15]), based on the testing the test structures meeting a predefined criteria (fig 17:106; [column 13 lines 5-15]), at least a second metal layer (fig 9b:2nd interconnect layer; [column 6 lines 55-67]) on the first wafer over the first interior metal layer (fig 9b; [column 6 lines 65-67]),
wherein the testing (fig 17:105; [column 12 lines 55-65]) comprises generating a metric (fig 17:parametric test; [column 13 lines 25-30]) for each of the test structures (fig 17:105; [column 12 lines 55-65]) corresponding to defects (fig 15:functional or fault test; [column 13 lines 25-30])occurring at the the first wafer (fig 9a:substrate; (column 6 lines 55-67), each metric indicating whether a defect (fig 15:functional or fault test; [column 13 lines 25-30]) is identified in a respective one of the test structures (fig 17:105; [column 12 lines 55-65]), comprising a count of the test structures identified as defective (fig 15:functional or fault test; [column 13 lines 25-30]),
and wherein fabrication proceeds to deposition of the second metal layer (fig 9b) when the combined value satisfies the threshold (fig 17:106; [column 13 lines 5-15]).
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Maeda does not teach test structures arranged at different levels
Young teaches:
A plurality of test structures (fig 3:300; [column 5 lines 60-65]) spatially arranged across different levels of the first wafer (fig 3:200; [column 5 lines 35-40]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to spatially arrange the test structures across different levels in order to form a space efficient structure for characterizing the process (column 3 lines 5-15)
Maeda does not detail the specific steps of the testing method include aggregating and comparing.
Sul teaches:
wherein the testing comprises generating a metric (fig 3:308; [para 0041]) for each of the test structures (fig 3:306; [para 0041]) corresponding to defects occurring at the different levels of the first wafer ([para 0030]),
aggregating the metrics into a combined value representative of cross- level defect conditions of the first wafer (fig 3:314; [para 0041]),
and comparing the combined value to a threshold during in-line wafer processing (fig 3:318; [para 0041]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the steps of IDDQ for stuck and delay testing in order to detect leakage current in large scale device (Sul paragraph 5) as is suggested by Maeda (column 9 lines 50-60)
Regarding claim 2.
Maeda in view of Young in view of Sul teaches the method of claim 1, further
Maeda teaches:
wherein forming the second metal layer further comprises: forming a top metal layer (fig 9d:Nth layer; [column 7 lines 5-10]) on the first wafer (fig 9d:substrate).
Regarding claim 4
Maeda in view of Young in view of Sul teaches the method of claim 1, further
Maeda teaches:
contacting, prior to completion of die formation on the first wafer, a second plurality of test pads exposed on a second interior metal layer of the first wafer with one or more test probes (fig 9b; [column 6 lines 50-67]),
the second plurality of test pads coupled to the plurality of test structures,
testing the test structures utilizing one or more signals provided by the one or more test probes to the second plurality of test pads (fig 17:105; [column 13 lines 10-20]);
and forming (fig 17:103; [column 13 lines 10-20]), based on the testing the test structures meeting a predefined criteria (fig 17:105,106; [column 13 lines 10-20]), at least a third metal layer on the first wafer over the second metal layer (fig 9c).
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Young teaches:
the second plurality of test pads (fig 2,3:215; [column 5 lines 50-40) formed in a scribe lane (fig 2,3:210; [column 5 lines 50-40) of the first wafer (fig 2,3:212; [column 5 lines 50-40)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide scribe lines in order that the device can be subsequently singulated in a dicing operation.
Regarding claim 5
Maeda in view of Young in view of Sul teaches the method of claim 1, further
Maeda teaches:
testing the test structures further comprises:
and forming, identifying a passing wafer (fig 17:105,106; [column 13 lines 10-20]) at least the second metal layer on the first wafer over the first interior metal layer (fig 17:103; [column 13 lines 10-20]).
Sul teaches:
testing the test structures (fig 3:302; [para 0041]) further comprises: adding each of the metrics to formulate a sum (fig 4:430; [para 0041]);
based on the sum identifying a passing wafer (fig 3:320; [para 0041])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to sum the metrics in order to analyze large scale devices simultaneously (paragraph 5).
Regarding claim 6
Maeda in view of Young in view of Sul teaches the method of claim 1, further
Maeda teaches:
testing the test structures further comprises: testing two or more test structures in parallel (fig 9a,18; [column 13 line 49]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346) as applied to claim 1 and further in view of Gao (US 2020/0335408).
Regarding claim 3.
Maeda in view of Young in view of Sul teaches the method of claim 1 above.
Maeda in view of Young in view of Sul does not teach polishing the pad,
Gao teaches:
polishing the first plurality of test pads (fig 8:104; [para 0047]) exposed on the first interior metal layer (fig 8:102; [para 0053]) of the first wafer (fig 8:100; [para 0047]) prior to forming the second metal layer (fig 8:802; [para 0053]) on the first wafer (fig 8:100; [para 0047]) over the first interior metal layer (fig 8; [para 0047]).
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It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to polish the surface in order to planarize defects and prepare the surface for subsequent deposition steps.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346) as applied to claim 1 and further in view of Hou (US 2004/0002175).
Regarding claim 7.
Maeda in view of Young in view of Sul teaches the method of claim 1 above.
Maeda in view of Young in view of Sul does not teach the test duration.
Hou teaches:
a time period between testing the test structures and forming the second metal layer is less than about 1 second per test pad (fig 1:20 milliseconds; [para 0022]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to take less than 1 second in order to minimize processing time and increase manufacturing throughput.
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346) as applied to claim 1 and further in view of Dabral (US 2020/0176419)
Regarding claim 8.
Maeda in view of Young in view of Sul teaches the method of claim 1 above.
Maeda further teaches:
testing test structures of a(fig 9a; [column 6 lines 55-67]) utilizing one or more signals provided by the one or more test probes to a plurality of test pads residing on interior metal layers of the wafers (fig 17:105; [column 13 lines 5-15]);
and forming on each of the (fig 17:106,103; [column 13 lines 10-20]),
wherein the first wafer is part of the batch.
Maeda in view of Young in view of Sul does not teach the batch comprises a plurality of wafers
Dabral teaches:
testing a batch comprising a plurality of wafers (fig 20:top,bottom; [para 0086])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to process a batch comprising multiple wafers in order to increase the production of the process by increasing the number of chips produced.
Regarding claim 9.
Maeda in view of Young in view of Sul in view of Dabral teaches the method of claim 8 above.
Maeda further teaches:
(fig 9a,9b; [column 7 lines 1-10])
Given the teaching of the references, it would have been obvious to determine the optimum duration (less than 6 hours) involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 10, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346) as applied to claim 1 and further in view of Dabral (US 2020/0176419)
Regarding claim 10.
Maeda in view of Young in view of Sul teaches the method of claim 1.
Maeda in view of Young in view of Sul does not teach bonding wafers.
Dabral teaches:
bonding the first wafer to a second wafer to form at least part of a wafer stack (fig 19:1945; [para 0085]);
and dicing stacked dies from the wafer stack (fig 19:1955; [para 0085]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond and dice wafers in order to provide dense wiring, heterogeneous integration, and is scalable. increase the functionality of the package (paragraph 4).
Regarding claim 11.
Maeda in view of Young in view of Sul in view of Dabral teaches the method of claim 10.
Dabral teaches:
bonding further comprises: forming a plurality of hybrid bonds between contact pads (fig 7a:118; [para 0060]) exposed on facing surfaces of the first and second wafers (fig 19,20:1945; [para 0085]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond and dice wafers in order to provide dense wiring, heterogeneous integration, and is scalable. increase the functionality of the package (paragraph 4).
Regarding claim 12.
Maeda in view of Young in view of Sul in view of Dabral teaches the method of claim 10.
Young teaches:
dicing further comprises: separating the test structures from the first and second wafers (column 5 lines 40-50, the testing structures are located in the scribe line and separated by the process of sawing the scribe line).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to separate the testing structures from the wafers because placing the test structures in the scribe line conserves die space for operational structures.
Claim(s) 13, 14, 16, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346)
Regarding claim 13.
Maeda teaches:
A method of wafer testing, comprising: contacting, prior to completion of die formation on a first wafer (fig 9a:substrate; [column 6 lines 55-67]), a first plurality of test pads exposed on a first interior metal layer (fig 6g; [column 2 lines 5-10]) of the first wafer with one or more test probes (fig 9a; [column 6 lines 55-67]),
the first plurality of test pads coupled to a plurality of test structures (fig 9a:primitive devices; [column 7 lines 5-10]) spatially arranged across
testing (fig 17:105; [column 13 lines 10-20]) the test structures utilizing one or more signals provided by the one or more test probes to the first plurality of test pads (annotated fig 9a);
generating a metric for each test structure (fig 17:parametric test; [column 13 lines 25-30),each metric indicating whether a defect is identified in a respective one of the test structures (fig 15:functional or fault test; [column 13 lines 25-30]);
each metric corresponding to defects (fig 15:functional or fault test; [column 13 lines 25-30]) in each of the respective test structures (fig 9a:primitive devices; [column 7 lines 5-10]);
comprising a count of the test structures identified as defective;
deciding,, whether to proceed with depositing a second metal layer on the first wafer during wafer processing (fig 17:106; [column 13 lines 10-15]);
and depositing the second metal layer (fig 9b; [column 6 lines 50-67]) when the combined value satisfies the threshold (fig 17:106,103; [column 13 lines 10-20]).
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Maeda does not teach test structures arranged at different levels
Young teaches:
A plurality of test structures (fig 3:300; [column 5 lines 60-65]) spatially arranged across different levels of the first wafer (fig 3:200; [column 5 lines 35-40]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to spatially arrange the test structures across different levels in order to form a space efficient structure for characterizing the process (column 3 lines 5-15)
Maeda does not detail the specific steps of the testing method.
Sul teaches:
generating a metric for each test structure (fig 3:DUT; [para 0041]), each metric corresponding to defects in each of the respective test structures (fig 3:308; [para 0041]);
aggregating the metrics into a combined value representative of cross-level defect conditions of the first wafer (fig 3:314; [para 0041]);
the combined value comprising a count of the test structures identified as defective (fig 3:314; [para 0041]);
comparing the combined value to a threshold during in-line wafer processing; deciding (fig 3:318; [para 0041]), based on the combined value satisfying the threshold, whether to proceed (fig 3:320; [para 0041])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the steps of IDDQ for stuck and delay testing in order to detect leakage current in large scale device (Sul paragraph 5) as is suggested by Maeda (column 9 lines 50-60)
Regarding claim 14.
Maeda in view of Young in view of Sul teaches the method of claim 13.
Maeda teaches:
forming the second metal layer further comprises: forming a top metal layer on the first wafer (fig 9d:Nth level; [column 7 lines 1-10]).
Regarding claim 16.
Maeda in view of Young in view of Sul teaches the method of claim 13.
Maeda teaches:
contacting, prior to completion of die formation on the first wafer,
a second plurality of test pads exposed on a second interior metal layer of the first wafer with one or more test probes (9b,9c annotated),
the second plurality of test pads coupled to the plurality of test structures (fig 2b; [column 6 lines 55-67]),
testing the test structures utilizing one or more signals (fig 17:105; [column 13 lines 10-20]) provided by the one or more test probes to the second plurality of test pads (fig 9b; [column 6 lines 55-67]);
and forming, based on the testing the test structures meeting a predefined criteria (fig 17:106,103; [column 13 lines 10-20]),
at least a third metal layer on the first wafer over the second metal layer (fig 9c; [column 7 lines 1-10]).
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Young teaches:
a method of wafer testing, comprising:
a second plurality of test pads (fig 3:316; [column 6 lines 20-25])
formed in a scribe lane (fig 2:210; [column 5 lines 45-50])
of a first wafer (fig 2:200; [column 5 lines 35-40]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to locate the test elements in a scribe line so that the die areas are not obscured.
Regarding claim 17.
Maeda in view of Young in view of Sul teaches the method of claim 13.
Maeda teaches:
testing the test structures (fig 17:105; [column 13 lines 10-20]) further comprises:
forming, based on(fig 17:106; [column 13 lines 10-20]), at least the second metal layer on the first wafer over the first interior metal layer (fig 9b; [column 6 lines 55-67]).
Sul teaches:
based on the sum (fig 4:430; [para 0045]) identifying a passing wafer (fig 3:320; [para 0041])
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Maeda (US 6423558) in view of Young (US 6680484) in view of Sul (US 2012/0158346) as applied to claim 13 and further in view of Gao (US 2020/0335408).
Regarding claim 15.
Maeda in view of Young in view of Sul teaches the method of claim 1 above.
Maeda in view of Young in view of Sul does not teach polishing the pad,
Gao teaches:
polishing the first plurality of test pads (fig 8:104; [para 0047]) exposed on the first interior metal layer (fig 8:102; [para 0053]) of the first wafer (fig 8:100; [para 0047]) prior to forming the second metal layer (fig 8:802; [para 0053]) on the first wafer (fig 8:100; [para 0047]) over the first interior metal layer (fig 8; [para 0047]).
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It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to polish the surface in order to planarize defects and prepare the surface for subsequent deposition steps.
Response to Arguments
Applicant's arguments filed 6/30/2026 have been fully considered but they are not persuasive.
The applicant argues that the prior art does not teach that each metric indicates whether a defect is identified in the respective test structure.
However, Maeda explicitly states “The test of primitive devices or sub-circuits may use an exhaustive test, a functional test, a stuck-at fault test, a delay fault test, a quiescent power supply power current test, a transient power supply current test, a parametric test or any other testing method. In particular, a test which takes place after the formation of each interconnect layer which follows the initial test may comprise only a wiring connection test” in column 13.
Testing for parameters, faults, and functionality is the same as measuring a metric to identify defects. “The identical invention must be shown in as complete detail as is contained in the ... claim.” Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). MPEP 2131
The applicant argues that the prior art does not teach a count of defects.
However, a count or in other words a number of defects is a property of the structures. How the defects are counted can be done in various ways including combining the current flow as taught by Sul. Further, the mere mental process of counting is an abstract idea and is not accorded patentability, mental processes – concepts performed in the human mind (including an observation, evaluation, judgment, opinion, counting) (see MPEP § 2106.04(a)(2)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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