DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 05, 2026 has been entered.
Status of the Claims
Species 1, as shown in FIGs. 3-6C, was elected without traverse.
Amendments filed June 05, 2026 is acknowledged. Non-elected Species, claims 9-16 have been withdrawn from consideration. Claims 1 and 17 have been amended. Claims 1-20 are pending.
Action on merits of the Elected Species, claims 1-8 and 17-20 follows.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d) as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 19 recites: The electronic apparatus of claim 17, wherein the second separation distance is greater than the first separation distance.
However, amended claim 17 has already claimed: “wherein a gate insulating layer patterned is arranged between the oxide semiconductor layer and the gate electrode, and an end of an upper surface of the gate insulating layer is spaced apart by a second separation distance, which is greater than the first separation distance, …”.
Therefore, claim 19 fails to further limit claim 17.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 5-8, 17 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over NOH et al. (US. Pub. No. 2021/0005638) of record, in view of YAMAZAKI et al. (US. Pub. No. 2015/0221679).
With respect to claim 1, NOH teaches a display apparatus substantially as claimed including:
a substrate (100);
a first thin-film transistor (200) arranged on the substrate and including a first semiconductor layer (210) and a first gate electrode (230), the first semiconductor layer (210) including silicon, and the first gate electrode (230) overlapping the first semiconductor layer;
a second thin-film transistor (300) arranged on the substrate and including a second semiconductor layer (310) and a second gate electrode (370), the second semiconductor layer (310) including an oxide semiconductor, and the second gate electrode (370) overlapping the second semiconductor layer (310); and
a display element (500) electrically connected to the first thin-film transistor,
wherein the second gate electrode (330) has a structure in which a lower layer (331) and an upper layer (331) are stacked in a thickness direction (Z), and the upper layer (332) includes a material different from a material of the lower layer (331),
wherein a maximum width of the lower layer (331) is greater than a maximum width of the upper layer (332) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (331) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (332) is inclined in a second angle, with respect to the substrate,
wherein the upper layer (332) includes an upper surface, and a lower surface contacting the lower layer (331) and having a length greater than a length of the upper surface,
wherein a second gate insulating layer (114) patterned is arranged between the second semiconductor layer (310) and the second gate electrode (330), and includes an upper surface contacting the lower layer of the second gate electrode (330), a lower surface contacting the second semiconductor layer (310), and an inclined side surface extending from the upper surface to the lower surface,
wherein an end of the upper surface of the second gate insulating layer (114) is spaced apart by a second separation distance in the first direction (X) from an end of the lower layer (331), and the second separation distance is greater than the first separation distance, and
wherein a width of the second gate insulating layer (114) disposed directly on the second semiconductor layer (310) is substantially the same as a width of a channel region (310c) of the second semiconductor layer (310). (See FIGs. 5, 14-15).
Thus, NOH is shown to teach all the features of the claim with the exception of explicitly disclosing the inclination of the second angle being different from the first angle.
However, YAMAZAKI ‘679 teaches a display device including:
a second thin-film transistor (150) arranged on a substrate (100) and including a second semiconductor layer (126) and a second gate electrode (114a) , and the second gate electrode overlapping the second semiconductor layer (106),
wherein the second gate electrode (114a) has a structure in which a lower layer (114a1) and an upper layer (114a2) are stacked in a thickness direction (Z), and the upper layer (114a2) includes a material different from a material of the lower layer (114a1),
wherein a maximum width of the lower layer (114a1) is greater than a maximum width of the upper layer (114a2) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (114a1) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (114a2) is inclined in a second angle, which is different from the first angle, with respect to the substrate;
wherein an end of the upper surface of the second gate insulating layer (112a) is spaced apart by a second separation distance in the first direction (X) from an end of the lower layer (114a1), and the second separation distance is greater than the first separation distance, and
wherein a width of the second gate insulating layer (112a) disposed directly on the second semiconductor layer (126) is substantially the same as a width of a channel region (106) of the second semiconductor layer (126). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second gate electrode of NOH having the side surface of lower layer and the side surface of upper layer incline at different angle as taught by YAMAZAKI for the same intended purpose of providing the upper layer and the lower layer with different width.
With respect to claim 17, NOH teaches an electronic apparatus substantially as claimed including:
a substrate (100);
a thin-film transistor (300) arranged on the substrate and including an oxide semiconductor layer (310) and a gate electrode (330), the oxide semiconductor layer (310) including an oxide semiconductor, and the gate electrode (330) overlapping the oxide semiconductor layer (310); and
a display element (500) electrically connected to the thin-film transistor,
wherein the gate electrode (330) has a structure in which a lower layer (331) and an upper layer (332) are stacked in a thickness direction (Z), the upper layer (332) includes a material different from a material of the lower layer (331), and a maximum width of the lower layer (331) is greater than a maximum width of the upper layer (332) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (331) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (332) is inclined in a second angle, with respect to the substrate,
wherein the upper layer (332) includes an upper surface, and a lower surface contacting the lower layer (331) and having a length greater than a length of the upper surface,
wherein a gate insulating layer (114) patterned is arranged between the oxide semiconductor layer (310) and the gate electrode (330), and an end of an upper surface of the gate insulating layer (114) is spaced apart by a second separation distance, which is greater than the first separation distance, in the first direction (X) perpendicular to the thickness direction (Z) from an end of the lower layer (331),
wherein a width of a channel region (310c) of the oxide semiconductor layer (310) is greater than a width of the gate electrode (330), and
wherein a width of the gate insulating layer (114) disposed directly on the oxide semiconductor layer (310) is substantially the same as the width of the channel region (310c) of the oxide semiconductor layer (310). (See FIGs. 5, 14-15).
Thus, NOH is shown to teach all the features of the claim with the exception of explicitly disclosing the inclination of the second angle being different from the first angle.
However, YAMAZAKI ‘679 teaches an electronic apparatus including:
a thin-film transistor (150) arranged on substrate (100) and including an oxide semiconductor layer (126) and a gate electrode (114a), the oxide semiconductor layer (126) including an oxide semiconductor, and the gate electrode (114a) overlapping the oxide semiconductor layer (126); and
wherein the gate electrode (114a) has a structure in which a lower layer (114a1) and an upper layer (114a2) are stacked in a thickness direction (Z), the upper layer (114a2) includes a material different from a material of the lower layer (114a1), and a maximum width of the lower layer (114a1) is greater than a maximum width of the upper layer (114a2) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (114a1) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (114a2) is inclined in a second angle, which is different from the first angle, with respect to the substrate,
wherein the upper layer (114a2) includes an upper surface, and a lower surface contacting the lower layer (114a1) and having a length greater than a length of the upper surface,
wherein a gate insulating layer (112a) patterned is arranged between the oxide semiconductor layer (126) and the gate electrode (114a), and an end of an upper surface of the gate insulating layer (112a) is spaced apart by a second separation distance, which is greater than the first separation distance, in the first direction (X) perpendicular to the thickness direction (Z) from an end of the lower layer (114a1). (See FIGs. 1, 25B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the gate electrode of NOH having the side surface of lower layer and the side surface of upper layer incline at different angle as taught by YAMAZAKI ‘679 for the same intended purpose of providing the upper layer and the lower layer with different width.
With respect to claim 5, a thickness of the upper layer (332) in the thickness direction (Z) of NOH or YAMAZAKI is greater than a thickness of the lower layer (331).
With respect to claim 6, an etch rate of the upper layer (332) of NOH or YAMAZAKI is greater than an etch rate of the lower layer (331).
With respect to claims 7 and 20, the upper layer (332) of NOH includes copper (Cu), and the lower layer (331) includes titanium (Ti).
With respect to claim 8, the first gate electrode (230) of NOH includes a single layer of a copper alloy and includes at least one of silver (Ag), calcium (Ca), and zinc (Zn) in addition to copper (Cu).
With respect to claim 19, As best understood by the Examiner, the second separation distance of NOH or YAMAZAKI is greater than the first separation distance.
Claims 2-4 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over NOH ‘638 and YAMAZAKI ‘679, as applied to claims 1 and 17 above and further in view of YAMAZAKI et al. (US. Pub. No. 2006/0051906) of record.
With respect to claims 2 and 18, the second separation distance of NOH and YAMAZAKI, being greater than the first separation distance. (See NOH’s FIG. 5 and YAMAZAKI’s FIG. 1).
Thus, NOH and YAMAZAKI ‘679 are shown to teach all the features of the claim with the exception of explicitly disclosing the second separation distance has a value in a range of about 0.2 to about 5 times that first separation distance.
Note that, the claimed range does not appears to be critical.
However, YAMAZAKI ‘906 teaches an apparatus including:
a gate electrode has a structure in which a lower layer (108) and an upper layer (109) are stacked in a thickness direction (Z), and the upper layer (109) includes a material different from a material of the lower layer (108),
a maximum width of the lower layer (108) is greater than a maximum width of the upper layer (109) by a first separation distance (124= 0.1 to 1 µm ) in a first direction (X) perpendicular to the thickness direction (Z),
wherein an end of the upper surface of gate insulating layer (1103) is spaced apart by a second separation distance (126 = 0.5 to 2 µm) in the first direction (X) from an end of the lower layer (108), and the second separation distance (126) is greater than the first separation distance (124), hence the second separation distance (126) has a value in a range of about 0.2 to about 5 times that first separation distance (124). (See FIGs. 4A-C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the gate electrode of NOH and YAMAZAKI, having the second separation distance value in a range of about 0.2 to about 5 times that first separation distance as taught by YAMAZAKI ‘906 for the same intended purpose of preventing the occurrence of an electrical short.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 3, in view of YAMAZAKI ‘906, the second separation distance (126) has a value in a range of about 0.5 µm to about 2 µm, hence overlaps the claimed range of 0.1 µm to about 1 µm.
With respect to claim 4, in view of YAMAZAKI ‘906, the first separation distance (124) has a value in a range of about 0.1 µm to about 1 µm, hence overlaps the claimed range of 0.2 µm to about 0.5 µm.
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANH D MAI whose telephone number is (571)272-1710 (Email: Anh.Mai2@uspto.gov). The examiner can normally be reached 8:00-5:00PM.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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