DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Species 1, as shown in FIGs. 3-6C, was elected without traverse.
Amendments filed January 12, 2026 is acknowledged. Non-elected Species, claims 9-16 have been withdrawn from consideration. Claims 1 and 17-20 have been amended. Claims 1-20 are pending.
Action on merits of the Elected Species, claims 1-8 and 17-20 follows.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 5-8 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over NOH et al. (US. Pub. No. 2021/0005638) of record, in view of YAMAGUCHI et al. (US. Pub. No. 2005/0194645).
With respect to claim 1, NOH teaches a display apparatus substantially as claimed including:
a substrate (100);
a first thin-film transistor (200) arranged on the substrate and including a first semiconductor layer (210) and a first gate electrode (230), the first semiconductor layer (210) including silicon, and the first gate electrode (230) overlapping the first semiconductor layer;
a second thin-film transistor (300) arranged on the substrate and including a second semiconductor layer (310) and a second gate electrode (370), the second semiconductor layer (310) including an oxide semiconductor, and the second gate electrode (370) overlapping the second semiconductor layer (310); and
a display element (500) electrically connected to the first thin-film transistor,
wherein the second gate electrode (330) has a structure in which a lower layer (331) and an upper layer (331) are stacked in a thickness direction (Z), and the upper layer (332) includes a material different from a material of the lower layer (331),
wherein a maximum width of the lower layer (331) is greater than a maximum width of the upper layer (332) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (331) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (332) is inclined in a second angle, with respect to the substrate,
wherein the upper layer (332) includes an upper surface, and a lower surface contacting the lower layer (331) and having a length greater than a length of the upper surface,
wherein a second gate insulating layer (114) patterned is arranged between the second semiconductor layer (310) and the second gate electrode (330), and includes an upper surface contacting the lower layer of the second gate electrode (330), a lower surface contacting the second semiconductor layer (310), and an inclined side surface extending from the upper surface to the lower surface,
wherein an end of the upper surface of the second gate insulating layer (114) is spaced apart by a second separation distance in the first direction (X) from an end of the lower layer (331), and
wherein a width of the second gate insulating layer (114) disposed directly on the second semiconductor layer (310) is substantially the same as a width of a channel region (310c) of the second semiconductor layer (310). (See FIGs. 5, 6, 8, 14-15).
Thus, NOH is shown to teach all the features of the claim with the exception of explicitly disclosing the inclination of the second angle being different from the first angle.
However, YAMAGUCHI teaches a display device including:
a second thin-film transistor arranged on a substrate and including a second semiconductor layer (1102) and a second gate electrode, and the second gate electrode overlapping the second semiconductor layer (1102),
wherein the second gate electrode has a structure in which a lower layer (1004) and an upper layer (1002) are stacked in a thickness direction (Z), and the upper layer (1002) includes a material different from a material of the lower layer (1004),
wherein a maximum width of the lower layer (1004) is greater than a maximum width of the upper layer (1002) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (1004) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (1002) is inclined in a second angle, which is different from the first angle, with respect to the substrate. (See FIG. 11A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second gate electrode of NOH having the side surface of lower layer and the side surface of upper layer incline at different angle as taught by YAMAGUCHI for the same intended purpose of providing the upper layer and the lower layer with different width.
With respect to claim 17, NOH teaches an electronic apparatus substantially as claimed including:
a substrate (100);
a thin-film transistor (300) arranged on the substrate and including an oxide semiconductor layer (310) and a gate electrode (330), the oxide semiconductor layer (310) including an oxide semiconductor, and the gate electrode (330) overlapping the oxide semiconductor layer (310); and
a display element (500) electrically connected to the thin-film transistor,
wherein the gate electrode (330) has a structure in which a lower layer (331) and an upper layer (332) are stacked in a thickness direction (Z), the upper layer (332) includes a material different from a material of the lower layer (331), and a maximum width of the lower layer (331) is greater than a maximum width of the upper layer (332) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (331) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (332) is inclined in a second angle, with respect to the substrate,
wherein the upper layer (332) includes an upper surface, and a lower surface contacting the lower layer (331) and having a length greater than a length of the upper surface,
wherein a gate insulating layer (114) patterned is arranged between the oxide semiconductor layer (310) and the gate electrode (330), and an end of an upper surface of the gate insulating layer (114) is spaced apart by a second separation distance in the first direction (X) perpendicular to the thickness direction (Z) from an end of the lower layer (331),
wherein a width of a channel region (310c) of the oxide semiconductor layer (310) is greater than a width of the gate electrode (330), and
wherein a width of the gate insulating layer (114) disposed directly on the oxide semiconductor layer (310) is substantially the same as the width of the channel region (310c) of the oxide semiconductor layer (310). (See FIGs. 5, 6, 8, 14-15).
Thus, NOH is shown to teach all the features of the claim with the exception of explicitly disclosing the inclination of the second angle being different from the first angle.
However, YAMAGUCHI teaches an electronic apparatus including:
a second thin-film transistor arranged on a substrate and including a second semiconductor layer (1102) and a second gate electrode, and the second gate electrode overlapping the second semiconductor layer (1102),
wherein the second gate electrode has a structure in which a lower layer (1004) and an upper layer (1002) are stacked in a thickness direction (Z), and the upper layer (1002) includes a material different from a material of the lower layer (1004),
wherein a maximum width of the lower layer (1004) is greater than a maximum width of the upper layer (1002) by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z),
wherein a side surface of the lower layer (1004) is inclined in a first angle with respect to the substrate, and a side surface of the upper layer (1002) is inclined in a second angle, which is different from the first angle, with respect to the substrate. (See FIG. 11A).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second gate electrode of NOH having the side surface of lower layer and the side surface of upper layer incline at different angle as taught by YAMAGUCHI for the same intended purpose of providing the upper layer and the lower layer with different width.
With respect to claims 2 and 18, the second separation distance of NOH, in view of YAMAGUCHI, has a value in a range within the claimed range of 0.2 to about 5 times that first separation distance. (See FIGs. 5-6 and 8).
Note that, the claimed range does not appears to be critical.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second separation distance of NOH, in view of YAMAGUCHI, having the value in the range as claimed without departing from the scope of NOH’s invention to prevent the occurrence of an electrical short.
With respect to claim 5, a thickness of the upper layer (332) in the thickness direction (Z) of NOH or YAMAGUCHI is greater than a thickness of the lower layer (331).
With respect to claim 6, an etch rate of the upper layer (332) of NOH or YAMAGUCHI is greater than an etch rate of the lower layer (331).
With respect to claims 7 and 20, the upper layer (332) of NOH includes copper (Cu), and the lower layer (331) includes titanium (Ti).
With respect to claim 8, the first gate electrode (230) of NOH includes a single layer of a copper alloy and includes at least one of silver (Ag), calcium (Ca), and zinc (Zn) in addition to copper (Cu).
With respect to claim 19, the second separation distance of NOH is greater than the first separation distance.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over NOH ‘638 and YAMAGUCHI ‘645, as applied to claim 1 above and further in view of YAMAZAKI et al. (US. Pub. No. 2006/0051906) of record.
With respect to claim 3, NOH, in view of YAMAGUCHI, teaches the display apparatus as described in claim 1 above including the edge of the lower layer (331) is spaced apart by a first separation distance in a first direction (X) perpendicular to the thickness direction (Z) from the edge of the upper layer (332),
wherein the end of the upper surface of the second gate insulating layer (114) is spaced apart by the second separation distance in the first direction (X) from the edge of the lower layer (331).
Note that, the claimed second separation distance value of 0.1 µm to about 1 µm does not appears to be critical.
Thus, NOH is shown to teach all the features of the claim with the exception of explicitly disclosing the second separation distance value.
However, YAMAZAKI ‘906 teaches a display apparatus including: an edge of an lower layer (108) is spaced apart by a first separation distance (124) in a first direction (X) perpendicular to the thickness direction (Z) from an edge of an upper layer (109), wherein the first separation distance (124) has a value in a range of about 0.1 µm to about 0.5 µm. (See FIGs. 4A-C).
NOH further teaches that the second separation distance is greater than the first separation distance.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second separation distance of NOH, in view of YAMAGUCHI, having the value being greater than the first separation distance value as taught by YAMAZAKI ‘906, hence greater than the first distance value of 0.1 µm to about 0.5 µm, for the same intended purpose of preventing occurrence of electrical short.
It is well settled that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (Claimed process which was performed at a temperature between 40 ºC and 80 ºC and an acid concentration between 25% and 70% was held to be prima facie obvious over a reference process which differed from the claims only in that the reference process was performed at a temperature of 100 ºC and an acid concentration of 10%.); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382 ("The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages.").
With respect to claim 4, in view of YAMAZAKI ‘906, the first separation distance (124) has a value in a range of about 0.1 µm to about 0.5 µm, hence overlaps the claimed range of 0.2 µm to about 0.5 µm.
Note that, the claimed value of 0.2 µm to about 0.5 µm does not appears to be critical.
Further, the specification contains no disclosure of either the critical nature of the claimed second separation value in a range of about 0.1 to 1 µm (claim 3) or first separation value in a range of about 0.2 to 0.5 µm (claim 4), of any unexpected results arising therefrom. Where patentability is aid to based upon particular chosen dimension or upon another variable recited in a claim, the Applicant must show that the chosen dimension are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Response to Arguments
Applicant’s arguments with respect to amended claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/Primary Examiner, Art Unit 2893
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