DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on Mar. 5th 2026 has been entered. Claims 11-16 and 28-41 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liang et al. (US 9627332) in view of Hosoda et al. (US 20040084778) and Saito et al. (US 20140264901).
Regarding claim 11, Liang teaches an integrated circuit (IC) chip (integrated circuit structure; Abstract), comprising:
a substrate (fig. 1A, substrate 10; col. 2, lin. 31) including a device region (active region 10A; col. 2, lin. 54) and a ring region (seal ring region 10S; col. 2, lin. 54) surrounding the device region (10A); and
an interconnect structure (seal ring structure 30 and metal interconnect layers (not shown) around semiconductor die 11 and; col. 2, lin. 55-58) disposed over the substrate (10) and comprising a device portion (metal interconnect layers in 10A (not shown) around semiconductor die 11 and; col. 2, lin. 55-56) disposed directly over the device region (10A) and a ring portion (seal ring structure 30; col. 2, lin. 57-58) disposed directly over the ring region (10S), the ring portion (30) of the interconnect structure comprising a plurality of seal ring walls (third seal rings 33; col. 4, lin. 8) interleaved by a plurality of metal-free zones (zone between 33), each of the plurality of seal ring walls (33) including a first group of metal layers (fig. 1C, body pattern 44S of metal layers 44 in third seal ring 33; col. 4, lin. 31-34) and a second group of metal layers (fig. 1B, metal layer 54; Col. 6, Lin. 17-18) directly over the first group of metal layers (44),
wherein each of the first group of metal layers (44) comprises:
a first plurality of metal line loops (body pattern 44S) fully surrounding the device portion (11) of the interconnect structure, and
a plurality of lateral connectors (connectors between neighbor 44S) sandwiched between two adjacent metal line loops (44S) of the first plurality of metal line loops,
wherein each of the second group of metal layers (54) comprises a second plurality of metal line loops (54 of 33) fully surrounding the device portion (11) of the interconnect structure,
wherein the second plurality of metal line loops (fig. 1B, 54 of 33) are disposed directly over the first plurality of metal line loops (44s of 33),
wherein a lower metal layer (fig. 1B, 44S in lower level 44) in the first group of metal layers (44) comprises a first metal line loop (left via rings 46R in lower level 44; col. 5, lin. 64-65) and a second metal line loop (nearest 46V in lower level 44),
wherein an upper metal layer (44S in upper level 44) in the first group of metal layers (44) comprises a third metal line loop (left 46R in upper level 44) directly over the first metal line loop (left 46R in lower level 44) and a fourth metal line loop (nearest 46V in upper level 44) directly over the second metal line loop (nearest 46V in lower level 44),
wherein a via bar (via ring 46R) is disposed vertically between the first metal line loop (left 46R in lower level 44) and the third metal line loop (left 46R in upper level 44).
In addition, Liang fails to explicitly teach no conductive features are present between the second metal line loop and the fourth metal line loop along a vertical direction.
However, Hosoda teaches no conductive features (Hosoda: fig. 5, no conductive features) are present between the second metal line loop (Hosoda: dummy patterns 50b; para. 0047, similar to 46V in lower level 44 of Liang) and the fourth metal line loop (Hosoda: dummy patterns 46b; para. 0047, similar to 46V in upper level 44 of Liang) along a vertical direction (vertical direction).
Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add detail of no conductive features are present between the second metal line loop and the seventh metal line loop along a vertical direction as taught by Hosoda.
Doing so would realize less via through inter-layer insulating films and the generation of cracks and peelings in the interface between the inter-layer insulating films or in the insulating film due to stresses generated at the end of the guard ring can be effectively prevented (Hosoda: para. 0015).
Liang in view of Hosoda fails to explicitly teach the second plurality of metal line loops are laterally spaced apart from one another,
wherein each of the second group of metal layers is free of any lateral connectors sandwiched between the second plurality of metal line loops.
However, Saito teaches the second plurality of metal line loops (Saito: fig. 5B, wiring layers M5 and M6; para. 0070, similar to 54 of Liang) are laterally spaced apart from one another (Saito: M5 or M6 laterally spaced without lateral connectors),
wherein each of the second group of metal layers (Saito: M5 and M6) is free of any lateral connectors (Saito: M5 or M6 without lateral connectors) sandwiched between the second plurality of metal line loops (Saito: M5 and M6).
Saito, Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second group of metal layers is free of any lateral connectors as taught by Saito.
Doing so would realize wider wiring patterns to better cover the thin wiring layers to provide higher moisture resistance (Saito: para. 0162).
Regarding claim 12, Liang in view of Hosoda and Saito further teaches the IC chip of claim 11, wherein each of the first plurality of metal line loops (Liang: fig. 1C, 44S) has a width smaller than about 1 μm (Liang: line width of each of the segments of the body pattern 44S ranges from 0.5 micrometers to 1 micrometer; col. 5, lin. 19-21) and
wherein each of the second plurality of metal line loops (Saito: fig. 3C, M6) has a width (Saito: M6 has more than twice width of M4, which is similar to 44s of Liang with 0.5 micrometers to 1 micrometer, so more than 1 micrometer to 2 micrometer) greater than about 1 μm.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 13, Liang in view of Hosoda and Saito further teaches the IC chip of claim 11, wherein none of the plurality of lateral connectors (Liang: fig. 1C, connectors between 44S only contact two neighbor 44S) is in contact with more than two metal line loops (Liang: 44S) of the first plurality of metal line loops.
Regarding claim 14, Liang in view of Hosoda and Saito further teaches the IC chip of claim 11 including plurality of lateral connectors (Liang: fig. 1C, connectors between 44S).
Liang in view of Hosoda and Saito as applied to claim 11 above fails to explicitly teach each of the plurality of lateral connectors is substantially square in shape.
However, Liang teaches each of the plurality of lateral connectors (Liang: fig. 1C, 44S) is substantially square in shape (Liang: from the top view of fig. 1C, connectors between 44S appears to be a square shape).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the substantially square in shape.
Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Hosoda and Saito as applied to claim 11 above, and further in view of Ogata et al. (US 20130062777).
Regarding claim 15 Liang in view of Hosoda and Saito teaches the IC chip of claim 11 including the first group of metal layers (Liang: fig. 1B, 44).
Liang in view of Hosoda and Saito fails to explicitly teach the first group of metal layers consists of 5 metal layers.
However, Ogata teaches the first group of metal layers (Ogata: fig. 1, Second to sixth wiring layers M2~M6 have almost the same structure; para. 0076, similar to 44 of Liang) consists of 5 metal layers (Ogata: M2~M6 5 layers).
Ogata, Saito, Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal ring regions.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first group of metal layers consists of 5 metal layers.
Doing so would realize a wiring rings structure to improve the mechanical strength of the periphery (Ogata: para. 0137).
Regarding claim 16 Liang in view of Hosoda and Saito teaches the IC chip of claim 11 including the second group of metal layers (Liang: fig. 1B, 54).
Liang in view of Hosoda and Saito fails to explicitly teach the second group of metal layers comprises consists of 4 metal layers.
However, Ogata teaches the second group of metal layers (Ogata: fig. 1, seventh wiring layer M7, eighth wiring layer M8 have the same structure and the number of layers can be set to be 3 and ninth wiring layer M9; para. 0077, 0078, similar to 54 of Liang) comprises consists of 4 metal layers (Ogata: 4 layers of 3 layers M7, M8 and M9).
Ogata, Saito, Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal ring regions.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second group of metal layers comprises consists of 4 metal layers.
Doing so would realize a wiring rings structure to improve the mechanical strength of the periphery (Ogata: para. 0137).
Claims 28, 30-32 and 34-35 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito and Ogata.
Regarding claim 28, Liang teaches an integrated circuit (IC) chip (integrated circuit structure; Abstract), comprising:
a substrate (fig. 1A, substrate 10; col. 2, lin. 31) including a device region (active region 10A; col. 2, lin. 54) and a ring region (seal ring region 10S; col. 2, lin. 54) surrounding the device region (10A); and
an interconnect structure (seal ring structure 30 and metal interconnect layers (not shown) around semiconductor die 11 and; col. 2, lin. 55-58) disposed over the substrate (10) and comprising a device portion (metal interconnect layers in 10A (not shown) around semiconductor die 11 and; col. 2, lin. 55-56) disposed directly over the device region (10A) and a ring portion (seal ring structure 30; col. 2, lin. 57-58) disposed directly over the ring region (10S), the ring portion (30) of the interconnect structure comprising a plurality of seal ring walls (third seal rings 33; col. 4, lin. 8) interleaved by a plurality of metal-free zones (zone between 33), each of the plurality of seal ring walls (33) including a first group of metal layers (fig. 1C, body pattern 44S of metal layers 44 in third seal ring 33; col. 4, lin. 31-34) and a second group of metal layers (fig. 1B, metal layer 54; Col. 6, Lin. 17-18) directly over the first group of metal layers (44),
wherein each of the first group of metal layers (44) comprises:
a first plurality of metal line loops (body pattern 44S) fully surrounding the device portion (11) of the interconnect structure, and
a plurality of lateral connectors (connectors between neighbor 44S) sandwiched between two adjacent metal line loops (44S) of the first plurality of metal line loops,
wherein each of the second group of metal layers (54) comprises a second plurality of metal line loops (54 of 33) fully surrounding the device portion (11) of the interconnect structure.
Liang fails to explicitly teach the second plurality of metal line loops are laterally spaced apart from one another,
wherein each of the second group of metal layers is free of any lateral connectors sandwiched between the second plurality of metal line loops.
However, Saito teaches the second plurality of metal line loops (Saito: fig. 5B, wiring layers M5 and M6; para. 0070, similar to 54 of Liang) are laterally spaced apart from one another (Saito: M5 or M6 laterally spaced without lateral connectors),
wherein each of the second group of metal layers (Saito: M5 and M6) is free of any lateral connectors (Saito: M5 or M6 without lateral connectors) sandwiched between the second plurality of metal line loops (Saito: M5 and M6).
Saito and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second group of metal layers is free of any lateral connectors as taught by Saito.
Doing so would realize wider wiring patterns to better cover the thin wiring layers to provide higher moisture resistance (Saito: para. 0162).
Liang in view of Saito fails to explicitly teach the first group of metal layers consists of five (5) metal layers, and
wherein the second group of metal layers consists of four (4) metal layers.
However, Ogata teaches the first group of metal layers (Ogata: fig. 1, Second to sixth wiring layers M2~M6 have almost the same structure; para. 0076, similar to 44 of Liang) consists of five (5) metal layers (Ogata: M2~M6 5 layers), and
wherein the second group of metal layers (seventh wiring layer M7, eighth wiring layer M8 have the same structure and the number of layers can be set to be 3 and ninth wiring layer M9; para. 0077, 0078, similar to 54 of Liang) consists of four (4) metal layers (Ogata: 4 layers of 3 layers M7, M8 and M9).
Saito, Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal ring regions.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first group of metal layers consists of five (5) metal layers and the second group of metal layers consists of four (4) metal layers.
Doing so would realize a wiring rings structure to improve the mechanical strength of the periphery (Ogata: para. 0137).
Regarding claim 30, Liang in view of Hosoda and Saito further teaches the IC chip of claim 28, wherein each of the first plurality of metal line loops (Liang: fig. 1C, 44S) has a width smaller than about 1 μm (Liang: line width of each of the segments of the body pattern 44S ranges from 0.5 micrometers to 1 micrometer; col. 5, lin. 19-21) and
wherein each of the second plurality of metal line loops (Saito: fig. 3C, M6) has a width (Saito: M6 has more than twice width of M4, which is similar to 44s of Liang with 0.5 micrometers to 1 micrometer, so more than 1 micrometer to 2 micrometer) greater than about 1 μm.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 31, Liang in view of Saito and Ogata further teaches the IC chip of claim 28 including plurality of lateral connectors (Liang: fig. 1C, connectors between 44S).
Liang in view of Saito and Ogata as applied to claim 11 above fails to explicitly teach each of the plurality of lateral connectors is substantially square in shape.
However, Liang teaches each of the plurality of lateral connectors (Liang: fig. 1C, 44S) is substantially square in shape (Liang: from the top view of fig. 1C, connectors between 44S appears to be a square shape).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the substantially square in shape.
Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 32, Liang in view of Saito and Ogata further teaches the IC chip of claim 28, wherein the first plurality of metal line loops (Liang: fig. 1B and 1C, four 44S in each 33) and the second plurality of metal line loops (Saito: fig. 3C, eight M5, M6 in one ring) comprise between about 4 and about 20 metal line loops.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 34, Liang in view of Saito and Ogata further teaches the IC chip of claim 28, wherein the plurality of lateral connectors (Liang: fig. 1C, connectors between neighbor 44S) are aligned along a direction (Liang: direction perpendicular 44S).
Regarding claim 35, Liang in view of Saito and Ogata further teaches the IC chip of claim 28, wherein the first plurality of metal line loops (Liang: fig. 1C, 44S), the plurality of lateral connectors (Liang: connectors between neighbor 44S), and the second plurality of metal line loops (Liang: 54) are formed of the same material (Liang: 44 and 54 are same metallic materials; col. 3, lin. 34-38 and col. 6, lin. 30-33).
Claim 29 is rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito and Ogata as applied to claim 28 above, and further in view of Hosoda.
Regarding claim 38, Liang in view of Saito and Ogata further teaches the IC chip of The IC chip of 28,
wherein a lower metal layer (Liang: fig. 1B, 44S in lower level 44) in the first group of metal layers (Liang: 44) comprises a first metal line loop (Liang: left via rings 46R in lower level 44; col. 5, lin. 64-65) and a second metal line loop (Liang: nearest 46V in lower level 44),
wherein an upper metal layer (Liang: 44S in upper level 44) in the first group of metal layers (Liang: 44) comprises a third metal line loop (Liang: left 46R in upper level 44) directly over the first metal line loop (Liang: left 46R in lower level 44) and a fourth metal line loop (Liang: nearest 46V in upper level 44) directly over the second metal line loop (Liang: nearest 46V in lower level 44),
wherein a via bar (Liang: via ring 46R) is disposed vertically between the first metal line loop (Liang: left 46R in lower level 44) and the third metal line loop (Liang: left 46R in upper level 44).
Liang in view of Saito and Ogata fails to explicitly teach no conductive features are present between the second metal line loop and the fourth metal line loop along a vertical direction.
However, Hosoda teaches no conductive features (Hosoda: fig. 5, no conductive features) are present between the second metal line loop (Hosoda: dummy patterns 50b; para. 0047, similar to 46V in lower level 44 of Liang) and the fourth metal line loop (Hosoda: dummy patterns 46b; para. 0047, similar to 46V in upper level 44 of Liang) along a vertical direction (vertical direction).
Hosoda, Ogata, Saito and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add detail of no conductive features are present between the second metal line loop and the seventh metal line loop along a vertical direction as taught by Hosoda.
Doing so would realize less via through inter-layer insulating films and the generation of cracks and peelings in the interface between the inter-layer insulating films or in the insulating film due to stresses generated at the end of the guard ring can be effectively prevented (Hosoda: para. 0015).
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito and Ogata as applied to claim 28 above, and further in view of Furusawa et al. (US 20090189245).
Regarding claim 33, Liang in view of Saito and Ogata teaches the IC chip of The IC chip of 28 including the ring region (Liang: fig. 1A, 30).
Liang in view of Saito and Ogata fails to explicitly teach the substrate further comprises four inner corner regions, and
wherein the ring region surrounds the device region and the four inner corner regions.
However, Furusawa teaches the substrate (Furusawa: fig. 7 and 12, semiconductor device substrate 100; para. 0028, similar to 10 of Liang) further comprises four inner corner regions (Furusawa: four inner corner regions of sacrifice pattern group 14 of 100; para. 0042), and
wherein the ring region (Furusawa: outer seal ring 25; para. 0053, similar to 30 of Liang) surrounds the device region (Furusawa: center of the chip) and the four inner corner regions (Furusawa: 14 of 100).
Furusawa, Ogata, Saito and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add detail of four inner corner regions and four inner corner portions as taught by Furusawa.
Doing so would realize four inner corners as a structure in wall for preventing the progress of cracks outside from the center of the chip (Furusawa: para. 0035, 0054).
Claims 36-37 and 40-41 are rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito.
Regarding claim 36, Liang teaches an integrated circuit (IC) chip (integrated circuit structure; Abstract), comprising:
a substrate (fig. 1A, substrate 10; col. 2, lin. 31) including a device region (active region 10A; col. 2, lin. 54) and a ring region (seal ring region 10S; col. 2, lin. 54) surrounding the device region (10A); and
an interconnect structure (seal ring structure 30 and metal interconnect layers (not shown) around semiconductor die 11 and; col. 2, lin. 55-58) disposed over the substrate (10) and comprising a device portion (metal interconnect layers in 10A (not shown) around semiconductor die 11 and; col. 2, lin. 55-56) disposed directly over the device region (10A) and a ring portion (seal ring structure 30; col. 2, lin. 57-58) disposed directly over the ring region (10S), the ring portion (30) of the interconnect structure comprising a plurality of seal ring walls (third seal rings 33; col. 4, lin. 8) interleaved by a plurality of metal-free zones (zone between 33), each of the plurality of seal ring walls (33) including a first group of metal layers (fig. 1C, body pattern 44S of metal layers 44 in third seal ring 33; col. 4, lin. 31-34) and a second group of metal layers (fig. 1B, metal layer 54; Col. 6, Lin. 17-18) directly over the first group of metal layers (44),
wherein each of the first group of metal layers (44) comprises:
a first plurality of metal line loops (body pattern 44S) fully surrounding the device portion (11) of the interconnect structure, and
a plurality of lateral connectors (connectors between neighbor 44S) sandwiched between two adjacent metal line loops (44S) of the first plurality of metal line loops,
wherein each of the second group of metal layers (54) comprises a second plurality of metal line loops (54 of 33) fully surrounding the device portion (11) of the interconnect structure,
wherein the first plurality of metal line loops (Liang: fig. 1B and 1C, four 44S in each 33) comprise between about 4 and about 20 metal line loops.
Liang fails to explicitly teach the second plurality of metal line loops are laterally spaced apart from one another,
wherein each of the second group of metal layers is free of any lateral connectors sandwiched between the second plurality of metal line loops,
wherein the second plurality of metal line loops comprise between about 4 and about 20 metal line loops.
However, Saito teaches the second plurality of metal line loops (Saito: fig. 5B, wiring layers M5 and M6; para. 0070, similar to 54 of Liang) are laterally spaced apart from one another (Saito: M5 or M6 laterally spaced without lateral connectors),
wherein each of the second group of metal layers (Saito: M5 and M6) is free of any lateral connectors (Saito: M5 or M6 without lateral connectors) sandwiched between the second plurality of metal line loops (Saito: M5 and M6),
wherein the second plurality of metal line loops (Saito: fig. 3C, eight M5, M6 in one ring) comprise between about 4 and about 20 metal line loops.
Saito and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the second group of metal layers is free of any lateral connectors as taught by Saito.
Doing so would realize wider wiring patterns to better cover the thin wiring layers to provide higher moisture resistance (Saito: para. 0162).
Regarding claim 37, Liang in view of Saito further teaches the IC chip of claim 36, wherein each of the first plurality of metal line loops (Liang: fig. 1C, 44S) has a width smaller than about 1 μm (Liang: line width of each of the segments of the body pattern 44S ranges from 0.5 micrometers to 1 micrometer; col. 5, lin. 19-21) and
wherein each of the second plurality of metal line loops (Saito: fig. 3C, M6) has a width (Saito: M6 has more than twice width of M4, which is similar to 44s of Liang with 0.5 micrometers to 1 micrometer, so more than 1 micrometer to 2 micrometer) greater than about 1 μm.
Furthermore, it has been held that where the claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 40, Liang in view of Saito further teaches the IC chip of claim 36 including plurality of lateral connectors (Liang: fig. 1C, connectors between 44S).
Liang in view of Hosoda and Saito as applied to claim 11 above fails to explicitly teach each of the plurality of lateral connectors is substantially square in shape.
However, Liang teaches each of the plurality of lateral connectors (Liang: fig. 1C, 44S) is substantially square in shape (Liang: from the top view of fig. 1C, connectors between 44S appears to be a square shape).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the substantially square in shape.
Here the general conditions of a claim are disclosed in the prior art, a change in shape is generally recognized as being within the level of ordinary skill in the art. In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 41, Liang in view of Saito further teaches the IC chip of claim 36, wherein the plurality of lateral connectors (Liang: fig. 1C, connectors between neighbor 44S) are aligned along a direction (Liang: direction perpendicular 44S).
Claim 38 is rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito as applied to claim 36 above, and further in view of Hosoda.
Regarding claim 38, Liang in view of Saito further teaches the IC chip of The IC chip of 36,
wherein the second plurality of metal line loops (Liang: fig. 1B, 54) are disposed directly over the first plurality of metal line loops (Liang: 44),
wherein a lower metal layer (Liang: fig. 1B, 44S in lower level 44) in the first group of metal layers (Liang: 44) comprises a first metal line loop (Liang: left via rings 46R in lower level 44; col. 5, lin. 64-65) and a second metal line loop (Liang: nearest 46V in lower level 44),
wherein an upper metal layer (Liang: 44S in upper level 44) in the first group of metal layers (Liang: 44) comprises a third metal line loop (Liang: left 46R in upper level 44) directly over the first metal line loop (Liang: left 46R in lower level 44) and a fourth metal line loop (Liang: nearest 46V in upper level 44) directly over the second metal line loop (Liang: nearest 46V in lower level 44),
wherein a via bar (Liang: via ring 46R) is disposed vertically between the first metal line loop (Liang: left 46R in lower level 44) and the third metal line loop (Liang: left 46R in upper level 44).
Liang in view of Saito fails to explicitly teach no conductive features are present between the second metal line loop and the fourth metal line loop along a vertical direction.
However, Hosoda teaches no conductive features (Hosoda: fig. 5, no conductive features) are present between the second metal line loop (Hosoda: dummy patterns 50b; para. 0047, similar to 46V in lower level 44 of Liang) and the fourth metal line loop (Hosoda: dummy patterns 46b; para. 0047, similar to 46V in upper level 44 of Liang) along a vertical direction (vertical direction).
Hosoda, Saito and Liang are considered to be analogous to the claimed invention because they are in the same field of seal rings.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add detail of no conductive features are present between the second metal line loop and the seventh metal line loop along a vertical direction as taught by Hosoda.
Doing so would realize less via through inter-layer insulating films and the generation of cracks and peelings in the interface between the inter-layer insulating films or in the insulating film due to stresses generated at the end of the guard ring can be effectively prevented (Hosoda: para. 0015).
Claim 39 is rejected under 35 U.S.C. 103 as being unpatentable over Liang in view of Saito as applied to claim 36 above, and further in view of Ogata.
Regarding claim 39, Liang in view of Saito further teaches the IC chip of claim 36 including the first group of metal layers (Liang: fig. 1B, 44).
Liang in view of Saito fails to explicitly teach the first group of metal layers consists of five (5) metal layers, and
wherein the second group of metal layers consists of four (4) metal layers.
However, Ogata teaches the first group of metal layers (Ogata: fig. 1, Second to sixth wiring layers M2~M6 have almost the same structure; para. 0076, similar to 44 of Liang) consists of five (5) metal layers (Ogata: M2~M6 5 layers), and
wherein the second group of metal layers (seventh wiring layer M7, eighth wiring layer M8 have the same structure and the number of layers can be set to be 3 and ninth wiring layer M9; para. 0077, 0078, similar to 54 of Liang) consists of four (4) metal layers (Ogata: 4 layers of 3 layers M7, M8 and M9).
Saito, Hosoda and Liang are considered to be analogous to the claimed invention because they are in the same field of seal ring regions.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to add the first group of metal layers consists of five (5) metal layers and the second group of metal layers consists of four (4) metal layers.
Doing so would realize a wiring rings structure to improve the mechanical strength of the periphery (Ogata: para. 0137).
Response to Arguments
Applicant’s arguments with respect to claims 11-16 and 28-41 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIJUN XU whose telephone number is (571)270-3447. The examiner can normally be reached Monday-Thursday 9am-5pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ZHIJUN XU/Examiner, Art Unit 2818
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights