DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Amendment filed April 29, 2026 is acknowledged. New claim 28 has been added. Claim 14 has been cancelled. Claims 1, 13, 16 and 21 have been amended. Non-elected Species, claim 11 has been withdrawn from consideration. Claims 1, 3-13, 16-17, 21-23 and 26-28 are pending.
Action on merits of claims 1, 3-10, 12-13, 16-17, 21-23 and 26-28 follows.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 21 and May 12, 2026 were filed after the mailing date of the Office Action on February 05, 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 3-10, 12-13, 16-17, 21-23, 26 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over CHANG (US. Patent No. 10,290,701) in view of LIN et al. (US. Pub. No. 2021/0074805) and SATO et al. (US. Pub. No. 2004/0222493) all of record.
With respect to claim 1, CHANG teaches a method of forming a semiconductor device as claimed including:
forming a transistor (not shown) over a substrate (300);
forming an interconnect structure (304) over the transistor and the substrate;
forming an etch stop layer (308) over the interconnect structure;
forming a first multi-layered structure (310) over the etch stop layer (308),
patterning the first multi-layered structure (310) to form a first electrode (312), wherein the first electrode (312) is a bottommost electrode of a metal-insulator-metal (MIM) capacitor;
forming a first dielectric layer (320) over the first electrode (312);
forming a second multi-layered structure (330) over the first dielectric layer (320), the second multi-layered structure (330) having the same layered structure as the first multi-layered structure (312); and
patterning the second multi-layered structure (330) to form a second electrode (332), wherein the second electrode (332) is a middle electrode of the MIM capacitor. (See FIGs. 4A-8).
Thus, CHANG is shown to teach all the features of the claim with the exception of explicitly disclosing forming the first multi-layered structure comprising a diffusion barrier between the first and second conductive layer.
However, LIN teaches a method for forming a semiconductor device including:
forming a first multi-layered structure (108) over an etch stop layer (102), comprising:
forming a first conductive layer (110a) over the etch stop layer;
forming a diffusion barrier of an amorphous material (112) on an upper portion of the first conductive layer (110a); and
forming a second conductive layer (110b) over the amorphous material (112), wherein the second conductive layer (110b) contact and extends along the amorphous material (112), wherein the second conductive layer (110b) is the polycrystalline material, wherein the first conductive layer (110a) and the second conductive layer (110b) are formed to have a same thickness using a same deposition method. (See at least FIG. 1C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first multi-layered structure of CHANG comprising the diffusion barrier of amorphous material between the first and second conductive layer as taught by LIN to prevent breakdown of the capacitor dielectric layer.
Further, SATO teaches a method for forming a diffusion barrier between a first and second conductive layer including:
forming a first multi-layered structure over an etch stop layer (11), comprising:
forming a first conductive layer (12) over the etch stop layer (11);
converting an upper portion of the first conductive layer (12) into an amorphous material (25) by treating the upper portion of the first conductive layer (12) with a plasma process (13).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the diffusion barrier layer of amorphous material of LIN including plasma treating the of the upper portion of the first conductive layer as taught by SATO to prevent leakage current.
With respect to claim 3, in view of SATO, the plasma process is performed using a gas source comprising nitrogen gas or a noble gas.
With respect to claim 4, in view of LIN, the first conductive layer (204a) and the second conductive layer (204b) are formed using physical vapor deposition (PVD).
With respect to claim 5, the first dielectric layer (320) of CHANG or LIN or SATO is formed of a high-k dielectric material.
With respect to claim 6, the first electrode (312) of CHANG covers a first portion of the etch stop layer (308) and exposes a second portion of the etch stop layer, wherein the first dielectric layer (320) is formed conformally over the first electrode (312) and over the second portion of the etch stop layer (308). (See FIGs. 5-6).
With respect to claim 7, the second electrode (332) of CHANG is formed to have a stair shaped cross-section, wherein a first portion of the second electrode (332) is laterally adjacent to the first electrode (312), and a second portion of the second electrode (332) extends along an upper surface of the first electrode (312) distal from the substrate.
With respect to claim 8, the second portion of the second electrode (332) of CHANG exposes a first portion of the first dielectric layer (320) at the upper surface of the first electrode (312). (See FIG. 8).
With respect to claim 9, the method of CHANG further including:
forming a second dielectric layer (340) over a second electrode (332) and over an exposed first portion of a first dielectric layer (320), wherein the second dielectric layer (340) comprises:
a first portion extending along the exposed first portion of the first dielectric layer (320);
a second portion extending along an upper surface of the second portion of the second electrode (332) distal from the substrate; and
a third portion extending along an upper surface of the first portion of the second electrode (312) distal from the substrate; and
forming a third electrode (352) over the second dielectric layer (340), wherein the third electrode (352) is atop electrode of the MIM capacitor (30), wherein the third electrode (352) is formed to have a stair shaped stair shaped cross-section, wherein a first portion of the third electrode (352) is laterally adjacent to the second portion of the second electrode (332) and extends along the first portion of the second dielectric layer (320), and a second portion of the third electrode (352) extends along the upper surface of the second portion of the second electrode (332) distal from the substrate, wherein the second portion of the third electrode (352) covers a first region of the second portion of the second dielectric layer (340) and exposes a second region of the second portion of the second dielectric layer. (See FIG. 11).
With respect to claim 10, forming the third electrode (352) of CHANG comprises: forming a third multi-layered structure (350) over the second dielectric layer (340), the third multi-layered structure (350) having the same layered structure as the first multi-layered structure (310); and
patterning the third multi-layered structure (350) to form the third electrode (352).
With respect to claim 12, the method of CHANG further comprises:
forming a first via (380) that extends through the first portion of the second electrode (332); and
forming a second via (380) that extends through the first portion of the third electrode (352) and the first electrode (312). (See FIG. 13).
With respect to claim 26, in view of SATO, the upper portion of the first conductive layer (12) is converted into the amorphous material by a single treatment process, wherein the single treatment process is the plasma process.
With respect to claim 13, CHANG method of forming a semiconductor device substantially as claimed, the method including:
forming a transistor (not shown) over a substrate;
forming an etch stop layer (308) over the transistor and the substrate; and
forming metal-insulator-metal (MIM) capacitors over the etch stop layer, comprising:
forming a bottom electrode (312) over the etch stop layer (308), wherein the bottom electrode (312) has a layered structure and comprises a first conductive layer (310b-1), a second conductive layer (310b-2), wherein the bottom electrode (312) is formed to cover a first portion of the etch stop layer (308) and expose a second portion of the etch stop layer (308);
forming a first dielectric layer (320) over the second portion of the etch stop layer (308) and over the bottom electrode (312);
forming a middle electrode (332) over the first dielectric layer (320);
forming a second dielectric layer (340) over the middle electrode (33); and
forming a top electrode (352) over the second dielectric layer (340). (See FIGs. 4A-11).
Thus, CHANG is shown to teach all the features of the claim with the exception of explicitly disclosing the bottom electrode comprising a third conductive layer.
However, LIN teaches a method of forming a semiconductor device including:
forming a bottom electrode (202) over an etch stop layer (102), wherein the bottom electrode has a layered structure and comprises a first conductive layer (204a), a second conductive layer (204b), and a third conductive layer (206) in-between, wherein the third conductive layer (206) is in physical contact with the first conductive layer (204a) and the second conductive layer (204b), wherein the first conductive layer (204a) and the second conductive layer (204b) are a polycrystalline material and are formed to have a same thickness using a same deposition method, and the third conductive layer (206) is an amorphous material, wherein the bottom electrode (202) is formed to cover a first portion of the etch stop layer (102) and expose a second portion of the etch stop layer. (See FIG. 2B).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the bottom electrode of CHANG including the third conductive layer in-between, and is in physical contact with the first conductive layer and the second conductive layer as taught by LIN to prevent breakdown of the capacitor dielectric layer.
Further, SATO teaches a method for forming a third conductive layer in physical contact with a first conductive layer (12) and a second conductive layer (37) including:
forming a bottom electrode over an etch stop layer (11), wherein the bottom electrode has a layered structure and comprises a first conductive layer (12), a second conductive layer (37), and a third conductive layer (25) in-between, wherein the third conductive layer (25) is in physical contact with the first conductive layer (12) and the second conductive layer (37), and the third conductive layer (25) is an amorphous material formed by converting an upper portion of the first conductive layer (12) into the amorphous material using a plasma process (13), wherein the bottom electrode is formed to cover a first portion of the etch stop layer (11) and expose a second portion of the etch stop layer. (See FIGs. 14A-C, 15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the third conductive layer of LIN including converting the upper portion of the first conductive layer into the amorphous material using a plasma process as taught by SATO to prevent leakage current.
With respect to claim 16, the middle electrode (332) of CHANG, is formed to have the same layered structure as the bottom electrode (312), wherein the middle electrode (332) has a first stair shaped cross-section, and the top electrode (352) has a second stair shaped cross-section, wherein the first dielectric layer (320) is partially covered by the middle electrode (332), and the second dielectric layer (340) is partially covered by the top electrode (312).
With respect to claim 17, the method of CHANG further comprises:
forming a first via (380) that extends through the first dielectric layer (320), the second dielectric layer (340), and the middle electrode (332); and
forming a second via (380) that extends through the first dielectric layer (320), the second dielectric layer (340), the bottom electrode (312), and the top electrode (352). (See FIG. 13).
With respect to claim 28, the bottom electrode (312) of CHANG is closer to the substrate (300) than other electrodes of the MIM capacitor.
With respect to claim 21, CHANG teaches a method of forming a semiconductor device substantially as claimed including:
forming a transistor (not shown) over a substrate;
forming an interconnect structure (304) over the substrate;
forming an etch stop layer (308) over the interconnect structure (304);
forming a first multi-layered structure (310b) over the etch stop layer (308), comprising:
forming a first conductive layer (310b-1) over the etch stop layer, the first conductive layer (310b-1) comprising a polycrystalline material; and
forming a third conductive layer (310b-2) over the first conductive layer (310b-1), the third conductive layer (310b-2) comprising the polycrystalline material, wherein the first conductive layer (310b-1) and the third conductive layer (310b-2) are formed;
patterning the first multi-layered structure (310b) to form a first electrode (312), wherein the first electrode (312) is a bottom electrode of a metal-insulator-metal (MIM) capacitor;
forming a first dielectric layer (320) over the first electrode (312);
forming a second multi-layered structure (330b) over the first dielectric layer (320), the second multi-layered structure (330b) having the same layered structure as the first multi-layered structure (310b); and
patterning the second multi-layered structure (330b) to form a second electrode (332), wherein the second electrode (332) is a middle electrode of the MIM capacitor. (See FIGs. 4B-8).
Thus, CHANG is shown to teach all the features of the claim with the exception of explicitly disclosing converts the upper portion of the first conductive layer into a second conductive layer.
However, LIN teaches a method of forming a semiconductor device including:
forming a first multi-layered structure (108) over the etch stop layer (104), comprising:
forming a first conductive layer (110a) over an etch stop layer (102), the first conductive layer (110a) comprising a polycrystalline material;
forming on an upper portion of the first conductive layer (110a) a second conductive layer (112) by performing a process, the second conductive layer (112) comprising an amorphous material; and
forming a third conductive layer (110b) that contacts and extend along the second conductive layer (112), the third conductive layer (110b) comprising the polycrystalline material, wherein the first conductive layer (110a) and the third conductive layer (110b) are formed to have a same thickness using a same deposition method;
patterning the first multi-layered structure (108) to form a first electrode (108). (See Fig. 1C).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the first multi-layered structure of CHANG including the second conductive layer comprising the amorphous material as taught by LIN to prevent breakdown of the capacitor dielectric layer.
Further, SATO teaches a method for forming a second conductive layer comprising an amorphous material including:
forming a first conductive layer (12) over an etch stop layer (11), the first conductive layer comprising a polycrystalline material;
converting an upper portion of the first conductive layer (12) into a second conductive layer (25) by performing a plasma process (13), the second conductive layer (25) comprising an amorphous material; and
forming a third conductive layer (37) that contacts and extends along the second conductive layer (25). (See FIG. 14C-15).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second conductive layer of LIN including converting the upper portion of the first conductive layer by performing the plasma process as taught by SATO to prevent leakage current.
With respect to claim 22, the first electrode (312) of CHANG covers a first portion of the etch stop layer (308) and exposes a second portion of the etch stop layer, wherein the first dielectric layer (320) is formed over the exposed second portion of the etch stop layer (308) and the first electrode (312), wherein a first portion of the second electrode (332) is formed to be laterally adjacent to the first electrode (312), and a second portion of the second electrode (332) is formed to extend along an upper surface of the first electrode (312) distal from the substrate, wherein the second portion of the second electrode (332) exposes a first portion of the first dielectric layer (320). (See FIG. 8).
With respect to claim 23, method of CHANG further including:
forming a second dielectric layer (340) over the second electrode (332) and the first dielectric layer (320), wherein the second dielectric layer (340) is formed to include:
a first portion extending along the exposed first portion of the first dielectric layer (320);
a second portion extending along an upper surface of the second portion of the second electrode (332) distal from the substrate; and
a third portion extending along an upper surface of the first portion of the second electrode (332) distal from the substrate; and
forming a third electrode (352) over the second dielectric layer (340), wherein the third electrode (352) is a top electrode of the MIM capacitor, wherein a first portion of the third electrode (352) is formed to be laterally adjacent to the second portion of the second electrode (332), and a second portion of the third electrode (352) is formed to extend along an upper surface of the second portion of the second electrode (332) distal from the substrate, wherein a sidewall of the second portion of the third electrode (352) laterally distal from the first portion of the third electrode (352) is disposed between a first sidewall of the second portion of the second electrode (332) and a second opposing sidewall of the second portion of the second electrode (332). (See FIG. 11).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over CHANG ‘701, LIN ‘805 and SATO ‘493 as applied to claim 1 above, and further in view of LIN et al. (US. Pub. No. 2021/0091169).
In view of SATO, the plasma process is performed for a duration between about 5 seconds and about 30 seconds, and a radio frequency (RF) power of the plasma process.
Thus, CHANG ‘701, LIN ‘805 and SATO, are shown to teach all the features of the claim with the exception of explicitly disclosing the radio frequency (RF) power of the plasma process being between about 30 W and about 300 W.
However, LIN ‘169 teaches a method of forming a semiconductor device utilizing a plasma treatment to smoot out rough surface of a first conductive layer (1702), wherein the plasma treatment being performed for a duration of between 5-15 seconds, and a radio (RF) power is between 200-300 watts. (See FIG. 19).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to perform the plasma treatment of the surface of the first conductive layer of LIN, in view of SATO, at the duration and RF power as taught by LIN ‘169 to smooth out the surface roughness of the first conductive layer.
Response to Arguments
Applicant’s arguments with respect to amended and new claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANH D MAI/ Primary Examiner, Art Unit 2893
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