DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on November 17, 2025 has been entered.
Status of the Claims
Amendment filed November 17, 2025 is acknowledged. New claims 26-27 have been added. Claims 2 and 25 have been cancelled. Claims 1, 3-4, 9-10, 13 and 21-23 have been amended. Non-elected Species, claim 11 has been withdrawn from consideration. Claims 1, 3-14, 16-17, 21-23 and 26-27 are pending.
Action on merits of claims 1, 3-10, 12-14, 16-17, 21-23 and 26-27 follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-8, 13-14, 16-17, 21-22 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over LIN et al. (US. Pub. No. 2021/0074805), in view of SATO et al. (US. Pub. No. 2004/0222493) both of record.
With respect to claim 1, LIN ‘805 teaches a method of forming a semiconductor device substantially as claimed including:
forming a transistor (308) over a substrate;
forming an interconnect structure (312) over the transistor and the substrate;
forming an etch stop layer (510) over the interconnect structure;
forming a first multi-layered structure over the etch stop layer, comprising:
forming a first conductive layer (204a) over the etch stop layer, wherein the first conductive layer (204a) is a polycrystalline material;
treating the upper portion of the first conductive layer (204a); and
forming a second conductive layer (204b) over the first conductive layer (204a), wherein the second conductive layer is the polycrystalline material, wherein the first conductive layer and the second conductive layer are formed to have a same thickness using a same deposition method;
patterning the first multi-layered structure to form a first electrode (202), wherein the first electrode (202) is a bottom electrode of a metal-insulator-metal (MIM) capacitor;
forming a first dielectric layer (208) over the first electrode (202),
forming a second multi-layered structure (108) over the first dielectric layer (208), the second multi-layered structure (108) having the same layered structure as the first multi-layered structure (202); and
patterning the second multi-layered structure (108) to form a second electrode (108), wherein the second electrode (108) is a middle electrode of the MIM capacitor. (See FIGs. 1A-C, 2A-C).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing converts the upper portion of the first conductive layer into an amorphous material by treating the upper portion of the first conductive layer.
However, SATO teaches a method of forming a semiconductor device including:
forming a first multi-layered structure over an etch stop layer (11), comprising:
forming a first conductive layer (12) over the etch stop layer, wherein the first conductive layer (12) is a polycrystalline material; (FIG. 16A)
converting an upper portion of the first conductive layer (12) into an amorphous material (33) by treating the upper portion of the first conductive layer (12) with a plasma process (13); (FIGs. 16B-C) and
forming a second conductive layer (37) over the treated (33) first conductive layer (12), wherein the second conductive layer (37) is the polycrystalline material. (FIG. 17D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to treat the upper portion of the first conductive layer of LIN with the plasma process as taught by SATO to convert the upper portion of the first conductive layer into the amorphous material to provide a barrier layer so that leakage current is suppressed.
With respect to claim 3, in view of SATO, the plasma process is performed using a gas source comprising nitrogen gas or a noble gas.
With respect to claim 4, the first conductive layer (204a) and the second conductive layer (204b) of LIN are formed using physical vapor deposition (PVD).
With respect to claim 5, the first dielectric layer (208) of LIN or SATO is formed of a high-k dielectric material.
With respect to claim 6, the first electrode (202) of LIN covers a first portion of the etch stop layer and exposes a second portion of the etch stop layer, wherein the first dielectric layer (208) is formed conformally over the first electrode (202) and over the second portion of the etch stop layer.
With respect to claim 7, the second electrode (108) of LIN is formed to have a stair shaped cross-section, wherein a first portion of the second electrode is laterally adjacent to the first electrode (202), and a second portion of the second electrode extends along an upper surface of the first electrode distal from the substrate.
With respect to claim 8, the second portion of the second electrode (108) of LIN exposes a first portion of the first dielectric layer (208) at the upper surface of the first electrode.
With respect to claim 26, in view of SATO, the upper portion of the first conductive layer (12) is converted into the amorphous material by a single treatment process, wherein the single treatment process is the plasma process.
With respect to claim 21, LIN teaches a method of forming a semiconductor device substantially as claimed including:
forming a transistor over a substrate;
forming an interconnect structure over the substrate;
forming an etch stop layer over the interconnect structure;
forming a first multi-layered structure over the etch stop layer, comprising:
forming a first conductive layer (204a) over the etch stop layer, the first conductive layer comprising a polycrystalline material;
treating an upper portion of the first conductive layer (204a) into a second conductive layer (206) by performing a process, the second conductive layer (206) comprising a crystal material; and
forming a third conductive layer (204b) over the second conductive layer (206), the third conductive layer (204b) comprising the polycrystalline material, wherein the first conductive layer (204a) and the third conductive layer (204b) are formed to have a same thickness using a same deposition method;
patterning the first multi-layered structure to form a first electrode (202), wherein the first electrode is a bottom electrode of a metal-insulator-metal (MIM) capacitor;
forming a first dielectric layer (208) over the first electrode (202);
forming a second multi-layered structure (108) over the first dielectric layer (208), the second multi-layered structure (108) having the same layered structure as the first multi-layered structure (202); and
patterning the second multi-layered structure to form a second electrode (108), wherein the second electrode is a middle electrode of the MIM capacitor. (See FIG. 1A-C, 2A-C).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing converts the upper portion of the first conductive layer into an amorphous material by treating the upper portion of the first conductive layer.
However, SATO teaches a method of forming a semiconductor device including:
forming a first multi-layered structure over an etch stop layer (11), comprising:
forming a first conductive layer (12) over the etch stop layer, wherein the first conductive layer (12) is a polycrystalline material; (FIG. 16A)
converting an upper portion of the first conductive layer (12) into a second conductive layer (33) by performing a plasma process (13), the second conductive layer (33) comprising an amorphous material; (FIGs. 16B-C) and
forming a third conductive layer (37) over the second conductive layer (33), the third conductive layer (37) is a polycrystalline material. (FIG. 17D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the second conductive layer of LIN by converting the upper portion of the first conductive layer utilizing the plasma process as taught by SATO to convert the upper portion of the first conductive layer into the amorphous material to provide a barrier layer so that leakage current is suppressed.
With respect to claim 22, the first electrode (202) of LIN covers a first portion of the etch stop layer and exposes a second portion of the etch stop layer, wherein the first dielectric layer (208) is formed over the exposed second portion of the etch stop layer and the first electrode (202), wherein a first portion of the second electrode (108) is formed to be laterally adjacent to the first electrode (202), and a second portion of the second electrode (108) is formed to extend along an upper surface of the first electrode (202) distal from the substrate, wherein the second portion of the second electrode (108) exposes a first portion of the first dielectric layer (208). (See FIGs. 9-10).
Claim 27 is rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 and SATO ‘493 as applied to claim 1 above, and further in view of LIN et al. (US. Pub. No. 2021/0091169).
In view of SATO, the plasma process is performed for a duration between about 5 seconds and about 30 seconds, and a radio frequency (RF) power of the plasma process.
Thus, LIN ‘805, in view of SATO, is shown to teach all the features of the claim with the exception of explicitly disclosing the radio frequency (RF) power of the plasma process being between about 30 W and about 300 W.
However, LIN ‘169 teaches a method of forming a semiconductor device utilizing a plasma treatment to smoot out rough surface of a first conductive layer (1702), wherein the plasma treatment being performed for a duration of between 5-15 seconds, and a radio (RF) power is between 200-300 watts. (See FIG. 19).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to perform the plasma treatment of the surface of the first conductive layer of LIN, in view of SATO, at the duration and RF power as taught by LIN ‘169 to smooth out the surface roughness of the first conductive layer.
Claims 9-10, 12 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805 and SATO ‘493 as applied to claims 8 and 22 above, and further in view of CHILDS et al. (US. Pub. No. 2013/0270675).
With respect to claim 9, LIN, in view of SATO, teaches the method as described in claim 8 above including the second portion of the second electrode exposes a first portion of the first dielectric layer at the upper surface of the first electrode.
Thus, LIN, in view of SATO, is shown to teach all the features of the claim with the exception of explicitly disclosing the method further comprising forming a second dielectric layer over the second electrode and over the exposed first portion of the first dielectric layer.
However, CHILDS teaches a method for forming a semiconductor device including:
forming a second dielectric layer (132) over a second electrode (130) and over an exposed first portion of a first dielectric layer (128), wherein the second dielectric layer (132) comprises:
a first portion extending along the exposed first portion of the first dielectric layer (128);
a second portion extending along an upper surface of the second portion of the second electrode (130) distal from the substrate; and
a third portion extending along an upper surface of the first portion of the second electrode (130) distal from the substrate; and
forming a third electrode (134) over the second dielectric layer (130), wherein the third electrode (134) is atop electrode of the MIM capacitor (100), wherein the third electrode (134) is formed to have a stair shaped stair shaped cross-section, wherein a first portion of the third electrode (134) is laterally adjacent to the second portion of the second electrode (130) and extends along the first portion of the second dielectric layer (132), and a second portion of the third electrode (134) extends along the upper surface of the second portion of the second electrode (130) distal from the substrate, wherein the second portion of the third electrode (134) covers a first region of the second portion of the second dielectric layer (132) and exposes a second region of the second portion of the second dielectric layer. (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the MIM capacitor of LIN having third electrodes formed over the second dielectric layer as taught by as taught by CHILDS for the same intended purpose of providing a high capacity MIM capacitor.
Note that, the stacked MIM capacitor, FIG. 7, of LIN is similarly formed.
With respect to claim 10, in view of CHILDS, forming the third electrode (134) comprises: forming a third multi-layered structure (134) over the second dielectric layer (132), the third multi- layered structure (134) having the same layered structure as the first multi-layered structure (128); and
patterning the third multi-layered structure (134) to form the third electrode (134).
With respect to claim 12, the method of LIN or CHILDS further comprises:
forming a first via (506b) that extends through the first portion of the second electrode; and
forming a second via (506a) that extends through the first portion of the third electrode and the first electrode (312). (See FIG. 7).
With respect to claim 23, LIN ‘805, in view of SATO, teaches the method as described in claim 22 above including:
forming a second dielectric layer (510) over the second electrode (108) and the first dielectric layer (208), wherein the second dielectric layer (510) is formed to include:
a first portion extending along the exposed first portion of the first dielectric layer (208);
a second portion extending along an upper surface of the second portion of the second electrode (108) distal from the substrate; and
a third portion extending along an upper surface of the first portion of the second electrode (108) distal from the substrate. (See FIGs. 9-10).
Thus, LIN and SATO are shown to teach all the features of the claim with the exception of explicitly further disclosing forming a third electrode over the second dielectric layer.
However, CHILDS teaches a method of forming a semiconductor device including:
forming a third electrode (134) over a second dielectric layer (132), wherein the third electrode (134) is a top electrode of a MIM capacitor, wherein a first portion of the third electrode (132) is formed to be laterally adjacent to the second portion of the second electrode (130), and a second portion of the third electrode (134) is formed to extend along an upper surface of the second portion of the second electrode (130) distal from the substrate, wherein a sidewall of the second portion of the third electrode (134) laterally distal from the first portion of the third electrode is disposed between a first sidewall of the second portion of the second electrode (130) and a second opposing sidewall of the second portion of the second electrode (130). (See FIG. 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN, in view of SATO, including the second dielectric layer and the third electrode over the second electrode as taught by CHILDS for the same intended purpose of providing a high capacity MIM capacitor.
Note that, the stacked MIM capacitor, FIGs.9-10, of LIN is similarly formed.
Claim 13-14 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over LIN ‘805, in view of SATO ‘493 and CHILDS ‘675.
With respect to claim 13, LIN ‘805 teaches a method of forming a semiconductor device substantially as claimed including:
forming a transistor over a substrate;
forming an etch stop layer over the transistor and the substrate; and
forming metal-insulator-metal (MIM) capacitors (700) over the etch stop layer, comprising:
forming a bottom electrode (202) over the etch stop layer, wherein the bottom electrode has a layered structure and comprises a first conductive layer (204a), a second conductive layer (204b) and a third conductive layer (112) in between, wherein the first conductive layer (204a) and the second conductive layer (204b) are a polycrystalline material, and are formed to have a same thickness using a same deposition method, and the third conductive layer (112) is a material formed using a treatment process, wherein the bottom electrode (204a) is formed to cover a first portion of the etch stop layer and expose a second portion of the etch stop layer;
forming a first dielectric layer (208) over the second portion of the etch stop layer and over the bottom electrode (204a);
forming a middle electrode (108) over the first dielectric layer (208). (See FIGs. 1A-C, 2A-C and 9-10).
Thus, LIN is shown to teach all the features of the claim with the exception of explicitly disclosing the third conductive layer is an amorphous material formed by using a plasma process and forming a second dielectric layer and a top electrode over the middle electrode.
However, SATO teaches a method of forming a semiconductor device including:
forming a bottom electrode over an etch stop layer (11), wherein the bottom electrode has a layered structure and comprises a first conductive layer (12), a second conductive layer (37) and a third conductive layer (33) in between, wherein the first conductive layer (12) and the second conductive layer (37) are a polycrystalline material, and the third conductive layer (33) is an amorphous material formed by using a plasma process, wherein the bottom electrode (12) is formed to cover a first portion of the etch stop layer. (See FIGs. 16A-17D).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the third conductive layer of LIN of the amorphous material formed by utilizing the plasma process as taught by SATO to convert the upper portion of the first conductive layer into the amorphous material to provide a barrier layer so that leakage current is suppressed.
Further, CHILDS teaches a method of forming a semiconductor device including:
forming a bottom electrode (126) over an etch stop layer (124), wherein the bottom electrode (126) is formed to cover a first portion of the etch stop layer (124) and expose a second portion of the etch stop layer;
forming a first dielectric layer (128) over the second portion of the etch stop layer and over the bottom electrode (126);
forming a middle electrode (130) over the first dielectric layer (128);
forming a second dielectric layer (132) over the middle electrode (130); and
forming a top electrode (134) over the second dielectric layer (132). (See FIG 1).
Therefore, it would have been obvious to one having ordinary skill in the art at the time of invention was made to form the semiconductor device of LIN including the second dielectric layer and the top electrode over the middle electrode as taught by CHILDS for the same intended purpose of providing a high capacity MIM capacitor.
Note that, the stacked MIM capacitor, FIGs. 9-10, of LIN is similarly formed.
With respect to claim 14, in view of SATO, forming the bottom electrode comprises:
forming a first layer (12) of the polycrystalline material over the etch stop layer using the deposition method;
converting an upper portion of the first layer (12) of the polycrystalline material into the amorphous material (33) using the plasma process (13); and
after the plasma process, forming a second layer (37) of the polycrystalline material over the amorphous material (33), using the deposition method. (See FIG. 17D).
With respect to claim 16, the middle electrode (108) of LIN, is formed to have the same layered structure as the bottom electrode (202), wherein the middle electrode (108) has a first stair shaped cross-section, and in view of CHILDS, the top electrode (134) has a second stair shaped cross-section, wherein the first dielectric layer (128) is partially covered by the middle electrode (130), and the second dielectric layer (132) is partially covered by the top electrode (3). (See FIG. 1).
With respect to claim 17, the method of LIN, FIG.7 or CHILDS, FIG. 1, further comprises:
forming a first via that extends through the first dielectric layer, the second dielectric layer, and the middle electrode; and
forming a second via (506) that extends through the first dielectric layer, the second dielectric layer, the bottom electrode, and the top electrode.
Response to Arguments
Applicant’s arguments with respect to amended and new claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/ANH D MAI/ Primary Examiner, Art Unit 2893